Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

---

Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	6629	1			T1	10		T5	8		T8	34
testmodes[AdcCtrlTestmodeNormal]	5030	1			T1	10		T2	1		T5	9
testmodes[AdcCtrlTestmodeLowpower]	5453	1			T3	11		T6	2		T8	7
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	3663	1			T1	5		T5	4		T8	27
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1611	1			T1	5		T5	4		T8	5
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1247	1			T8	1		T9	16		T49	24
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1579	1			T1	5		T5	4		T8	5
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	1813	1			T1	4		T5	4		T7	1
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1311	1			T8	3		T9	13		T15	1
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1275	1			T8	2		T9	13		T49	22
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1272	1			T8	2		T9	17		T49	21
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2652	1			T3	10		T6	1		T8	3