Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24833

1

T1

20

T2

1

T3

11

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21734

1

T1

20

T2

1

T3

11

auto[ADC_CTRL_FILTER_COND_OUT]

3099

1

T6

40

T7

1

T8

4

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19077

1

T1

20

T3

11

T5

17

auto[1]

5756

1

T2

1

T6

40

T7

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21167

1

T1

20

T2

1

T3

11

auto[1]

3666

1

T6

38

T8

5

T9

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for max_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	59	1			T198	2		T217	9		T99	21
values[1]	621	1			T7	1		T45	23		T140	22
values[2]	604	1			T111	1		T41	7		T160	15
values[3]	791	1			T6	39		T8	5		T9	1
values[4]	507	1			T8	4		T14	1		T150	13
values[5]	478	1			T111	1		T48	23		T183	15
values[6]	646	1			T14	1		T46	19		T140	11
values[7]	745	1			T7	1		T11	12		T14	1
values[8]	2779	1			T2	1		T12	24		T26	22
values[9]	1390	1			T6	40		T11	6		T13	1
minimum	16213	1			T1	20		T3	11		T5	17

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	882	1			T7	1		T45	23		T111	1
values[1]	574	1			T9	1		T218	11		T160	15
values[2]	791	1			T6	39		T8	4		T14	1
values[3]	552	1			T8	5		T48	23		T141	1
values[4]	428	1			T111	1		T182	1		T40	5
values[5]	671	1			T14	1		T46	19		T140	11
values[6]	2947	1			T2	1		T7	1		T11	12
values[7]	569	1			T11	6		T13	1		T139	10
values[8]	1010	1			T6	40		T181	1		T48	21
values[9]	195	1			T146	1		T44	6		T165	14
minimum	16214	1			T1	20		T3	11		T5	17

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20778

1

T1

20

T2

1

T3

11

auto[1]

4055

1

T6

39

T8

2

T11

16

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	328	1			T45	13		T140	10		T41	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T7	1		T111	1		T219	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T218	11		T160	3		T152	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T9	1		T220	1		T42	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T6	19		T14	1		T140	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T8	4		T150	1		T182	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T8	3		T48	12		T221	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T141	1		T152	1		T220	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T111	1		T40	4		T183	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T182	1		T164	1		T136	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T14	1		T136	11		T144	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T46	19		T140	4		T152	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1588	1			T2	1		T7	1		T11	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T14	1		T15	18		T139	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T11	6		T13	1		T139	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T141	1		T175	6		T143	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	334	1			T181	1		T182	1		T164	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T6	22		T48	11		T183	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T44	4		T222	10		T223	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T146	1		T165	8		T224	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16091	1			T1	20		T3	11		T5	17
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T45	10		T140	12		T41	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T40	4		T164	8		T225	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T160	12		T85	9		T162	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T42	4		T226	19		T227	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T6	20		T140	11		T151	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T150	12		T149	12		T16	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T8	2		T48	11		T221	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T43	4		T228	10		T229	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T40	1		T159	5		T188	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T164	1		T136	13		T53	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T136	10		T144	5		T230	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T140	7		T16	1		T231	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	917	1			T205	9		T174	19		T232	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T15	24		T188	2		T233	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T144	6		T83	2		T234	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T143	7		T229	12		T235	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	288	1			T164	16		T225	14		T236	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T6	18		T48	10		T142	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T44	2		T222	8		T223	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T165	6		T224	7		T237	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T8	3		T9	1		T48	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T198	1		T217	9		T99	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T198	1		T238	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T45	13		T140	10		T160	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T7	1		T219	1		T40	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T41	5		T160	3		T152	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T111	1		T220	1		T42	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T6	19		T8	3		T140	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T9	1		T182	1		T149	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T14	1		T154	2		T239	21
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T8	4		T150	1		T164	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T111	1		T48	12		T183	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T53	1		T144	10		T28	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T14	1		T40	4		T136	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T46	19		T140	4		T182	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T7	1		T11	12		T144	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T14	1		T15	18		T139	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1590	1			T2	1		T12	24		T26	22
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T141	1		T183	3		T145	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	414	1			T11	6		T13	1		T181	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	379	1			T6	22		T48	11		T142	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16090	1			T1	20		T3	11		T5	17
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T99	8		T240	10		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T238	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T45	10		T140	12		T160	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T40	4		T164	8		T225	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T41	2		T160	12		T162	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T42	2		T226	10		T235	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T6	20		T8	2		T140	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T149	12		T42	2		T43	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T233	1		T241	13		T178	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T150	12		T164	1		T228	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T48	11		T159	5		T221	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T53	9		T144	9		T165	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T40	1		T136	10		T242	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T140	7		T136	13		T54	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T144	5		T188	9		T230	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T15	24		T188	2		T243	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	899	1			T205	9		T174	19		T232	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T229	12		T235	9		T155	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	358	1			T164	16		T144	6		T225	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T6	18		T48	10		T142	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T8	3		T9	1		T48	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T45	11		T140	13		T41	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T7	1		T111	1		T219	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T218	1		T160	13		T152	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T9	1		T220	1		T42	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T6	21		T14	1		T140	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T8	3		T150	13		T182	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T8	4		T48	12		T221	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T141	1		T152	1		T220	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T111	1		T40	4		T183	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T182	1		T164	2		T136	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T14	1		T136	11		T144	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T46	1		T140	8		T152	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1263	1			T2	1		T7	1		T11	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T14	1		T15	26		T139	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T11	1		T13	1		T139	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T141	1		T175	1		T143	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	341	1			T181	1		T182	1		T164	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T6	19		T48	11		T183	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T44	4		T222	9		T223	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T146	1		T165	9		T224	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16214	1			T1	20		T3	11		T5	17
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T45	12		T140	9		T41	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T40	4		T164	4		T225	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T218	10		T160	2		T85	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T42	4		T226	4		T167	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T6	18		T140	13		T159	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T8	1		T162	6		T244	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T8	1		T48	11		T221	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T43	2		T228	12		T245	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T40	1		T183	14		T159	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T144	9		T54	9		T184	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T136	10		T35	11		T184	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T46	18		T140	3		T231	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1242	1			T11	11		T12	21		T26	20
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T15	16		T139	16		T233	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T11	5		T139	9		T144	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T175	5		T143	2		T155	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T164	11		T225	13		T106	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T6	21		T48	10		T183	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T44	2		T222	9		T246	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T165	5		T237	12		T247	15

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	8	40	83.33	8

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T198	1		T217	1		T99	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T198	1		T238	2		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T45	11		T140	13		T160	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T7	1		T219	1		T40	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T41	4		T160	13		T152	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T111	1		T220	1		T42	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T6	21		T8	4		T140	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T9	1		T182	1		T149	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T14	1		T154	1		T239	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T8	3		T150	13		T164	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T111	1		T48	12		T183	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T53	10		T144	10		T28	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T14	1		T40	4		T136	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T46	1		T140	8		T182	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T7	1		T11	1		T144	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T14	1		T15	26		T139	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1242	1			T2	1		T12	3		T26	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T141	1		T183	1		T145	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	428	1			T11	1		T13	1		T181	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	302	1			T6	19		T48	11		T142	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16213	1			T1	20		T3	11		T5	17
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T217	8		T99	12		T240	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T45	12		T140	9		T160	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T40	4		T164	4		T225	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T41	3		T160	2		T162	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T42	2		T217	5		T226	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T6	18		T8	1		T140	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T162	6		T42	2		T43	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T154	1		T239	20		T192	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T8	1		T228	12		T244	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T48	11		T183	14		T159	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T144	9		T184	10		T165	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T40	1		T136	10		T35	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T46	18		T140	3		T54	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T11	11		T33	1		T248	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T15	16		T139	16		T233	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1247	1			T12	21		T26	20		T47	35
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T183	2		T155	3		T249	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	344	1			T11	5		T164	11		T144	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	316	1			T6	21		T48	10		T175	5

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20778

1

T1

20

T2

1

T3

11

auto[1]

auto[0]

4055

1

T6

39

T8

2

T11

16

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24833

1

T1

20

T2

1

T3

11

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21965

1

T1

20

T2

1

T3

11

auto[ADC_CTRL_FILTER_COND_OUT]

2868

1

T7

2

T8

5

T13

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19244

1

T1

20

T3

11

T5

17

auto[1]

5589

1

T2

1

T6

79

T7

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21167

1

T1

20

T2

1

T3

11

auto[1]

3666

1

T6

38

T8

5

T9

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	23	1			T99	20		T223	3		-	-
values[0]	39	1			T144	6		T250	2		T251	3
values[1]	791	1			T7	1		T11	6		T182	1
values[2]	2879	1			T2	1		T8	4		T12	24
values[3]	606	1			T11	12		T140	11		T182	1
values[4]	622	1			T139	17		T160	15		T144	14
values[5]	624	1			T140	25		T40	7		T164	28
values[6]	585	1			T6	40		T14	1		T181	1
values[7]	690	1			T6	39		T111	1		T48	23
values[8]	700	1			T8	5		T14	1		T15	15
values[9]	1061	1			T7	1		T9	1		T13	1
minimum	16213	1			T1	20		T3	11		T5	17

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1073	1			T7	1		T8	4		T140	22
values[1]	2777	1			T2	1		T11	6		T12	24
values[2]	508	1			T11	12		T40	5		T164	2
values[3]	820	1			T139	17		T142	14		T175	6
values[4]	525	1			T140	25		T40	7		T164	28
values[5]	563	1			T6	40		T14	1		T149	13
values[6]	639	1			T6	39		T14	1		T111	1
values[7]	723	1			T7	1		T8	5		T15	15
values[8]	854	1			T9	1		T15	27		T111	1
values[9]	138	1			T13	1		T188	10		T145	1
minimum	16213	1			T1	20		T3	11		T5	17

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20778

1

T1

20

T2

1

T3

11

auto[1]

4055

1

T6

39

T8

2

T11

16

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	369	1			T8	4		T53	1		T244	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T7	1		T140	10		T182	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1597	1			T2	1		T11	6		T12	24
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T14	1		T182	1		T141	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T11	12		T40	4		T164	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T183	15		T162	7		T189	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T139	17		T142	1		T160	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T175	6		T225	4		T54	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T164	12		T136	1		T152	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T140	14		T40	5		T221	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T6	22		T83	1		T228	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T14	1		T149	1		T153	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T6	19		T14	1		T181	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T111	1		T48	12		T219	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T150	1		T183	3		T198	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T7	1		T8	3		T15	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	291	1			T9	1		T111	1		T48	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T15	10		T139	10		T136	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T188	1		T189	1		T185	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T13	1		T145	1		T252	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16090	1			T1	20		T3	11		T5	17
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T53	9		T44	2		T248	19
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T140	12		T143	7		T144	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	947	1			T45	10		T140	7		T164	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T16	1		T235	13		T200	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T40	1		T164	1		T144	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T253	13		T230	4		T227	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T142	13		T160	12		T83	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T225	5		T54	7		T245	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T164	16		T136	13		T85	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T140	11		T40	2		T106	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T6	18		T83	10		T228	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T149	12		T153	10		T224	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T6	20		T142	8		T160	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T48	11		T221	17		T106	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T150	12		T159	14		T235	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T8	2		T15	7		T151	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T48	10		T40	2		T41	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T15	17		T136	10		T143	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T188	9		T19	1		T254	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T252	1		T255	13		T256	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T8	3		T9	1		T48	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T99	11		T223	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T250	2		T257	17		T258	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T144	1		T251	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T11	6		T53	1		T244	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T7	1		T182	1		T143	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1637	1			T2	1		T8	4		T12	24
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T14	1		T140	10		T144	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T11	12		T140	4		T40	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T182	1		T141	1		T183	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T139	17		T160	3		T144	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T225	4		T54	10		T230	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T164	12		T142	1		T136	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T140	14		T40	5		T175	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T6	22		T181	1		T83	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T14	1		T149	1		T106	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T6	19		T183	3		T142	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T111	1		T48	12		T221	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T14	1		T150	1		T198	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T8	3		T15	8		T46	19
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	371	1			T9	1		T111	1		T48	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T7	1		T13	1		T15	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16090	1			T1	20		T3	11		T5	17
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T99	9		T223	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T258	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T144	5		T251	2		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T53	9		T44	2		T248	19
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T143	7		T188	2		T228	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	970	1			T45	10		T164	9		T205	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T140	12		T144	9		T42	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T140	7		T40	1		T159	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T253	13		T227	2		T259	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T160	12		T144	6		T226	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T225	5		T54	7		T230	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T164	16		T142	13		T136	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T140	11		T40	2		T185	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T6	18		T83	10		T226	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T149	12		T106	12		T153	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T6	20		T142	8		T160	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T48	11		T221	17		T106	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T150	12		T159	14		T234	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T8	2		T15	7		T151	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T48	10		T40	2		T41	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T15	17		T136	10		T143	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T8	3		T9	1		T48	2