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Summary for Variable clk_gate_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for clk_gate_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 24833 1 T1 20 T2 1 T3 11



Summary for Variable cond_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cond_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[ADC_CTRL_FILTER_COND_IN] 21464 1 T1 20 T2 1 T3 11
auto[ADC_CTRL_FILTER_COND_OUT] 3369 1 T6 39 T7 1 T9 1



Summary for Variable en_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for en_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 18951 1 T1 20 T3 11 T5 17
auto[1] 5882 1 T2 1 T6 79 T7 1



Summary for Variable interrupt_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for interrupt_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 21167 1 T1 20 T2 1 T3 11
auto[1] 3666 1 T6 38 T8 5 T9 1



Summary for Variable max_v_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 12 0 12 100.00


User Defined Bins for max_v_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
maximum 664 1 T9 1 T14 1 T49 4
values[0] 12 1 T152 1 T258 11 - -
values[1] 714 1 T7 1 T13 1 T48 23
values[2] 2990 1 T2 1 T6 40 T12 24
values[3] 636 1 T8 5 T9 1 T219 1
values[4] 535 1 T183 3 T142 14 T225 9
values[5] 610 1 T7 1 T14 1 T15 15
values[6] 650 1 T15 27 T150 13 T48 21
values[7] 660 1 T8 4 T11 12 T141 1
values[8] 798 1 T6 39 T40 5 T89 1
values[9] 692 1 T11 6 T14 1 T111 1
minimum 15872 1 T1 20 T3 11 T5 17



Summary for Variable min_v_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 12 1 11 91.67


User Defined Bins for min_v_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
maximum 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0] 650 1 T6 40 T7 1 T13 1
values[1] 3067 1 T2 1 T12 24 T26 22
values[2] 610 1 T8 5 T9 1 T219 1
values[3] 568 1 T14 1 T15 15 T40 7
values[4] 569 1 T7 1 T15 27 T111 1
values[5] 577 1 T8 4 T150 13 T48 21
values[6] 767 1 T6 39 T11 12 T141 1
values[7] 694 1 T139 10 T40 5 T89 1
values[8] 811 1 T11 6 T14 1 T111 1
values[9] 99 1 T14 1 T41 7 T106 26
minimum 16421 1 T1 20 T3 11 T5 17



Summary for Variable wakeup_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for wakeup_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 20778 1 T1 20 T2 1 T3 11
auto[1] 4055 1 T6 39 T8 2 T11 16



Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 48 4 44 91.67 4


Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes
interrupt_cpmin_v_cpcond_cpCOUNTAT LEASTNUMBERSTATUS
* [maximum] * -- -- 4


Covered bins
interrupt_cpmin_v_cpcond_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_IN] 206 1 T6 22 T7 1 T48 12
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 172 1 T13 1 T182 1 T164 1
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_IN] 1619 1 T2 1 T12 24 T26 22
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 309 1 T46 19 T140 18 T182 1
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_IN] 188 1 T8 3 T43 4 T154 1
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 151 1 T9 1 T219 1 T183 3
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_IN] 167 1 T14 1 T15 8 T40 5
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 170 1 T141 1 T225 4 T54 10
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_IN] 134 1 T15 10 T139 17 T151 1
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 159 1 T7 1 T111 1 T218 11
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_IN] 151 1 T8 4 T48 11 T182 1
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 184 1 T150 1 T40 4 T183 15
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_IN] 233 1 T11 12 T144 1 T189 1
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 230 1 T6 19 T141 1 T160 12
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_IN] 211 1 T139 10 T40 3 T89 1
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 192 1 T220 2 T42 4 T217 15
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_IN] 215 1 T11 6 T164 12 T136 1
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 236 1 T14 1 T111 1 T149 1
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_IN] 14 1 T254 11 T305 3 - -
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 38 1 T14 1 T41 5 T106 14
auto[0] minimum auto[ADC_CTRL_FILTER_COND_IN] 16135 1 T1 20 T3 11 T5 17
auto[0] minimum auto[ADC_CTRL_FILTER_COND_OUT] 53 1 T142 1 T85 12 T35 3
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_IN] 142 1 T6 18 T48 11 T140 12
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 130 1 T164 1 T153 9 T229 10
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_IN] 953 1 T45 10 T205 9 T174 19
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 186 1 T140 18 T53 9 T228 10
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_IN] 144 1 T8 2 T43 4 T229 12
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 127 1 T188 11 T224 20 T302 10
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_IN] 125 1 T15 7 T40 2 T142 13
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 106 1 T225 5 T54 7 T234 5
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_IN] 94 1 T15 17 T151 12 T188 2
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 182 1 T160 12 T144 6 T83 10
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_IN] 101 1 T48 10 T164 8 T143 7
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 141 1 T150 12 T40 1 T159 5
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_IN] 142 1 T144 5 T242 2 T207 10
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 162 1 T6 20 T160 9 T225 14
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_IN] 149 1 T40 2 T253 13 T153 10
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 142 1 T42 2 T245 9 T227 12
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_IN] 167 1 T164 16 T136 13 T144 9
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 193 1 T149 12 T221 17 T248 13
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_IN] 11 1 T254 11 - - - -
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 36 1 T41 2 T106 12 T298 3
auto[1] minimum auto[ADC_CTRL_FILTER_COND_IN] 163 1 T8 3 T9 1 T48 2
auto[1] minimum auto[ADC_CTRL_FILTER_COND_OUT] 70 1 T142 8 T85 9 T287 6



Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 48 3 45 93.75 3


Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins
interrupt_cpmax_v_cpcond_cpCOUNTAT LEASTNUMBERSTATUS
[auto[0]] [minimum] [auto[ADC_CTRL_FILTER_COND_OUT]] 0 1 1
[auto[1]] [values[0]] [auto[ADC_CTRL_FILTER_COND_IN]] 0 1 1
[auto[1]] [minimum] [auto[ADC_CTRL_FILTER_COND_OUT]] 0 1 1


Covered bins
interrupt_cpmax_v_cpcond_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] maximum auto[ADC_CTRL_FILTER_COND_IN] 414 1 T9 1 T49 4 T50 2
auto[0] maximum auto[ADC_CTRL_FILTER_COND_OUT] 107 1 T14 1 T41 5 T152 1
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_IN] 1 1 T152 1 - - - -
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 1 1 T258 1 - - - -
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_IN] 191 1 T7 1 T48 12 T140 10
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 187 1 T13 1 T182 1 T142 1
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_IN] 1628 1 T2 1 T6 22 T12 24
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 248 1 T46 19 T140 18 T182 1
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_IN] 186 1 T8 3 T266 1 T43 4
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 211 1 T9 1 T219 1 T198 1
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_IN] 145 1 T142 1 T107 14 T16 1
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 165 1 T183 3 T225 4 T188 1
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_IN] 190 1 T14 1 T15 8 T139 17
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 164 1 T7 1 T111 1 T141 1
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_IN] 155 1 T15 10 T48 11 T182 1
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 182 1 T150 1 T40 4 T183 15
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_IN] 197 1 T8 4 T11 12 T144 1
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 173 1 T141 1 T160 12 T225 14
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_IN] 216 1 T40 3 T89 1 T189 1
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 255 1 T6 19 T220 2 T42 4
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_IN] 201 1 T11 6 T139 10 T164 12
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 201 1 T14 1 T111 1 T149 1
auto[0] minimum auto[ADC_CTRL_FILTER_COND_IN] 15749 1 T1 20 T3 11 T5 17
auto[1] maximum auto[ADC_CTRL_FILTER_COND_IN] 68 1 T136 13 T144 9 T36 1
auto[1] maximum auto[ADC_CTRL_FILTER_COND_OUT] 75 1 T41 2 T221 17 T106 12
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 10 1 T258 10 - - - -
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_IN] 149 1 T48 11 T140 12 T136 10
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 187 1 T142 8 T85 9 T153 9
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_IN] 967 1 T6 18 T45 10 T205 9
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 147 1 T140 18 T164 1 T53 9
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_IN] 134 1 T8 2 T43 4 T229 12
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 105 1 T228 10 T224 20 T99 13
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_IN] 101 1 T142 13 T16 1 T155 4
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 124 1 T225 5 T188 11 T54 7
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_IN] 116 1 T15 7 T40 2 T151 12
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 140 1 T160 12 T44 2 T226 10
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_IN] 131 1 T15 17 T48 10 T164 8
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 182 1 T150 12 T40 1 T159 5
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_IN] 135 1 T144 5 T242 2 T207 10
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 155 1 T160 9 T225 14 T230 4
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_IN] 151 1 T40 2 T253 13 T153 10
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 176 1 T6 20 T42 2 T227 12
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_IN] 116 1 T164 16 T162 2 T245 11
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 174 1 T149 12 T248 13 T276 3
auto[1] minimum auto[ADC_CTRL_FILTER_COND_IN] 123 1 T8 3 T9 1 T48 2



Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 48 4 44 91.67 4


Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes
wakeup_cpmin_v_cpcond_cpCOUNTAT LEASTNUMBERSTATUS
* [maximum] * -- -- 4


Covered bins
wakeup_cpmin_v_cpcond_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_IN] 171 1 T6 19 T7 1 T48 12
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 164 1 T13 1 T182 1 T164 2
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_IN] 1289 1 T2 1 T12 3 T26 2
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 236 1 T46 1 T140 20 T182 1
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_IN] 186 1 T8 4 T43 6 T154 1
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 160 1 T9 1 T219 1 T183 1
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_IN] 154 1 T14 1 T15 8 T40 5
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 137 1 T141 1 T225 6 T54 8
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_IN] 122 1 T15 18 T139 1 T151 13
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 222 1 T7 1 T111 1 T218 1
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_IN] 135 1 T8 3 T48 11 T182 1
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 189 1 T150 13 T40 4 T183 1
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_IN] 179 1 T11 1 T144 6 T189 1
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 205 1 T6 21 T141 1 T160 10
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_IN] 193 1 T139 1 T40 3 T89 1
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 178 1 T220 2 T42 4 T217 2
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_IN] 204 1 T11 1 T164 17 T136 14
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 240 1 T14 1 T111 1 T149 13
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_IN] 14 1 T254 12 T305 2 - -
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 44 1 T14 1 T41 4 T106 13
auto[0] minimum auto[ADC_CTRL_FILTER_COND_IN] 16271 1 T1 20 T3 11 T5 17
auto[0] minimum auto[ADC_CTRL_FILTER_COND_OUT] 85 1 T142 9 T85 10 T35 1
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_IN] 177 1 T6 21 T48 11 T140 9
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 138 1 T265 9 T184 12 T245 15
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_IN] 1283 1 T12 21 T26 20 T45 12
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 259 1 T46 18 T140 16 T260 17
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_IN] 146 1 T8 1 T43 2 T184 10
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 118 1 T183 2 T168 14 T222 9
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_IN] 138 1 T15 7 T40 2 T107 13
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 139 1 T225 3 T54 9 T168 8
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_IN] 106 1 T15 9 T139 16 T106 4
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 119 1 T218 10 T160 2 T144 7
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_IN] 117 1 T8 1 T48 10 T164 4
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 136 1 T40 1 T183 14 T159 11
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_IN] 196 1 T11 11 T242 17 T259 12
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 187 1 T6 18 T160 11 T225 13
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_IN] 167 1 T139 9 T40 2 T165 1
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 156 1 T42 2 T217 13 T245 7
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_IN] 178 1 T11 5 T164 11 T144 9
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 189 1 T221 12 T217 12 T248 2
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_IN] 11 1 T254 10 T305 1 - -
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 30 1 T41 3 T106 13 T185 14
auto[1] minimum auto[ADC_CTRL_FILTER_COND_IN] 27 1 T136 10 T244 8 T293 2
auto[1] minimum auto[ADC_CTRL_FILTER_COND_OUT] 38 1 T85 11 T35 2 T288 8



Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 48 5 43 89.58 5


Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes
wakeup_cpmax_v_cpcond_cpCOUNTAT LEASTNUMBERSTATUS
[auto[1]] [values[0]] * -- -- 2
[auto[1]] [minimum] * -- -- 2


Uncovered bins
wakeup_cpmax_v_cpcond_cpCOUNTAT LEASTNUMBERSTATUS
[auto[0]] [minimum] [auto[ADC_CTRL_FILTER_COND_OUT]] 0 1 1


Covered bins
wakeup_cpmax_v_cpcond_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] maximum auto[ADC_CTRL_FILTER_COND_IN] 425 1 T9 1 T49 4 T50 2
auto[0] maximum auto[ADC_CTRL_FILTER_COND_OUT] 90 1 T14 1 T41 4 T152 1
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_IN] 1 1 T152 1 - - - -
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 11 1 T258 11 - - - -
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_IN] 188 1 T7 1 T48 12 T140 13
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 230 1 T13 1 T182 1 T142 9
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_IN] 1300 1 T2 1 T6 19 T12 3
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 192 1 T46 1 T140 20 T182 1
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_IN] 169 1 T8 4 T266 1 T43 6
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 136 1 T9 1 T219 1 T198 1
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_IN] 135 1 T142 14 T107 1 T16 2
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 158 1 T183 1 T225 6 T188 12
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_IN] 150 1 T14 1 T15 8 T139 1
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 178 1 T7 1 T111 1 T141 1
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_IN] 165 1 T15 18 T48 11 T182 1
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 224 1 T150 13 T40 4 T183 1
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_IN] 170 1 T8 3 T11 1 T144 6
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 200 1 T141 1 T160 10 T225 15
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_IN] 198 1 T40 3 T89 1 T189 1
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 221 1 T6 21 T220 2 T42 4
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_IN] 145 1 T11 1 T139 1 T164 17
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 220 1 T14 1 T111 1 T149 13
auto[0] minimum auto[ADC_CTRL_FILTER_COND_IN] 15872 1 T1 20 T3 11 T5 17
auto[1] maximum auto[ADC_CTRL_FILTER_COND_IN] 57 1 T144 9 T269 13 T306 11
auto[1] maximum auto[ADC_CTRL_FILTER_COND_OUT] 92 1 T41 3 T221 12 T106 13
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_IN] 152 1 T48 11 T140 9 T136 10
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 144 1 T85 11 T265 9 T35 2
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_IN] 1295 1 T6 21 T12 21 T26 20
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 203 1 T46 18 T140 16 T260 17
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_IN] 151 1 T8 1 T43 2 T184 10
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 180 1 T228 12 T239 14 T99 11
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_IN] 111 1 T107 13 T155 3 T165 5
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 131 1 T183 2 T225 3 T54 9
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_IN] 156 1 T15 7 T139 16 T40 2
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 126 1 T218 10 T160 2 T44 2
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_IN] 121 1 T15 9 T48 10 T164 4
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 140 1 T40 1 T183 14 T159 11
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_IN] 162 1 T8 1 T11 11 T242 17
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 128 1 T160 11 T225 13 T221 10
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_IN] 169 1 T40 2 T165 1 T297 10
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 210 1 T6 18 T42 2 T217 13
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_IN] 172 1 T11 5 T139 9 T164 11
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 155 1 T217 12 T248 2 T276 2



Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 2 2 50.00 2


Automatically Generated Cross Bins for wakeup_gated_xp

Element holes
wakeup_cpclk_gate_cpCOUNTAT LEASTNUMBERSTATUS
* [auto[1]] -- -- 2


Covered bins
wakeup_cpclk_gate_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 20778 1 T1 20 T2 1 T3 11
auto[1] auto[0] 4055 1 T6 39 T8 2 T11 16

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