Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24833

1

T1

20

T2

1

T3

11

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21699

1

T1

20

T2

1

T3

11

auto[ADC_CTRL_FILTER_COND_OUT]

3134

1

T7

2

T8

5

T9

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18937

1

T1

20

T3

11

T5

17

auto[1]

5896

1

T2

1

T6

79

T7

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21167

1

T1

20

T2

1

T3

11

auto[1]

3666

1

T6

38

T8

5

T9

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	300	1			T15	27		T175	6		T83	11
values[0]	20	1			T164	13		T276	6		T307	1
values[1]	544	1			T7	1		T11	6		T14	1
values[2]	612	1			T7	1		T45	23		T48	21
values[3]	714	1			T46	19		T140	47		T40	5
values[4]	3004	1			T2	1		T12	24		T13	1
values[5]	712	1			T6	79		T14	1		T140	11
values[6]	500	1			T14	1		T182	1		T40	7
values[7]	805	1			T8	5		T182	1		T198	1
values[8]	526	1			T150	13		T139	27		T183	3
values[9]	883	1			T8	4		T9	1		T11	12
minimum	16213	1			T1	20		T3	11		T5	17

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	462	1			T7	1		T11	6		T111	2
values[1]	696	1			T45	23		T48	21		T164	2
values[2]	771	1			T46	19		T140	47		T40	5
values[3]	2955	1			T2	1		T6	39		T12	24
values[4]	687	1			T6	40		T14	2		T140	11
values[5]	574	1			T182	1		T40	7		T198	1
values[6]	683	1			T8	5		T150	13		T182	1
values[7]	614	1			T181	1		T139	27		T142	14
values[8]	893	1			T9	1		T11	12		T15	27
values[9]	117	1			T8	4		T141	1		T175	6
minimum	16381	1			T1	20		T3	11		T5	17

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20778

1

T1

20

T2

1

T3

11

auto[1]

4055

1

T6

39

T8

2

T11

16

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T111	2		T41	5		T221	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T7	1		T11	6		T152	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T164	1		T183	15		T136	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T45	13		T48	11		T149	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T40	4		T42	7		T95	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T46	19		T140	24		T141	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1658	1			T2	1		T6	19		T12	24
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T13	1		T48	12		T219	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T6	22		T14	1		T146	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T14	1		T140	4		T218	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T40	5		T198	1		T159	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T182	1		T143	3		T188	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T182	1		T183	3		T160	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T8	3		T150	1		T198	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T181	1		T54	10		T265	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T139	27		T142	1		T107	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T11	12		T15	10		T151	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T9	1		T164	12		T225	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T8	4		T141	1		T175	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T239	15		T308	1		T282	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16129	1			T1	20		T3	11		T5	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T7	1		T14	1		T42	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T41	2		T153	9		T229	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T253	13		T234	5		T44	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T164	1		T136	13		T53	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T45	10		T48	10		T149	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T40	1		T42	2		T95	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T140	23		T144	6		T228	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	962	1			T6	20		T15	7		T40	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T48	11		T143	7		T43	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T6	18		T234	13		T231	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T140	7		T142	8		T136	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T40	2		T159	5		T85	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T143	7		T188	9		T293	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T160	12		T248	19		T226	19
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T8	2		T150	12		T144	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T54	7		T16	1		T245	20
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T142	13		T99	8		T269	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T15	17		T151	12		T159	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T164	16		T225	5		T106	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T36	1		T263	11		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T282	9		T222	8		T286	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T8	3		T9	1		T48	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T242	9		T224	7		T191	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T15	10		T175	6		T83	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T189	1		T44	8		T155	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T164	5		T276	3		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T307	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T111	2		T41	5		T217	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T7	1		T11	6		T14	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T164	1		T136	1		T225	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T7	1		T45	13		T48	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T40	4		T183	15		T53	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T46	19		T140	24		T141	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1668	1			T2	1		T12	24		T15	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T13	1		T48	12		T219	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T6	41		T14	1		T40	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T140	4		T218	11		T142	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T40	5		T198	1		T146	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T14	1		T182	1		T143	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T182	1		T159	12		T160	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T8	3		T198	1		T144	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T183	3		T265	10		T226	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T150	1		T139	27		T107	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T8	4		T11	12		T181	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T9	1		T164	12		T142	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16090	1			T1	20		T3	11		T5	17
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T15	17		T83	10		T226	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T44	4		T155	9		T207	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T164	8		T276	3		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T41	2		T153	9		T179	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T253	13		T44	2		T252	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T164	1		T136	13		T225	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T45	10		T48	10		T149	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T40	1		T53	9		T165	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T140	23		T144	6		T228	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	959	1			T15	7		T205	9		T174	19
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T48	11		T143	7		T43	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T6	38		T40	2		T234	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T140	7		T142	8		T136	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T40	2		T42	2		T153	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T143	7		T188	9		T224	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T159	5		T160	12		T85	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T8	2		T144	9		T228	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T226	10		T245	20		T233	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T150	12		T99	8		T269	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T151	12		T159	14		T160	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T164	16		T142	13		T225	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T8	3		T9	1		T48	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T111	2		T41	4		T221	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T7	1		T11	1		T152	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T164	2		T183	1		T136	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T45	11		T48	11		T149	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T40	4		T42	7		T95	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T46	1		T140	25		T141	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1301	1			T2	1		T6	21		T12	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T13	1		T48	12		T219	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T6	19		T14	1		T146	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T14	1		T140	8		T218	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T40	5		T198	1		T159	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T182	1		T143	8		T188	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T182	1		T183	1		T160	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T8	4		T150	13		T198	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T181	1		T54	8		T265	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T139	2		T142	14		T107	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T11	1		T15	18		T151	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T9	1		T164	17		T225	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T8	3		T141	1		T175	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T239	1		T308	1		T282	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16271	1			T1	20		T3	11		T5	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T7	1		T14	1		T42	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T41	3		T221	10		T217	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T11	5		T217	5		T44	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T183	14		T225	13		T221	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T45	12		T48	10		T244	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T40	1		T42	2		T95	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T46	18		T140	22		T144	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1319	1			T6	18		T12	21		T15	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T48	11		T143	7		T43	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T6	21		T184	10		T231	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T140	3		T218	10		T136	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T40	2		T159	11		T85	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T143	2		T185	14		T309	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T183	2		T160	2		T162	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T8	1		T144	9		T228	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T54	9		T265	9		T245	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T139	25		T107	13		T184	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T11	11		T15	9		T159	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T164	11		T225	3		T106	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T8	1		T175	5		T35	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T239	14		T222	9		T286	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T164	4		T276	2		T310	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T35	11		T242	9		T191	3

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T15	18		T175	1		T83	11
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T189	1		T44	5		T155	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T164	9		T276	4		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T307	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T111	2		T41	4		T217	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T7	1		T11	1		T14	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T164	2		T136	14		T225	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T7	1		T45	11		T48	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T40	4		T183	1		T53	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T46	1		T140	25		T141	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1311	1			T2	1		T12	3		T15	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T13	1		T48	12		T219	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T6	40		T14	1		T40	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T140	8		T218	1		T142	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T40	5		T198	1		T146	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T14	1		T182	1		T143	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T182	1		T159	6		T160	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T8	4		T198	1		T144	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T183	1		T265	1		T226	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T150	13		T139	2		T107	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T8	3		T11	1		T181	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T9	1		T164	17		T142	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16213	1			T1	20		T3	11		T5	17
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T15	9		T175	5		T226	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T44	7		T155	4		T262	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T164	4		T276	2		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T41	3		T217	8		T179	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T11	5		T217	5		T44	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T225	13		T221	22		T162	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T45	12		T48	10		T244	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T40	1		T183	14		T261	20
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T46	18		T140	22		T144	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1316	1			T12	21		T15	7		T26	20
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T48	11		T143	7		T43	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T6	39		T40	2		T184	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T140	3		T218	10		T136	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T40	2		T42	2		T184	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T143	2		T185	14		T200	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T159	11		T160	2		T85	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T8	1		T144	9		T228	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T183	2		T265	9		T226	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T139	25		T107	13		T184	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T8	1		T11	11		T159	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T164	11		T225	3		T106	13

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20778

1

T1

20

T2

1

T3

11

auto[1]

auto[0]

4055

1

T6

39

T8

2

T11

16