Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24833

1

T1

20

T2

1

T3

11

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21433

1

T1

20

T2

1

T3

11

auto[ADC_CTRL_FILTER_COND_OUT]

3400

1

T6

40

T8

9

T11

18

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19207

1

T1

20

T3

11

T5

17

auto[1]

5626

1

T2

1

T7

1

T8

5

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21167

1

T1

20

T2

1

T3

11

auto[1]

3666

1

T6

38

T8

5

T9

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	42	1			T207	19		T271	19		T311	4
values[0]	61	1			T143	15		T36	3		T165	14
values[1]	696	1			T6	39		T182	1		T164	13
values[2]	567	1			T8	4		T111	1		T182	1
values[3]	573	1			T11	6		T14	1		T111	1
values[4]	636	1			T7	1		T14	1		T15	15
values[5]	2877	1			T2	1		T8	5		T11	12
values[6]	733	1			T40	7		T149	13		T41	7
values[7]	732	1			T13	1		T40	5		T136	14
values[8]	576	1			T7	1		T14	1		T46	19
values[9]	1127	1			T6	40		T9	1		T45	23
minimum	16213	1			T1	20		T3	11		T5	17

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	754	1			T6	39		T182	1		T183	3
values[1]	828	1			T8	4		T111	1		T182	1
values[2]	409	1			T7	1		T11	6		T14	2
values[3]	2917	1			T2	1		T8	5		T12	24
values[4]	616	1			T11	12		T15	27		T140	25
values[5]	813	1			T13	1		T149	13		T136	14
values[6]	655	1			T48	23		T139	10		T40	5
values[7]	568	1			T46	19		T150	13		T140	11
values[8]	805	1			T7	1		T14	1		T45	23
values[9]	227	1			T6	40		T9	1		T219	1
minimum	16241	1			T1	20		T3	11		T5	17

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20778

1

T1

20

T2

1

T3

11

auto[1]

4055

1

T6

39

T8

2

T11

16

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T6	19		T183	3		T142	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T182	1		T142	1		T53	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T111	1		T182	1		T160	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T8	4		T164	5		T89	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T7	1		T14	1		T253	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T11	6		T14	1		T111	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1642	1			T2	1		T12	24		T15	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T8	3		T181	1		T140	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T140	14		T164	13		T41	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T11	12		T15	10		T40	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T13	1		T149	1		T136	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T152	1		T266	1		T220	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T40	3		T159	12		T236	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T48	12		T139	10		T144	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T140	4		T143	3		T83	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T46	19		T150	1		T198	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T7	1		T144	10		T35	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T14	1		T45	13		T139	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T9	1		T152	1		T146	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T6	22		T219	1		T42	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16090	1			T1	20		T3	11		T5	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T312	1		T313	11		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T6	20		T142	13		T143	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T142	8		T53	9		T225	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T160	9		T85	9		T54	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T164	8		T233	1		T283	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T253	13		T235	13		T314	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T136	10		T245	11		T241	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	944	1			T15	7		T48	10		T205	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T8	2		T140	12		T40	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T140	11		T164	17		T41	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T15	17		T40	2		T188	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T149	12		T136	13		T160	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T43	4		T44	2		T16	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T40	2		T159	5		T236	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T48	11		T144	5		T252	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T140	7		T143	7		T83	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T150	12		T188	11		T16	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T144	9		T155	9		T233	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T45	10		T159	14		T234	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T106	12		T207	9		T291	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T6	18		T42	2		T233	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T8	3		T9	1		T48	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T312	6		T313	10		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T207	10		T311	1		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T271	10		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T143	8		T36	2		T165	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T315	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T6	19		T183	3		T142	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T182	1		T164	5		T53	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T111	1		T182	1		T160	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T8	4		T142	1		T225	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T14	1		T85	12		T253	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T11	6		T111	1		T141	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T7	1		T15	8		T48	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T14	1		T140	10		T151	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1662	1			T2	1		T12	24		T26	22
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T8	3		T11	12		T15	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T149	1		T41	5		T160	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T40	5		T266	1		T220	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T13	1		T40	3		T136	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T144	1		T189	1		T42	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T7	1		T140	4		T143	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T14	1		T46	19		T150	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T9	1		T144	10		T152	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	404	1			T6	22		T45	13		T139	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16090	1			T1	20		T3	11		T5	17
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T207	9		T311	3		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T271	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T143	7		T36	1		T165	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T315	13		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T6	20		T142	13		T44	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T164	8		T53	9		T231	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T160	9		T54	7		T177	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T142	8		T225	14		T283	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T85	9		T253	13		T242	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T245	11		T233	1		T241	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T15	7		T48	10		T226	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T140	12		T151	12		T136	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	893	1			T140	11		T164	17		T205	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T8	2		T15	17		T40	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T149	12		T41	2		T160	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T40	2		T44	2		T16	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T40	2		T136	13		T159	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T144	5		T43	4		T252	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T140	7		T143	7		T165	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T150	12		T48	11		T188	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T144	9		T83	10		T106	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T6	18		T45	10		T159	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T8	3		T9	1		T48	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T6	21		T183	1		T142	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T182	1		T142	9		T53	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T111	1		T182	1		T160	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T8	3		T164	9		T89	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T7	1		T14	1		T253	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T11	1		T14	1		T111	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1283	1			T2	1		T12	3		T15	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T8	4		T181	1		T140	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T140	12		T164	19		T41	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T11	1		T15	18		T40	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T13	1		T149	13		T136	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T152	1		T266	1		T220	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T40	3		T159	6		T236	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T48	12		T139	1		T144	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T140	8		T143	8		T83	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T46	1		T150	13		T198	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T7	1		T144	10		T35	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T14	1		T45	11		T139	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T9	1		T152	1		T146	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T6	19		T219	1		T42	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16213	1			T1	20		T3	11		T5	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T312	7		T313	11		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T6	18		T183	2		T143	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T225	13		T231	7		T99	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T160	11		T85	11		T54	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T8	1		T164	4		T221	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T154	1		T239	14		T192	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T11	5		T136	10		T245	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1303	1			T12	21		T15	7		T26	20
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T8	1		T140	9		T40	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T140	13		T164	11		T41	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T11	11		T15	9		T40	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T160	2		T225	3		T221	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T43	2		T44	2		T184	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T40	2		T159	11		T260	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T48	11		T139	9		T244	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T140	3		T143	2		T248	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T46	18		T107	13		T16	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T144	9		T35	13		T184	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T45	12		T139	16		T175	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T106	13		T207	9		T291	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T6	21		T42	2		T233	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T313	10		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T207	10		T311	4		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T271	10		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T143	8		T36	3		T165	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T315	14		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T6	21		T183	1		T142	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T182	1		T164	9		T53	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T111	1		T182	1		T160	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T8	3		T142	9		T225	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T14	1		T85	10		T253	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T11	1		T111	1		T141	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T7	1		T15	8		T48	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T14	1		T140	13		T151	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1237	1			T2	1		T12	3		T26	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T8	4		T11	1		T15	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	294	1			T149	13		T41	4		T160	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T40	5		T266	1		T220	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T13	1		T40	3		T136	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T144	6		T189	1		T42	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T7	1		T140	8		T143	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T14	1		T46	1		T150	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T9	1		T144	10		T152	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	327	1			T6	19		T45	11		T139	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16213	1			T1	20		T3	11		T5	17
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T207	9		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T271	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T143	7		T165	5		T316	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T6	18		T183	2		T217	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T164	4		T231	7		T99	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T160	11		T54	9		T317	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T8	1		T225	13		T283	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T85	11		T242	9		T154	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T11	5		T221	10		T217	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T15	7		T48	10		T183	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T140	9		T218	10		T136	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1318	1			T12	21		T26	20		T47	35
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T8	1		T11	11		T15	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T41	3		T160	2		T225	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T40	2		T44	2		T245	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T40	2		T159	11		T162	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T43	2		T244	8		T226	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T140	3		T143	2		T260	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T46	18		T48	11		T139	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T144	9		T106	13		T35	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	339	1			T6	21		T45	12		T139	16

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20778

1

T1

20

T2

1

T3

11

auto[1]

auto[0]

4055

1

T6

39

T8

2

T11

16