Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24833

1

T1

20

T2

1

T3

11

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21985

1

T1

20

T2

1

T3

11

auto[ADC_CTRL_FILTER_COND_OUT]

2848

1

T7

2

T8

5

T13

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19265

1

T1

20

T3

11

T5

17

auto[1]

5568

1

T2

1

T6

79

T7

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21167

1

T1

20

T2

1

T3

11

auto[1]

3666

1

T6

38

T8

5

T9

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	305	1			T48	21		T139	10		T188	10
values[0]	99	1			T144	6		T248	30		T222	18
values[1]	710	1			T7	1		T182	1		T53	10
values[2]	2941	1			T2	1		T8	4		T11	6
values[3]	540	1			T11	12		T140	11		T182	1
values[4]	652	1			T139	17		T175	6		T160	15
values[5]	593	1			T140	25		T40	7		T142	14
values[6]	626	1			T6	40		T14	1		T181	1
values[7]	601	1			T6	39		T111	1		T48	23
values[8]	745	1			T7	1		T8	5		T14	1
values[9]	808	1			T9	1		T13	1		T15	27
minimum	16213	1			T1	20		T3	11		T5	17

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	757	1			T7	1		T8	4		T182	1
values[1]	2833	1			T2	1		T11	6		T12	24
values[2]	497	1			T11	12		T140	11		T40	5
values[3]	795	1			T139	17		T142	14		T175	6
values[4]	551	1			T140	25		T40	7		T164	28
values[5]	556	1			T6	40		T14	1		T149	13
values[6]	578	1			T6	39		T14	1		T46	19
values[7]	788	1			T7	1		T8	5		T15	15
values[8]	904	1			T9	1		T15	27		T111	1
values[9]	75	1			T13	1		T252	2		T192	9
minimum	16499	1			T1	20		T3	11		T5	17

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20778

1

T1

20

T2

1

T3

11

auto[1]

4055

1

T6

39

T8

2

T11

16

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T8	4		T44	4		T153	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T7	1		T182	1		T143	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1616	1			T2	1		T11	6		T12	24
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T14	1		T140	10		T182	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T11	12		T140	4		T40	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T183	15		T162	7		T189	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T139	17		T142	1		T160	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T175	6		T144	8		T225	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T164	12		T152	2		T85	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T140	14		T40	5		T136	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T6	22		T83	1		T228	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T14	1		T149	1		T153	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T6	19		T14	1		T181	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T46	19		T111	1		T48	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T150	1		T183	3		T198	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T7	1		T8	3		T15	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	317	1			T9	1		T111	1		T48	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T15	10		T139	10		T136	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T254	8		T196	1		T324	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T13	1		T252	1		T192	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16199	1			T1	20		T3	11		T5	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T145	1		T207	10		T325	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T44	2		T153	9		T290	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T143	7		T144	14		T188	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	938	1			T45	10		T164	8		T205	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T140	12		T42	2		T16	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T140	7		T40	1		T164	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T253	13		T230	4		T227	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T142	13		T160	12		T83	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T144	6		T225	5		T54	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T164	16		T85	9		T226	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T140	11		T40	2		T136	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T6	18		T83	10		T228	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T149	12		T153	10		T224	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T6	20		T142	8		T160	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T48	11		T221	17		T106	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T150	12		T159	14		T234	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T8	2		T15	7		T151	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T48	10		T40	2		T41	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T15	17		T136	10		T143	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T254	4		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T252	1		T255	13		T256	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T8	3		T9	1		T48	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T207	9		T325	14		T294	7

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T48	11		T188	1		T226	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T139	10		T165	4		T180	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T248	11		T222	10		T255	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T144	1		T251	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T53	1		T244	9		T44	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T7	1		T182	1		T143	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1651	1			T2	1		T8	4		T11	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T14	1		T140	10		T144	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T11	12		T140	4		T40	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T182	1		T141	1		T183	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T139	17		T160	3		T152	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T175	6		T144	8		T225	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T142	1		T152	1		T83	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T140	14		T40	5		T136	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T6	22		T181	1		T164	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T14	1		T149	1		T106	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T6	19		T142	1		T160	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T111	1		T48	12		T221	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T14	1		T150	1		T183	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T7	1		T8	3		T15	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T9	1		T111	1		T182	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T13	1		T15	10		T136	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16090	1			T1	20		T3	11		T5	17
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T48	10		T188	9		T226	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T223	2		T322	14		T256	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T248	19		T222	8		T255	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T144	5		T251	2		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T53	9		T44	2		T153	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T143	7		T188	2		T228	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	981	1			T45	10		T164	8		T205	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T140	12		T144	9		T42	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T140	7		T40	1		T164	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T253	13		T227	2		T200	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T160	12		T42	2		T226	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T144	6		T225	5		T54	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T142	13		T83	2		T85	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T140	11		T40	2		T136	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T6	18		T164	16		T83	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T149	12		T106	12		T153	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T6	20		T142	8		T160	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T48	11		T221	17		T106	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T150	12		T159	14		T234	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T8	2		T15	7		T151	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T40	2		T41	2		T242	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T15	17		T136	10		T143	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T8	3		T9	1		T48	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T8	3		T44	4		T153	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T7	1		T182	1		T143	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1274	1			T2	1		T11	1		T12	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T14	1		T140	13		T182	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T11	1		T140	8		T40	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T183	1		T162	1		T189	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T139	1		T142	14		T160	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T175	1		T144	7		T225	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T164	17		T152	2		T85	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T140	12		T40	5		T136	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T6	19		T83	11		T228	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T14	1		T149	13		T153	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T6	21		T14	1		T181	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T46	1		T111	1		T48	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T150	13		T183	1		T198	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T7	1		T8	4		T15	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T9	1		T111	1		T48	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T15	18		T139	1		T136	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T254	5		T196	1		T324	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T13	1		T252	2		T192	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16326	1			T1	20		T3	11		T5	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T145	1		T207	10		T325	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T8	1		T44	2		T233	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T143	2		T144	9		T228	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1280	1			T11	5		T12	21		T26	20
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T140	9		T42	2		T16	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T11	11		T140	3		T40	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T183	14		T162	6		T261	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T139	16		T160	2		T42	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T175	5		T144	7		T225	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T164	11		T85	11		T260	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T140	13		T40	2		T221	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T6	21		T228	12		T261	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T184	10		T262	10		T167	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T6	18		T160	11		T225	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T46	18		T48	11		T221	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T183	2		T159	13		T155	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T8	1		T15	7		T165	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T48	10		T40	2		T41	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T15	9		T139	9		T136	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T254	7		T326	13		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T192	8		T256	8		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T244	8		T248	10		T154	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T207	9		T325	11		T294	3

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T48	11		T188	10		T226	11
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T139	1		T165	4		T180	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T248	20		T222	9		T255	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T144	6		T251	3		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T53	10		T244	1		T44	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T7	1		T182	1		T143	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1334	1			T2	1		T8	3		T11	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T14	1		T140	13		T144	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T11	1		T140	8		T40	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T182	1		T141	1		T183	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T139	1		T160	13		T152	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T175	1		T144	7		T225	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T142	14		T152	1		T83	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T140	12		T40	5		T136	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T6	19		T181	1		T164	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T14	1		T149	13		T106	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T6	21		T142	9		T160	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T111	1		T48	12		T221	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T14	1		T150	13		T183	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T7	1		T8	4		T15	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T9	1		T111	1		T182	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	314	1			T13	1		T15	18		T136	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16213	1			T1	20		T3	11		T5	17
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T48	10		T226	2		T185	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T139	9		T180	1		T192	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T248	10		T222	9		T327	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T244	8		T44	2		T154	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T143	2		T228	6		T217	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1298	1			T8	1		T11	5		T12	21
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T140	9		T144	9		T42	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T11	11		T140	3		T40	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T183	14		T162	6		T261	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T139	16		T160	2		T42	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T175	5		T144	7		T225	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T85	11		T260	17		T328	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T140	13		T40	2		T221	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T6	21		T164	11		T226	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T106	13		T265	9		T184	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T6	18		T160	11		T225	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T48	11		T221	12		T106	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T183	2		T159	13		T155	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T8	1		T15	7		T46	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T40	2		T41	3		T242	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T15	9		T136	10		T143	7

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20778

1

T1

20

T2

1

T3

11

auto[1]

auto[0]

4055

1

T6

39

T8

2

T11

16