Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24833

1

T1

20

T2

1

T3

11

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21740

1

T1

20

T2

1

T3

11

auto[ADC_CTRL_FILTER_COND_OUT]

3093

1

T6

40

T7

1

T8

4

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19065

1

T1

20

T3

11

T5

17

auto[1]

5768

1

T2

1

T6

40

T7

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21167

1

T1

20

T2

1

T3

11

auto[1]

3666

1

T6

38

T8

5

T9

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	243	1			T143	15		T217	13		T234	6
values[0]	65	1			T198	1		T217	9		T240	21
values[1]	613	1			T7	1		T45	23		T140	22
values[2]	551	1			T111	1		T41	7		T160	15
values[3]	868	1			T6	39		T9	1		T140	25
values[4]	524	1			T8	9		T14	1		T150	13
values[5]	463	1			T111	1		T164	2		T141	1
values[6]	654	1			T14	1		T46	19		T140	11
values[7]	755	1			T7	1		T11	12		T14	1
values[8]	2731	1			T2	1		T12	24		T26	22
values[9]	1153	1			T6	40		T11	6		T13	1
minimum	16213	1			T1	20		T3	11		T5	17

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	588	1			T45	23		T111	1		T219	1
values[1]	599	1			T9	1		T160	15		T152	1
values[2]	827	1			T6	39		T8	4		T14	1
values[3]	497	1			T8	5		T48	23		T141	1
values[4]	465	1			T111	1		T182	1		T40	5
values[5]	690	1			T14	1		T46	19		T140	11
values[6]	2923	1			T2	1		T7	1		T11	12
values[7]	548	1			T11	6		T139	10		T141	1
values[8]	1077	1			T6	40		T13	1		T181	1
values[9]	151	1			T182	1		T146	1		T165	14
minimum	16468	1			T1	20		T3	11		T5	17

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20778

1

T1

20

T2

1

T3

11

auto[1]

4055

1

T6

39

T8

2

T11

16

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T45	13		T41	5		T160	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T111	1		T219	1		T40	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T160	3		T152	1		T85	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T9	1		T42	11		T199	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T6	19		T14	1		T140	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T8	4		T150	1		T182	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T8	3		T48	12		T221	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T141	1		T152	1		T220	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T111	1		T40	4		T183	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T182	1		T164	1		T136	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T14	1		T136	11		T144	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T46	19		T140	4		T152	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1588	1			T2	1		T7	1		T11	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T14	1		T15	18		T139	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T11	6		T139	10		T144	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T141	1		T175	6		T143	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	322	1			T13	1		T181	1		T164	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T6	22		T48	11		T183	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T182	1		T168	9		T222	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T146	1		T165	8		T237	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16168	1			T1	20		T3	11		T5	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T7	1		T83	1		T35	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T45	10		T41	2		T160	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T40	4		T164	8		T225	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T160	12		T85	9		T162	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T42	4		T226	19		T227	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T6	20		T140	11		T151	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T150	12		T149	12		T43	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T8	2		T48	11		T221	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T228	10		T229	10		T245	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T40	1		T159	5		T188	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T164	1		T136	13		T53	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T136	10		T144	5		T230	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T140	7		T16	1		T231	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	935	1			T205	9		T174	19		T232	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T15	24		T188	2		T233	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T144	6		T83	2		T234	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T143	7		T229	12		T235	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T164	16		T225	14		T236	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T6	18		T48	10		T142	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T168	12		T222	8		T223	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T165	6		T237	12		T329	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T8	3		T9	1		T48	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T83	10		T238	1		T254	4

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T234	1		T17	9		T283	13
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T143	8		T217	13		T153	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T198	1		T217	9		T240	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T330	5		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T45	13		T140	10		T160	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T7	1		T219	1		T40	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T41	5		T160	3		T152	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T111	1		T42	7		T217	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T6	19		T140	14		T151	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T9	1		T182	1		T149	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T8	3		T14	1		T48	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T8	4		T150	1		T152	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T111	1		T183	15		T159	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T164	1		T141	1		T53	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T14	1		T40	4		T136	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T46	19		T140	4		T182	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T7	1		T11	12		T144	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T14	1		T15	18		T139	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1596	1			T2	1		T12	24		T26	22
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T141	1		T145	1		T229	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	334	1			T11	6		T13	1		T181	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	322	1			T6	22		T48	11		T183	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16090	1			T1	20		T3	11		T5	17
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T234	5		T17	4		T283	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T143	7		T153	10		T90	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T240	10		T331	14		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T330	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T45	10		T140	12		T160	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T40	4		T164	8		T225	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T41	2		T160	12		T162	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T42	2		T235	15		T227	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T6	20		T140	11		T151	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T149	12		T42	2		T43	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T8	2		T48	11		T227	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T150	12		T228	10		T276	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T159	5		T221	17		T188	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T164	1		T53	9		T144	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T40	1		T136	10		T242	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T140	7		T136	13		T54	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T144	5		T188	9		T230	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T15	24		T188	2		T233	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	921	1			T205	9		T174	19		T232	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T229	12		T235	9		T155	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	307	1			T164	16		T144	6		T225	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T6	18		T48	10		T142	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T8	3		T9	1		T48	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T45	11		T41	4		T160	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T111	1		T219	1		T40	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T160	13		T152	1		T85	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T9	1		T42	11		T199	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T6	21		T14	1		T140	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T8	3		T150	13		T182	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T8	4		T48	12		T221	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T141	1		T152	1		T220	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T111	1		T40	4		T183	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T182	1		T164	2		T136	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T14	1		T136	11		T144	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T46	1		T140	8		T152	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1280	1			T2	1		T7	1		T11	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T14	1		T15	26		T139	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T11	1		T139	1		T144	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T141	1		T175	1		T143	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	337	1			T13	1		T181	1		T164	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T6	19		T48	11		T183	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T182	1		T168	13		T222	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T146	1		T165	9		T237	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16301	1			T1	20		T3	11		T5	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T7	1		T83	11		T35	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T45	12		T41	3		T160	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T40	4		T164	4		T225	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T160	2		T85	11		T162	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T42	4		T226	4		T167	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T6	18		T140	13		T218	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T8	1		T162	6		T43	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T8	1		T48	11		T221	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T228	12		T245	7		T165	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T40	1		T183	14		T159	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T144	9		T54	9		T184	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T136	10		T35	11		T184	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T46	18		T140	3		T231	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1243	1			T11	11		T12	21		T26	20
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T15	16		T139	16		T233	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T11	5		T139	9		T144	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T175	5		T143	2		T155	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T164	11		T225	13		T106	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T6	21		T48	10		T183	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T168	8		T222	9		T246	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T165	5		T237	12		T329	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T140	9		T200	11		T240	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T35	2		T185	14		T254	7

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T234	6		T17	10		T283	10
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T143	8		T217	1		T153	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T198	1		T217	1		T240	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T330	6		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T45	11		T140	13		T160	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T7	1		T219	1		T40	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T41	4		T160	13		T152	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T111	1		T42	7		T217	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T6	21		T140	12		T151	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T9	1		T182	1		T149	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T8	4		T14	1		T48	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T8	3		T150	13		T152	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T111	1		T183	1		T159	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T164	2		T141	1		T53	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T14	1		T40	4		T136	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T46	1		T140	8		T182	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T7	1		T11	1		T144	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T14	1		T15	26		T139	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1264	1			T2	1		T12	3		T26	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T141	1		T145	1		T229	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	363	1			T11	1		T13	1		T181	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T6	19		T48	11		T183	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16213	1			T1	20		T3	11		T5	17
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T17	3		T283	12		T100	16
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T143	7		T217	12		T180	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T217	8		T240	10		T331	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T330	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T45	12		T140	9		T160	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T40	4		T164	4		T225	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T41	3		T160	2		T162	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T42	2		T217	5		T167	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T6	18		T140	13		T218	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T162	6		T42	2		T43	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T8	1		T48	11		T154	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T8	1		T228	12		T244	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T183	14		T159	11		T221	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T144	9		T184	10		T165	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T40	1		T136	10		T35	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T46	18		T140	3		T54	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T11	11		T33	1		T248	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T15	16		T139	16		T233	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1253	1			T12	21		T26	20		T47	35
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T155	3		T249	1		T332	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T11	5		T164	11		T144	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T6	21		T48	10		T183	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20778

1

T1

20

T2

1

T3

11

auto[1]

auto[0]

4055

1

T6

39

T8

2

T11

16