Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24833

1

T1

20

T2

1

T3

11

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19649

1

T1

20

T3

11

T5

17

auto[ADC_CTRL_FILTER_COND_OUT]

5184

1

T2

1

T6

79

T7

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19006

1

T1

20

T3

11

T5

17

auto[1]

5827

1

T2

1

T6

79

T7

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21167

1

T1

20

T2

1

T3

11

auto[1]

3666

1

T6

38

T8

5

T9

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	251	1			T221	30		T162	7		T42	10
values[0]	85	1			T6	40		T164	2		T230	5
values[1]	747	1			T9	1		T15	27		T140	22
values[2]	526	1			T13	1		T111	1		T182	1
values[3]	731	1			T8	5		T219	1		T164	28
values[4]	507	1			T8	4		T14	1		T182	1
values[5]	716	1			T46	19		T140	11		T183	3
values[6]	741	1			T14	1		T15	15		T45	23
values[7]	657	1			T6	39		T7	1		T11	6
values[8]	597	1			T11	12		T14	1		T140	25
values[9]	3062	1			T2	1		T7	1		T12	24
minimum	16213	1			T1	20		T3	11		T5	17

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	735	1			T9	1		T13	1		T140	22
values[1]	2793	1			T2	1		T12	24		T26	22
values[2]	633	1			T8	5		T219	1		T164	28
values[3]	610	1			T8	4		T14	1		T46	19
values[4]	671	1			T45	23		T140	11		T136	14
values[5]	778	1			T11	6		T14	1		T15	15
values[6]	621	1			T6	39		T7	1		T11	12
values[7]	580	1			T7	1		T14	1		T111	1
values[8]	801	1			T181	1		T150	13		T139	17
values[9]	110	1			T162	7		T42	1		T178	9
minimum	16501	1			T1	20		T3	11		T5	17

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20778

1

T1

20

T2

1

T3

11

auto[1]

4055

1

T6

39

T8

2

T11

16

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T9	1		T13	1		T53	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T140	10		T182	1		T40	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T182	1		T149	1		T175	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1624	1			T2	1		T12	24		T26	22
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T219	1		T164	12		T225	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T8	3		T141	1		T218	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T40	5		T183	18		T152	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T8	4		T14	1		T46	19
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T45	13		T140	4		T136	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T221	11		T234	1		T265	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T14	1		T15	8		T48	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T11	6		T48	12		T144	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T11	12		T139	10		T188	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T6	19		T7	1		T151	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T14	1		T111	1		T140	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T7	1		T141	1		T107	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	292	1			T181	1		T150	1		T142	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T139	17		T106	5		T44	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T42	1		T178	1		T186	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T162	7		T320	1		T333	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16175	1			T1	20		T3	11		T5	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T6	22		T185	1		T227	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T53	9		T143	7		T160	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T140	12		T40	1		T164	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T149	12		T143	7		T42	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	889	1			T205	9		T41	2		T174	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T164	16		T225	19		T235	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T8	2		T252	1		T242	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T40	2		T236	2		T228	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T40	2		T142	13		T200	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T45	10		T140	7		T136	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T234	13		T276	3		T153	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T15	7		T48	10		T160	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T48	11		T144	9		T83	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T188	11		T162	2		T43	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T6	20		T151	12		T188	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T140	11		T164	8		T83	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T234	5		T17	4		T165	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T150	12		T142	8		T144	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T106	10		T44	2		T185	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T178	8		T186	9		T294	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T322	14		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T8	3		T9	1		T15	17
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T6	18		T185	1		T227	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T221	13		T42	8		T153	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T162	7		T185	12		T333	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T230	1		T319	11		T334	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T6	22		T164	1		T335	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T9	1		T15	10		T53	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T140	10		T182	1		T40	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T13	1		T182	1		T175	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T111	1		T217	6		T36	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T219	1		T164	12		T149	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T8	3		T141	1		T41	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T40	5		T183	15		T152	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T8	4		T14	1		T182	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T140	4		T183	3		T136	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T46	19		T234	1		T276	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T14	1		T15	8		T45	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T48	12		T221	11		T265	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T139	10		T188	1		T162	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T6	19		T7	1		T11	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T11	12		T14	1		T140	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T198	1		T107	1		T234	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	290	1			T111	1		T181	1		T150	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1617	1			T2	1		T7	1		T12	24
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16090	1			T1	20		T3	11		T5	17
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T221	17		T42	2		T153	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T185	4		T318	11		T323	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T230	4		T334	4		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T6	18		T164	1		T194	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T15	17		T53	9		T143	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T140	12		T40	1		T136	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T143	7		T42	2		T54	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T36	1		T235	9		T278	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T164	16		T149	12		T16	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T8	2		T41	2		T159	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T40	2		T225	19		T236	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T40	2		T142	13		T200	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T140	7		T136	13		T159	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T234	13		T276	3		T153	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T15	7		T45	10		T48	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T48	11		T153	9		T290	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T188	11		T162	2		T248	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T6	20		T151	12		T144	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T140	11		T164	8		T83	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T234	5		T17	4		T165	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T150	12		T142	8		T144	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	962	1			T205	9		T174	19		T232	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T8	3		T9	1		T48	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T9	1		T13	1		T53	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T140	13		T182	1		T40	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T182	1		T149	13		T175	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1224	1			T2	1		T12	3		T26	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T219	1		T164	17		T225	21
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T8	4		T141	1		T218	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T40	5		T183	2		T152	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T8	3		T14	1		T46	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T45	11		T140	8		T136	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T221	1		T234	14		T265	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T14	1		T15	8		T48	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T11	1		T48	12		T144	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T11	1		T139	1		T188	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T6	21		T7	1		T151	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T14	1		T111	1		T140	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T7	1		T141	1		T107	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T181	1		T150	13		T142	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T139	1		T106	11		T44	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T42	1		T178	9		T186	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T162	1		T320	1		T333	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16290	1			T1	20		T3	11		T5	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T6	19		T185	2		T227	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T143	7		T160	2		T245	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T140	9		T40	1		T136	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T175	5		T143	2		T42	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1289	1			T12	21		T26	20		T47	35
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T164	11		T225	16		T244	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T8	1		T218	10		T242	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T40	2		T183	16		T228	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T8	1		T46	18		T40	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T45	12		T140	3		T159	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T221	10		T265	9		T276	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T15	7		T48	10		T160	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T11	5		T48	11		T144	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T11	11		T139	9		T162	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T6	18		T106	13		T245	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T140	13		T164	4		T228	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T17	3		T269	13		T249	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T221	12		T42	2		T107	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T139	16		T106	4		T44	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T294	5		T304	11		T321	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T162	6		T333	3		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T15	9		T95	4		T336	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T6	21		T306	11		T337	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T221	18		T42	8		T153	10
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T162	1		T185	5		T333	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T230	5		T319	1		T334	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T6	19		T164	2		T335	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T9	1		T15	18		T53	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T140	13		T182	1		T40	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T13	1		T182	1		T175	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T111	1		T217	1		T36	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T219	1		T164	17		T149	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T8	4		T141	1		T41	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T40	5		T183	1		T152	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T8	3		T14	1		T182	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T140	8		T183	1		T136	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T46	1		T234	14		T276	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T14	1		T15	8		T45	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T48	12		T221	1		T265	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T139	1		T188	12		T162	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T6	21		T7	1		T11	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T11	1		T14	1		T140	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T198	1		T107	1		T234	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T111	1		T181	1		T150	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1310	1			T2	1		T7	1		T12	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16213	1			T1	20		T3	11		T5	17
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T221	12		T42	2		T100	16
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T162	6		T185	11		T333	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T319	10		T334	13		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T6	21		T194	3		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T15	9		T143	7		T160	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T140	9		T40	1		T136	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T175	5		T143	2		T42	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T217	5		T184	12		T185	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T164	11		T207	9		T259	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T8	1		T41	3		T159	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T40	2		T183	14		T225	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T8	1		T40	2		T218	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T140	3		T183	2		T159	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T46	18		T276	2		T309	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T15	7		T45	12		T48	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T48	11		T221	10		T265	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T139	9		T162	4		T248	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T6	18		T11	5		T144	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T11	11		T140	13		T164	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T17	3		T288	8		T179	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T107	13		T33	1		T226	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1269	1			T12	21		T26	20		T47	35

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20778

1

T1

20

T2

1

T3

11

auto[1]

auto[0]

4055

1

T6

39

T8

2

T11

16