Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_6

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	342	1			T8	3		T53	10		T244	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T7	1		T140	13		T182	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1279	1			T2	1		T11	1		T12	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T14	1		T182	1		T141	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T11	1		T40	4		T164	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T183	1		T162	1		T189	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T139	1		T142	14		T160	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T175	1		T225	6		T54	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T164	17		T136	14		T152	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T140	12		T40	5		T221	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T6	19		T83	11		T228	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T14	1		T149	13		T153	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T6	21		T14	1		T181	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T111	1		T48	12		T219	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T150	13		T183	1		T198	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T7	1		T8	4		T15	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T9	1		T111	1		T48	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T15	18		T139	1		T136	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T188	10		T189	1		T185	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T13	1		T145	1		T252	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16213	1			T1	20		T3	11		T5	17
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	292	1			T8	1		T244	8		T44	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T140	9		T143	2		T144	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1265	1			T11	5		T12	21		T26	20
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T16	1		T184	1		T190	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T11	11		T40	1		T218	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T183	14		T162	6		T259	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T139	16		T160	2		T42	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T175	5		T225	3		T54	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T164	11		T85	11		T260	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T140	13		T40	2		T221	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T6	21		T228	12		T261	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T184	10		T262	10		T167	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T6	18		T160	11		T225	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T48	11		T221	12		T106	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T183	2		T159	13		T239	20
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T8	1		T15	7		T46	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T48	10		T40	2		T41	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T15	9		T139	9		T136	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T185	14		T254	7		T263	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T264	12		T192	18		T256	8

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T99	10		T223	3		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T250	1		T257	1		T258	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T144	6		T251	3		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T11	1		T53	10		T244	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T7	1		T182	1		T143	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1323	1			T2	1		T8	3		T12	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T14	1		T140	13		T144	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T11	1		T140	8		T40	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T182	1		T141	1		T183	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T139	1		T160	13		T144	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T225	6		T54	8		T230	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T164	17		T142	14		T136	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T140	12		T40	5		T175	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T6	19		T181	1		T83	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T14	1		T149	13		T106	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T6	21		T183	1		T142	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T111	1		T48	12		T221	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T14	1		T150	13		T198	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T8	4		T15	8		T46	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	302	1			T9	1		T111	1		T48	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	306	1			T7	1		T13	1		T15	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16213	1			T1	20		T3	11		T5	17
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T99	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T250	1		T257	16		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T11	5		T244	8		T44	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T143	2		T228	6		T217	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1284	1			T8	1		T12	21		T26	20
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T140	9		T144	9		T42	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T11	11		T140	3		T40	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T183	14		T162	6		T259	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T139	16		T160	2		T144	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T225	3		T54	9		T33	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T164	11		T85	11		T260	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T140	13		T40	2		T175	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T6	21		T226	11		T245	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T106	13		T265	9		T184	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T6	18		T183	2		T160	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T48	11		T221	12		T106	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T159	13		T155	4		T239	20
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T8	1		T15	7		T46	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	303	1			T48	10		T40	2		T41	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T15	9		T139	9		T136	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20778

1

T1

20

T2

1

T3

11

auto[1]

auto[0]

4055

1

T6

39

T8

2

T11

16