Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24833

1

T1

20

T2

1

T3

11

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21696

1

T1

20

T2

1

T3

11

auto[ADC_CTRL_FILTER_COND_OUT]

3137

1

T7

1

T8

4

T9

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19155

1

T1

20

T3

11

T5

17

auto[1]

5678

1

T2

1

T6

39

T7

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21167

1

T1

20

T2

1

T3

11

auto[1]

3666

1

T6

38

T8

5

T9

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	7	1			T202	7		-	-		-	-
values[0]	77	1			T11	12		T111	1		T248	22
values[1]	727	1			T13	1		T14	1		T140	11
values[2]	810	1			T8	5		T14	1		T139	27
values[3]	543	1			T6	39		T48	21		T40	5
values[4]	618	1			T150	13		T151	13		T149	13
values[5]	608	1			T15	27		T140	25		T182	1
values[6]	703	1			T7	2		T9	1		T45	23
values[7]	744	1			T11	6		T14	1		T15	15
values[8]	503	1			T6	40		T8	4		T181	1
values[9]	3280	1			T2	1		T12	24		T26	22
minimum	16213	1			T1	20		T3	11		T5	17

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1108	1			T8	5		T11	12		T13	1
values[1]	660	1			T6	39		T48	21		T139	17
values[2]	482	1			T150	13		T198	1		T152	1
values[3]	647	1			T140	25		T151	13		T149	13
values[4]	655	1			T7	1		T9	1		T15	27
values[5]	648	1			T7	1		T15	15		T182	1
values[6]	2976	1			T2	1		T11	6		T12	24
values[7]	642	1			T6	40		T8	4		T181	1
values[8]	591	1			T48	23		T183	3		T142	9
values[9]	184	1			T46	19		T144	6		T189	1
minimum	16240	1			T1	20		T3	11		T5	17

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20778

1

T1

20

T2

1

T3

11

auto[1]

4055

1

T6

39

T8

2

T11

16

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T8	3		T111	1		T139	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	359	1			T11	12		T13	1		T14	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T6	19		T139	17		T40	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T48	11		T221	11		T229	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T152	1		T266	1		T236	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T150	1		T198	1		T226	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T140	14		T136	11		T89	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T151	1		T149	1		T146	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T7	1		T45	13		T111	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T9	1		T15	10		T182	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T182	1		T16	4		T248	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T7	1		T15	8		T164	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1646	1			T2	1		T12	24		T26	22
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T11	6		T14	1		T83	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T6	22		T183	15		T159	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T8	4		T181	1		T40	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T142	1		T145	1		T42	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T48	12		T183	3		T159	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T46	19		T166	1		T267	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T144	1		T189	1		T154	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16105	1			T1	20		T3	11		T5	17
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T8	2		T140	7		T164	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T143	7		T144	6		T225	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T6	20		T40	2		T142	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T48	10		T229	12		T191	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T236	2		T226	9		T242	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T150	12		T226	10		T95	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T140	11		T136	10		T153	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T151	12		T149	12		T228	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T45	10		T41	2		T143	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T15	17		T164	16		T53	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T16	1		T248	19		T235	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T15	7		T164	8		T160	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	953	1			T140	12		T40	1		T205	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T83	2		T106	10		T44	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T6	18		T159	5		T44	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T40	2		T188	2		T242	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T142	8		T42	2		T228	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T48	11		T159	14		T188	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T267	8		T223	2		T268	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T144	5		T269	12		T270	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T8	3		T9	1		T48	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T202	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T111	1		T247	14		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T11	12		T248	11		T249	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T140	4		T164	1		T218	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T13	1		T14	1		T175	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T8	3		T139	27		T142	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T14	1		T221	11		T106	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T6	19		T40	3		T266	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T48	11		T198	1		T154	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T136	11		T89	1		T236	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T150	1		T151	1		T149	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T140	14		T141	2		T143	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T15	10		T182	1		T164	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T7	1		T45	13		T111	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T7	1		T9	1		T182	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T140	10		T85	12		T220	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T11	6		T14	1		T15	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T6	22		T40	4		T152	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T8	4		T181	1		T40	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1766	1			T2	1		T12	24		T26	22
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T48	12		T183	3		T159	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16090	1			T1	20		T3	11		T5	17
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T202	6		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T247	16		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T248	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T140	7		T164	1		T136	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T143	7		T144	6		T225	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T8	2		T142	13		T160	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T106	12		T245	11		T227	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T6	20		T40	2		T242	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T48	10		T229	12		T95	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T136	10		T236	2		T226	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T150	12		T151	12		T149	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T140	11		T143	7		T144	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T15	17		T164	16		T53	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T45	10		T41	2		T16	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T164	8		T225	5		T221	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T140	12		T85	9		T162	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T15	7		T83	2		T106	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T6	18		T40	1		T17	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T40	2		T188	2		T229	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1010	1			T205	9		T142	8		T174	19
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T48	11		T159	14		T144	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T8	3		T9	1		T48	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T8	4		T111	1		T139	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	303	1			T11	1		T13	1		T14	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T6	21		T139	1		T40	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T48	11		T221	1		T229	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T152	1		T266	1		T236	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T150	13		T198	1		T226	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T140	12		T136	11		T89	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T151	13		T149	13		T146	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T7	1		T45	11		T111	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T9	1		T15	18		T182	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T182	1		T16	4		T248	20
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T7	1		T15	8		T164	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1299	1			T2	1		T12	3		T26	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T11	1		T14	1		T83	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T6	19		T183	1		T159	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T8	3		T181	1		T40	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T142	9		T145	1		T42	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T48	12		T183	1		T159	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T46	1		T166	1		T267	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T144	6		T189	1		T154	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16226	1			T1	20		T3	11		T5	17
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T8	1		T139	9		T140	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	311	1			T11	11		T175	5		T143	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T6	18		T139	16		T40	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T48	10		T221	10		T239	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T162	6		T33	1		T226	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T226	2		T95	4		T99	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T140	13		T136	10		T107	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T228	12		T265	9		T154	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T45	12		T41	3		T143	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T15	9		T164	11		T225	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T16	1		T248	10		T184	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T15	7		T164	4		T160	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1300	1			T12	21		T26	20		T47	35
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T11	5		T260	17		T106	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T6	21		T183	14		T159	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T8	1		T40	2		T242	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T42	2		T228	6		T184	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T48	11		T183	2		T159	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T46	18		T267	8		T271	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T269	13		T270	4		T272	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T273	14		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T202	7		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T111	1		T247	17		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T11	1		T248	12		T249	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T140	8		T164	2		T218	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T13	1		T14	1		T175	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T8	4		T139	2		T142	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T14	1		T221	1		T106	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T6	21		T40	3		T266	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T48	11		T198	1		T154	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T136	11		T89	1		T236	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T150	13		T151	13		T149	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T140	12		T141	2		T143	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T15	18		T182	1		T164	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T7	1		T45	11		T111	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T7	1		T9	1		T182	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T140	13		T85	10		T220	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T11	1		T14	1		T15	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T6	19		T40	4		T152	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T8	3		T181	1		T40	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1373	1			T2	1		T12	3		T26	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T48	12		T183	1		T159	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16213	1			T1	20		T3	11		T5	17
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T247	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T11	11		T248	10		T249	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T140	3		T218	10		T217	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T175	5		T143	7		T144	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T8	1		T139	25		T160	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T221	10		T106	13		T245	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T6	18		T40	2		T244	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T48	10		T154	1		T185	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T136	10		T162	6		T35	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T228	12		T265	9		T226	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T140	13		T143	2		T144	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T15	9		T164	11		T160	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T45	12		T41	3		T16	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T164	4		T225	3		T221	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T140	9		T85	11		T162	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T11	5		T15	7		T260	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T6	21		T40	1		T217	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T8	1		T40	2		T190	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1403	1			T12	21		T26	20		T46	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T48	11		T183	2		T159	13

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20778

1

T1

20

T2

1

T3

11

auto[1]

auto[0]

4055

1

T6

39

T8

2

T11

16