Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24833

1

T1

20

T2

1

T3

11

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21734

1

T1

20

T2

1

T3

11

auto[ADC_CTRL_FILTER_COND_OUT]

3099

1

T6

39

T7

1

T8

4

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19000

1

T1

20

T3

11

T5

17

auto[1]

5833

1

T2

1

T6

40

T7

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21167

1

T1

20

T2

1

T3

11

auto[1]

3666

1

T6

38

T8

5

T9

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	31	1			T226	13		T274	18		-	-
values[0]	10	1			T89	1		T180	8		T275	1
values[1]	598	1			T7	1		T11	6		T14	2
values[2]	620	1			T9	1		T48	21		T182	1
values[3]	738	1			T15	27		T140	22		T219	1
values[4]	810	1			T14	1		T45	23		T111	1
values[5]	2813	1			T2	1		T7	1		T12	24
values[6]	559	1			T8	5		T15	15		T139	10
values[7]	715	1			T46	19		T140	25		T218	11
values[8]	515	1			T13	1		T139	17		T182	1
values[9]	1211	1			T6	79		T8	4		T11	12
minimum	16213	1			T1	20		T3	11		T5	17

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	684	1			T7	1		T11	6		T14	2
values[1]	686	1			T9	1		T182	1		T136	35
values[2]	738	1			T15	27		T111	1		T140	22
values[3]	3101	1			T2	1		T7	1		T12	24
values[4]	444	1			T15	15		T164	28		T198	1
values[5]	614	1			T8	5		T139	10		T140	11
values[6]	730	1			T13	1		T46	19		T140	25
values[7]	626	1			T6	79		T181	1		T139	17
values[8]	826	1			T111	1		T150	13		T48	23
values[9]	158	1			T8	4		T11	12		T162	7
minimum	16226	1			T1	20		T3	11		T5	17

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20778

1

T1

20

T2

1

T3

11

auto[1]

4055

1

T6

39

T8

2

T11

16

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T7	1		T11	6		T48	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T14	2		T40	4		T198	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T9	1		T182	1		T136	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T136	11		T83	1		T85	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T15	10		T111	1		T140	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T219	1		T182	1		T183	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1693	1			T2	1		T12	24		T26	22
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T7	1		T14	1		T164	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T164	12		T198	1		T152	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T15	8		T162	7		T42	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T8	3		T139	10		T152	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T140	4		T41	5		T53	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T13	1		T46	19		T40	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T140	14		T231	8		T155	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T6	22		T182	1		T159	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T6	19		T181	1		T139	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T150	1		T48	12		T143	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T111	1		T149	1		T83	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T11	12		T162	5		T187	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T8	4		T226	3		T95	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16090	1			T1	20		T3	11		T5	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T164	5		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T48	10		T188	11		T234	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T40	1		T160	9		T144	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T136	13		T54	7		T276	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T136	10		T83	2		T85	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T15	17		T140	12		T142	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T143	7		T221	17		T235	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1006	1			T45	10		T151	12		T205	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T164	1		T36	1		T248	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T164	16		T230	4		T224	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T15	7		T42	2		T224	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T8	2		T188	2		T228	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T140	7		T41	2		T53	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T40	2		T142	8		T106	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T140	11		T231	7		T155	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T6	18		T159	14		T44	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T6	20		T40	2		T241	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T150	12		T48	11		T143	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T149	12		T83	10		T252	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T162	2		T187	10		T277	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T226	9		T95	7		T278	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T8	3		T9	1		T48	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T164	8		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T226	3		T274	18		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T89	1		T180	8		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T275	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T7	1		T11	6		T234	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T14	2		T40	4		T164	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T9	1		T48	11		T182	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T136	11		T144	8		T220	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T15	10		T140	10		T144	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T219	1		T183	18		T143	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T45	13		T111	1		T159	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T14	1		T182	1		T146	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1638	1			T2	1		T12	24		T26	22
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T7	1		T140	4		T164	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T8	3		T139	10		T198	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T15	8		T41	5		T220	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T46	19		T218	11		T142	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T140	14		T53	1		T225	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T13	1		T182	1		T40	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T139	17		T141	1		T189	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	337	1			T6	22		T11	12		T150	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	331	1			T6	19		T8	4		T111	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16090	1			T1	20		T3	11		T5	17
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T226	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T234	5		T153	9		T235	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T40	1		T164	8		T160	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T48	10		T142	13		T136	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T136	10		T144	6		T188	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T15	17		T140	12		T144	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T143	7		T83	2		T85	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T45	10		T159	5		T43	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T36	1		T248	11		T242	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	931	1			T151	12		T164	16		T205	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T140	7		T164	1		T235	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T8	2		T228	10		T44	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T15	7		T41	2		T42	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T142	8		T188	2		T106	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T140	11		T53	9		T225	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T40	2		T44	2		T245	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T241	13		T167	10		T279	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T6	18		T150	12		T48	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T6	20		T40	2		T149	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T8	3		T9	1		T48	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T7	1		T11	1		T48	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T14	2		T40	4		T198	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T9	1		T182	1		T136	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T136	11		T83	3		T85	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T15	18		T111	1		T140	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T219	1		T182	1		T183	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1353	1			T2	1		T12	3		T26	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T7	1		T14	1		T164	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T164	17		T198	1		T152	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T15	8		T162	1		T42	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T8	4		T139	1		T152	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T140	8		T41	4		T53	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T13	1		T46	1		T40	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T140	12		T231	8		T155	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T6	19		T182	1		T159	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T6	21		T181	1		T139	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T150	13		T48	12		T143	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T111	1		T149	13		T83	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T11	1		T162	3		T187	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T8	3		T226	10		T95	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16213	1			T1	20		T3	11		T5	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T164	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T11	5		T48	10		T154	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T40	1		T160	11		T144	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T217	12		T54	9		T276	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T136	10		T85	11		T165	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T15	9		T140	9		T43	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T183	16		T143	2		T260	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1346	1			T12	21		T26	20		T45	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T248	10		T242	9		T245	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T164	11		T239	20		T262	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T15	7		T162	6		T42	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T8	1		T139	9		T228	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T140	3		T41	3		T225	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T46	18		T40	2		T218	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T140	13		T231	7		T155	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T6	21		T159	13		T221	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T6	18		T139	16		T40	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T48	11		T143	7		T160	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T244	8		T226	2		T242	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T11	11		T162	4		T187	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T8	1		T226	2		T95	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T164	4		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T226	11		T274	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T89	1		T180	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T275	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T7	1		T11	1		T234	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T14	2		T40	4		T164	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T9	1		T48	11		T182	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T136	11		T144	7		T220	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T15	18		T140	13		T144	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T219	1		T183	2		T143	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T45	11		T111	1		T159	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T14	1		T182	1		T146	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1266	1			T2	1		T12	3		T26	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T7	1		T140	8		T164	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T8	4		T139	1		T198	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T15	8		T41	4		T220	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T46	1		T218	1		T142	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T140	12		T53	10		T225	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T13	1		T182	1		T40	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T139	1		T141	1		T189	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	317	1			T6	19		T11	1		T150	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	340	1			T6	21		T8	3		T111	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16213	1			T1	20		T3	11		T5	17
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T226	2		T274	17		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T180	7		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T11	5		T154	1		T99	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T40	1		T164	4		T160	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T48	10		T201	6		T280	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T136	10		T144	7		T184	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T15	9		T140	9		T144	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T183	16		T143	2		T85	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T45	12		T159	11		T43	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T248	10		T242	9		T245	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1303	1			T12	21		T26	20		T47	35
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T140	3		T162	6		T107	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T8	1		T139	9		T228	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T15	7		T41	3		T42	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T46	18		T218	10		T106	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T140	13		T225	13		T42	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T40	2		T175	5		T44	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T139	16		T100	16		T167	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T6	21		T11	11		T48	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T6	18		T8	1		T40	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20778

1

T1

20

T2

1

T3

11

auto[1]

auto[0]

4055

1

T6

39

T8

2

T11

16