Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24833

1

T1

20

T2

1

T3

11

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21558

1

T1

20

T2

1

T3

11

auto[ADC_CTRL_FILTER_COND_OUT]

3275

1

T6

79

T8

9

T11

18

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19144

1

T1

20

T3

11

T5

17

auto[1]

5689

1

T2

1

T6

39

T7

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21167

1

T1

20

T2

1

T3

11

auto[1]

3666

1

T6

38

T8

5

T9

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	242	1			T9	1		T144	19		T152	1
values[0]	15	1			T143	15		-	-		-	-
values[1]	695	1			T6	39		T182	1		T183	3
values[2]	691	1			T8	4		T111	1		T182	1
values[3]	466	1			T7	1		T11	6		T14	1
values[4]	644	1			T14	1		T48	21		T140	22
values[5]	2881	1			T2	1		T8	5		T12	24
values[6]	739	1			T11	12		T40	7		T149	13
values[7]	703	1			T13	1		T40	5		T136	14
values[8]	675	1			T7	1		T14	1		T46	19
values[9]	869	1			T6	40		T45	23		T139	17
minimum	16213	1			T1	20		T3	11		T5	17

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	502	1			T6	39		T182	1		T183	3
values[1]	825	1			T8	4		T111	1		T182	1
values[2]	357	1			T7	1		T11	6		T14	2
values[3]	2933	1			T2	1		T8	5		T12	24
values[4]	638	1			T15	27		T140	25		T40	7
values[5]	793	1			T11	12		T149	13		T160	15
values[6]	628	1			T13	1		T139	10		T40	5
values[7]	661	1			T7	1		T14	1		T46	19
values[8]	808	1			T9	1		T45	23		T139	17
values[9]	176	1			T6	40		T219	1		T152	1
minimum	16512	1			T1	20		T3	11		T5	17

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20778

1

T1

20

T2

1

T3

11

auto[1]

4055

1

T6

39

T8

2

T11

16

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T183	3		T220	1		T217	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T6	19		T182	1		T225	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T111	1		T182	1		T160	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T8	4		T164	5		T142	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T7	1		T14	1		T136	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T11	6		T14	1		T111	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1657	1			T2	1		T12	24		T15	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T8	3		T181	1		T140	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T140	14		T164	13		T183	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T15	10		T40	5		T152	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T149	1		T221	13		T220	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T11	12		T160	3		T266	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T13	1		T40	3		T136	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T139	10		T260	18		T42	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T7	1		T46	19		T150	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T14	1		T48	12		T198	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T9	1		T144	10		T162	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T45	13		T139	17		T175	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T152	1		T146	1		T106	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T6	22		T219	1		T233	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16137	1			T1	20		T3	11		T5	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T53	1		T98	1		T280	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T36	1		T153	9		T287	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T6	20		T225	14		T231	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T160	9		T85	9		T253	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T164	8		T142	8		T233	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T136	10		T235	13		T241	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T288	4		T289	9		T267	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	973	1			T15	7		T48	10		T151	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T8	2		T140	12		T40	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T140	11		T164	17		T41	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T15	17		T40	2		T188	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T149	12		T221	17		T106	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T160	12		T225	5		T44	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T40	2		T136	13		T159	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T226	10		T227	1		T90	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T150	12		T140	7		T143	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T48	11		T188	11		T234	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T144	9		T290	2		T233	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T45	10		T159	14		T42	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T106	12		T207	9		T291	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T6	18		T233	10		T286	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T8	3		T9	1		T48	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T53	9		T280	12		T292	11

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T9	1		T144	10		T152	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T229	1		T259	15		T168	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T143	8		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T183	3		T142	1		T217	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T6	19		T182	1		T53	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T111	1		T182	1		T220	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T8	4		T164	5		T142	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T7	1		T14	1		T160	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T11	6		T111	1		T141	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T48	11		T182	1		T151	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T14	1		T140	10		T141	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1684	1			T2	1		T12	24		T15	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T8	3		T15	10		T181	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T149	1		T221	13		T220	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T11	12		T40	5		T160	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T13	1		T40	3		T136	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T42	1		T244	9		T199	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T7	1		T46	19		T150	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T14	1		T48	12		T139	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T152	1		T162	7		T189	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T6	22		T45	13		T139	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16090	1			T1	20		T3	11		T5	17
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T144	9		T207	9		T271	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T229	10		T259	13		T168	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T143	7		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T142	13		T36	1		T153	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T6	20		T53	9		T231	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T54	7		T44	4		T177	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T164	8		T142	8		T225	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T160	9		T85	9		T253	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T233	1		T288	4		T279	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T48	10		T151	12		T136	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T140	12		T83	2		T226	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	928	1			T15	7		T140	11		T164	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T8	2		T15	17		T40	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T149	12		T221	17		T188	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T40	2		T160	12		T225	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T40	2		T136	13		T159	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T226	10		T227	1		T241	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T150	12		T140	7		T143	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T48	11		T188	11		T16	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T106	12		T248	11		T165	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T6	18		T45	10		T159	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T8	3		T9	1		T48	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T183	1		T220	1		T217	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T6	21		T182	1		T225	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T111	1		T182	1		T160	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T8	3		T164	9		T142	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T7	1		T14	1		T136	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T11	1		T14	1		T111	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1317	1			T2	1		T12	3		T15	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T8	4		T181	1		T140	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T140	12		T164	19		T183	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T15	18		T40	5		T152	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T149	13		T221	18		T220	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T11	1		T160	13		T266	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T13	1		T40	3		T136	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T139	1		T260	1		T42	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T7	1		T46	1		T150	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T14	1		T48	12		T198	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T9	1		T144	10		T162	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T45	11		T139	1		T175	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T152	1		T146	1		T106	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T6	19		T219	1		T233	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16268	1			T1	20		T3	11		T5	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T53	10		T98	1		T280	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T183	2		T217	5		T249	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T6	18		T225	13		T231	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T160	11		T85	11		T54	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T8	1		T164	4		T221	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T136	10		T239	14		T293	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T11	5		T154	1		T262	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1313	1			T12	21		T15	7		T26	20
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T8	1		T140	9		T40	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T140	13		T164	11		T183	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T15	9		T40	2		T228	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T221	12		T106	4		T43	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T11	11		T160	2		T225	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T40	2		T159	11		T162	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T139	9		T260	17		T244	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T46	18		T140	3		T143	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T48	11		T107	13		T16	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T144	9		T162	6		T35	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T45	12		T139	16		T175	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T106	13		T207	9		T291	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T6	21		T233	10		T264	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T143	7		T165	5		T192	20
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T280	12		T292	16		T294	3

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T9	1		T144	10		T152	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T229	11		T259	14		T168	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T143	8		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T183	1		T142	14		T217	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T6	21		T182	1		T53	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T111	1		T182	1		T220	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T8	3		T164	9		T142	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T7	1		T14	1		T160	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T11	1		T111	1		T141	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T48	11		T182	1		T151	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T14	1		T140	13		T141	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1279	1			T2	1		T12	3		T15	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T8	4		T15	18		T181	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T149	13		T221	18		T220	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T11	1		T40	5		T160	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T13	1		T40	3		T136	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T42	1		T244	1		T199	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T7	1		T46	1		T150	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T14	1		T48	12		T139	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T152	1		T162	1		T189	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T6	19		T45	11		T139	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16213	1			T1	20		T3	11		T5	17
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T144	9		T35	11		T207	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T259	14		T168	8		T264	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T143	7		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T183	2		T217	5		T165	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T6	18		T231	7		T99	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T54	9		T44	7		T200	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T8	1		T164	4		T225	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T160	11		T85	11		T242	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T11	5		T221	10		T217	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T48	10		T183	14		T136	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T140	9		T218	10		T217	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1333	1			T12	21		T15	7		T26	20
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T8	1		T15	9		T40	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T221	12		T106	4		T228	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T11	11		T40	2		T160	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T40	2		T159	11		T162	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T244	8		T226	2		T184	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T46	18		T140	3		T143	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T48	11		T139	9		T260	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T162	6		T106	13		T248	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T6	21		T45	12		T139	16

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20778

1

T1

20

T2

1

T3

11

auto[1]

auto[0]

4055

1

T6

39

T8

2

T11

16