Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24833

1

T1

20

T2

1

T3

11

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21607

1

T1

20

T2

1

T3

11

auto[ADC_CTRL_FILTER_COND_OUT]

3226

1

T7

1

T8

4

T9

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19278

1

T1

20

T3

11

T5

17

auto[1]

5555

1

T2

1

T6

39

T7

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21167

1

T1

20

T2

1

T3

11

auto[1]

3666

1

T6

38

T8

5

T9

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	264	1			T46	19		T48	23		T183	3
values[0]	46	1			T11	12		T248	22		T249	12
values[1]	756	1			T13	1		T14	1		T111	1
values[2]	793	1			T8	5		T14	1		T139	27
values[3]	531	1			T6	39		T48	21		T40	5
values[4]	678	1			T150	13		T140	25		T151	13
values[5]	575	1			T15	27		T182	1		T164	28
values[6]	711	1			T7	2		T9	1		T45	23
values[7]	734	1			T11	6		T14	1		T15	15
values[8]	529	1			T6	40		T8	4		T181	1
values[9]	3003	1			T2	1		T12	24		T26	22
minimum	16213	1			T1	20		T3	11		T5	17

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	798	1			T11	12		T13	1		T14	1
values[1]	709	1			T6	39		T8	5		T48	21
values[2]	576	1			T150	13		T151	13		T198	1
values[3]	559	1			T140	25		T149	13		T89	1
values[4]	614	1			T7	1		T9	1		T15	27
values[5]	707	1			T7	1		T15	15		T182	1
values[6]	2948	1			T2	1		T11	6		T12	24
values[7]	635	1			T6	40		T8	4		T181	1
values[8]	671	1			T48	23		T183	3		T142	9
values[9]	117	1			T46	19		T144	6		T189	1
minimum	16499	1			T1	20		T3	11		T5	17

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20778

1

T1

20

T2

1

T3

11

auto[1]

4055

1

T6

39

T8

2

T11

16

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T139	10		T140	4		T136	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T11	12		T13	1		T14	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T6	19		T8	3		T139	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T48	11		T40	3		T36	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T136	11		T152	1		T266	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T150	1		T151	1		T198	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T140	14		T89	1		T107	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T149	1		T146	1		T228	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T7	1		T45	13		T111	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T9	1		T15	10		T182	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T15	8		T182	1		T16	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T7	1		T164	5		T41	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1631	1			T2	1		T12	24		T26	22
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T11	6		T14	1		T40	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T6	22		T152	1		T145	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T8	4		T181	1		T40	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T142	1		T159	12		T42	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T48	12		T183	3		T159	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T46	19		T223	1		T268	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T144	1		T189	1		T202	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16158	1			T1	20		T3	11		T5	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T14	1		T143	8		T225	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T140	7		T136	13		T253	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T144	6		T83	10		T106	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T6	20		T8	2		T142	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T48	10		T40	2		T36	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T136	10		T236	2		T226	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T150	12		T151	12		T226	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T140	11		T153	10		T290	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T149	12		T228	10		T235	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T45	10		T53	9		T143	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T15	17		T164	16		T225	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T15	7		T16	1		T248	19
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T164	8		T41	2		T160	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	946	1			T140	12		T205	9		T174	19
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T40	1		T83	2		T106	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T6	18		T44	4		T153	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T40	2		T188	2		T242	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T142	8		T159	5		T42	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T48	11		T159	14		T188	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T223	2		T268	4		T271	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T144	5		T202	6		T272	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T8	3		T9	1		T48	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T143	7		T225	14		T248	11

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T46	19		T107	1		T262	17
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T48	12		T183	3		T144	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T11	12		T248	11		T249	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T111	1		T140	4		T164	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T13	1		T14	1		T218	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	304	1			T8	3		T139	27		T142	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T14	1		T106	14		T36	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T6	19		T152	1		T266	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T48	11		T40	3		T198	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T140	14		T136	11		T89	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T150	1		T151	1		T149	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T141	2		T53	1		T143	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T15	10		T182	1		T164	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T7	1		T45	13		T111	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T7	1		T9	1		T164	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T15	8		T140	10		T85	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T11	6		T14	1		T40	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T6	22		T152	1		T146	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T8	4		T181	1		T40	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1654	1			T2	1		T12	24		T26	22
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T183	15		T159	14		T189	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16090	1			T1	20		T3	11		T5	17
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T223	2		T271	9		T238	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T48	11		T144	5		T188	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T248	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T140	7		T164	1		T136	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T143	7		T144	6		T225	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T8	2		T142	13		T160	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T106	12		T36	1		T227	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T6	20		T226	9		T242	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T48	10		T40	2		T229	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T140	11		T136	10		T236	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T150	12		T151	12		T149	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T53	9		T143	7		T144	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T15	17		T164	16		T225	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T45	10		T16	1		T248	19
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T164	8		T41	2		T160	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T15	7		T140	12		T85	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T40	1		T83	2		T106	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T6	18		T44	4		T17	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T40	2		T188	2		T242	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	957	1			T205	9		T142	8		T174	19
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T159	14		T276	3		T165	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T8	3		T9	1		T48	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T139	1		T140	8		T136	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T11	1		T13	1		T14	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T6	21		T8	4		T139	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T48	11		T40	3		T36	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T136	11		T152	1		T266	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T150	13		T151	13		T198	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T140	12		T89	1		T107	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T149	13		T146	1		T228	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T7	1		T45	11		T111	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T9	1		T15	18		T182	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T15	8		T182	1		T16	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T7	1		T164	9		T41	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1286	1			T2	1		T12	3		T26	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T11	1		T14	1		T40	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T6	19		T152	1		T145	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T8	3		T181	1		T40	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T142	9		T159	6		T42	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T48	12		T183	1		T159	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T46	1		T223	3		T268	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T144	6		T189	1		T202	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16280	1			T1	20		T3	11		T5	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T14	1		T143	8		T225	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T139	9		T140	3		T217	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T11	11		T218	10		T175	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T6	18		T8	1		T139	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T48	10		T40	2		T239	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T136	10		T162	6		T33	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T226	2		T154	1		T185	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T140	13		T107	13		T35	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T228	12		T265	9		T192	20
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T45	12		T143	2		T144	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T15	9		T164	11		T225	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T15	7		T16	1		T248	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T164	4		T41	3		T160	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1291	1			T12	21		T26	20		T47	35
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T11	5		T40	1		T260	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T6	21		T217	12		T44	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T8	1		T40	2		T183	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T159	11		T42	2		T228	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T48	11		T183	2		T159	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T46	18		T271	9		T295	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T272	11		T296	14		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T279	10		T273	14		T277	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T143	7		T225	13		T248	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T46	1		T107	1		T262	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T48	12		T183	1		T144	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T11	1		T248	12		T249	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T111	1		T140	8		T164	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T13	1		T14	1		T218	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T8	4		T139	2		T142	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T14	1		T106	13		T36	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T6	21		T152	1		T266	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T48	11		T40	3		T198	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T140	12		T136	11		T89	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T150	13		T151	13		T149	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T141	2		T53	10		T143	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T15	18		T182	1		T164	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T7	1		T45	11		T111	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T7	1		T9	1		T164	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T15	8		T140	13		T85	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T11	1		T14	1		T40	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T6	19		T152	1		T146	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T8	3		T181	1		T40	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1306	1			T2	1		T12	3		T26	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T183	1		T159	15		T189	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16213	1			T1	20		T3	11		T5	17
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T46	18		T262	16		T271	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T48	11		T183	2		T297	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T11	11		T248	10		T249	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T140	3		T217	5		T279	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T218	10		T175	5		T143	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T8	1		T139	25		T160	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T106	13		T239	14		T262	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T6	18		T244	8		T33	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T48	10		T40	2		T154	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T140	13		T136	10		T162	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T228	12		T265	9		T226	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T143	2		T144	9		T107	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T15	9		T164	11		T225	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T45	12		T16	1		T248	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T164	4		T41	3		T160	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T15	7		T140	9		T85	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T11	5		T40	1		T260	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T6	21		T217	12		T44	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T8	1		T40	2		T242	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1305	1			T12	21		T26	20		T47	35
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T183	14		T159	13		T276	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20778

1

T1

20

T2

1

T3

11

auto[1]

auto[0]

4055

1

T6

39

T8

2

T11

16