Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24833

1

T1

20

T2

1

T3

11

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21717

1

T1

20

T2

1

T3

11

auto[ADC_CTRL_FILTER_COND_OUT]

3116

1

T6

39

T7

1

T8

4

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18979

1

T1

20

T3

11

T5

17

auto[1]

5854

1

T2

1

T6

40

T7

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21167

1

T1

20

T2

1

T3

11

auto[1]

3666

1

T6

38

T8

5

T9

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	268	1			T8	4		T150	13		T160	15
values[0]	2	1			T89	1		T275	1		-	-
values[1]	611	1			T7	1		T11	6		T14	2
values[2]	613	1			T9	1		T48	21		T182	1
values[3]	746	1			T15	27		T140	22		T219	1
values[4]	870	1			T7	1		T14	1		T45	23
values[5]	2720	1			T2	1		T12	24		T26	22
values[6]	625	1			T8	5		T15	15		T139	10
values[7]	710	1			T46	19		T140	25		T218	11
values[8]	471	1			T13	1		T139	17		T182	1
values[9]	984	1			T6	79		T11	12		T111	1
minimum	16213	1			T1	20		T3	11		T5	17

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	505	1			T7	1		T11	6		T14	2
values[1]	650	1			T9	1		T182	1		T136	35
values[2]	712	1			T14	1		T15	27		T111	1
values[3]	3112	1			T2	1		T7	1		T12	24
values[4]	508	1			T15	15		T140	11		T164	28
values[5]	532	1			T8	5		T139	10		T41	7
values[6]	735	1			T13	1		T46	19		T140	25
values[7]	570	1			T6	39		T181	1		T139	17
values[8]	949	1			T6	40		T111	1		T150	13
values[9]	109	1			T8	4		T11	12		T162	7
minimum	16451	1			T1	20		T3	11		T5	17

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20778

1

T1

20

T2

1

T3

11

auto[1]

4055

1

T6

39

T8

2

T11

16

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T7	1		T11	6		T48	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T14	2		T198	1		T144	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T9	1		T182	1		T136	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T136	11		T83	1		T85	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T15	10		T111	1		T140	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T14	1		T219	1		T183	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1711	1			T2	1		T12	24		T26	22
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T7	1		T182	1		T164	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T164	12		T198	1		T228	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T15	8		T140	4		T162	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T8	3		T139	10		T152	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T41	5		T53	1		T225	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T13	1		T46	19		T40	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T140	14		T42	4		T231	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T175	6		T159	14		T221	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T6	19		T181	1		T139	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T6	22		T150	1		T48	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T111	1		T149	1		T83	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T11	12		T162	5		T282	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T8	4		T95	5		T298	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16177	1			T1	20		T3	11		T5	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T40	4		T164	5		T160	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T48	10		T188	11		T234	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T144	6		T236	2		T229	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T136	13		T54	7		T235	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T136	10		T83	2		T85	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T15	17		T140	12		T142	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T143	7		T221	17		T235	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	998	1			T45	10		T151	12		T205	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T164	1		T36	1		T248	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T164	16		T228	10		T230	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T15	7		T140	7		T42	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T8	2		T188	2		T44	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T41	2		T53	9		T225	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T40	2		T142	8		T106	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T140	11		T42	2		T231	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T159	14		T44	2		T245	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T6	20		T40	2		T241	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T6	18		T150	12		T48	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T149	12		T83	10		T252	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T162	2		T282	9		T277	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T95	7		T298	3		T278	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T8	3		T9	1		T48	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T40	1		T164	8		T160	9

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T150	1		T160	3		T162	5
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T8	4		T226	6		T19	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T89	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T275	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T7	1		T11	6		T234	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T14	2		T40	4		T164	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T9	1		T48	11		T182	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T136	11		T144	8		T85	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T15	10		T140	10		T142	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T219	1		T183	18		T143	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T45	13		T111	1		T159	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T7	1		T14	1		T182	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1609	1			T2	1		T12	24		T26	22
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T140	4		T164	1		T162	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T8	3		T139	10		T152	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T15	8		T41	5		T53	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T46	19		T218	11		T142	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T140	14		T42	4		T231	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T13	1		T40	5		T175	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T139	17		T182	1		T141	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T6	22		T11	12		T48	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	296	1			T6	19		T111	1		T181	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16090	1			T1	20		T3	11		T5	17
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T150	12		T160	12		T162	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T226	19		T19	1		T298	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T234	5		T153	9		T235	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T40	1		T164	8		T160	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T48	10		T136	13		T188	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T136	10		T144	6		T85	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T15	17		T140	12		T142	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T143	7		T83	2		T221	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T45	10		T159	5		T144	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T36	1		T248	11		T242	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	921	1			T151	12		T164	16		T205	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T140	7		T164	1		T224	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T8	2		T228	10		T44	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T15	7		T41	2		T53	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T142	8		T188	2		T106	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T140	11		T42	2		T231	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T40	2		T245	18		T99	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T241	13		T167	10		T91	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T6	18		T48	11		T159	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T6	20		T40	2		T149	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T8	3		T9	1		T48	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T7	1		T11	1		T48	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T14	2		T198	1		T144	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T9	1		T182	1		T136	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T136	11		T83	3		T85	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T15	18		T111	1		T140	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T14	1		T219	1		T183	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1345	1			T2	1		T12	3		T26	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T7	1		T182	1		T164	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T164	17		T198	1		T228	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T15	8		T140	8		T162	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T8	4		T139	1		T152	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T41	4		T53	10		T225	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T13	1		T46	1		T40	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T140	12		T42	4		T231	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T175	1		T159	15		T221	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T6	21		T181	1		T139	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T6	19		T150	13		T48	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T111	1		T149	13		T83	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T11	1		T162	3		T282	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T8	3		T95	8		T298	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16265	1			T1	20		T3	11		T5	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T40	4		T164	9		T160	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T11	5		T48	10		T154	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T144	7		T184	12		T167	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T217	12		T54	9		T35	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T136	10		T85	11		T165	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T15	9		T140	9		T43	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T183	16		T143	2		T260	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1364	1			T12	21		T26	20		T45	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T248	10		T242	9		T245	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T164	11		T228	12		T217	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T15	7		T140	3		T162	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T8	1		T139	9		T44	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T41	3		T225	13		T16	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T46	18		T40	2		T218	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T140	13		T42	2		T231	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T175	5		T159	13		T221	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T6	18		T139	16		T40	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T6	21		T48	11		T143	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T226	4		T242	17		T245	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T11	11		T162	4		T277	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T8	1		T95	4		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T299	11		T180	7		T222	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T40	1		T164	4		T160	11

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T150	13		T160	13		T162	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T8	3		T226	21		T19	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T89	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T275	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T7	1		T11	1		T234	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T14	2		T40	4		T164	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T9	1		T48	11		T182	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T136	11		T144	7		T85	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T15	18		T140	13		T142	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T219	1		T183	2		T143	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T45	11		T111	1		T159	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T7	1		T14	1		T182	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1250	1			T2	1		T12	3		T26	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T140	8		T164	2		T162	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T8	4		T139	1		T152	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T15	8		T41	4		T53	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T46	1		T218	1		T142	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T140	12		T42	4		T231	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T13	1		T40	5		T175	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T139	1		T182	1		T141	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T6	19		T11	1		T48	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T6	21		T111	1		T181	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16213	1			T1	20		T3	11		T5	17
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T160	2		T162	4		T244	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T8	1		T226	4		T293	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T11	5		T154	1		T99	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T40	1		T164	4		T160	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T48	10		T276	2		T201	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T136	10		T144	7		T85	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T15	9		T140	9		T228	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T183	16		T143	2		T260	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T45	12		T159	11		T144	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T248	10		T242	9		T245	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1280	1			T12	21		T26	20		T47	35
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T140	3		T162	6		T107	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T8	1		T139	9		T228	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T15	7		T41	3		T225	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T46	18		T218	10		T106	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T140	13		T42	2		T231	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T40	2		T175	5		T33	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T139	16		T100	16		T167	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T6	21		T11	11		T48	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T6	18		T40	2		T242	17

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20778

1

T1

20

T2

1

T3

11

auto[1]

auto[0]

4055

1

T6

39

T8

2

T11

16