Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24833

1

T1

20

T2

1

T3

11

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21746

1

T1

20

T2

1

T3

11

auto[ADC_CTRL_FILTER_COND_OUT]

3087

1

T6

39

T9

1

T11

18

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18929

1

T1

20

T3

11

T5

17

auto[1]

5904

1

T2

1

T6

39

T8

5

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21167

1

T1

20

T2

1

T3

11

auto[1]

3666

1

T6

38

T8

5

T9

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	380	1			T9	1		T49	4		T50	2
values[0]	31	1			T186	4		T293	13		T300	3
values[1]	733	1			T7	1		T13	1		T48	23
values[2]	2887	1			T2	1		T6	40		T12	24
values[3]	703	1			T8	5		T9	1		T46	19
values[4]	551	1			T183	3		T142	14		T225	9
values[5]	616	1			T7	1		T14	1		T15	15
values[6]	649	1			T15	27		T150	13		T40	5
values[7]	644	1			T8	4		T11	12		T182	1
values[8]	745	1			T6	39		T40	5		T141	1
values[9]	1022	1			T11	6		T14	2		T111	1
minimum	15872	1			T1	20		T3	11		T5	17

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	839	1			T7	1		T13	1		T48	23
values[1]	3088	1			T2	1		T6	40		T12	24
values[2]	581	1			T8	5		T9	1		T219	1
values[3]	577	1			T15	15		T40	7		T141	1
values[4]	577	1			T7	1		T14	1		T15	27
values[5]	560	1			T8	4		T111	1		T150	13
values[6]	749	1			T6	39		T11	12		T40	5
values[7]	742	1			T139	10		T40	5		T164	28
values[8]	731	1			T11	6		T14	1		T111	1
values[9]	163	1			T14	1		T41	7		T106	26
minimum	16226	1			T1	20		T3	11		T5	17

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20778

1

T1

20

T2

1

T3

11

auto[1]

4055

1

T6

39

T8

2

T11

16

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T7	1		T182	1		T136	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T13	1		T48	12		T140	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1750	1			T2	1		T6	22		T12	24
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T46	19		T182	1		T53	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T8	3		T219	1		T154	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T9	1		T183	3		T198	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T15	8		T40	5		T142	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T141	1		T225	4		T234	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T7	1		T14	1		T15	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T218	11		T183	15		T198	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T8	4		T182	1		T164	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T111	1		T150	1		T159	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T141	1		T160	12		T189	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T6	19		T11	12		T40	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T139	10		T40	3		T164	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T89	1		T220	2		T42	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T111	1		T136	1		T162	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T11	6		T14	1		T149	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T106	14		T248	3		T185	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T14	1		T41	5		T254	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16090	1			T1	20		T3	11		T5	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T145	1		T301	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T136	10		T226	9		T245	18
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T48	11		T140	12		T164	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1028	1			T6	18		T45	10		T140	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T53	9		T236	2		T235	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T8	2		T229	12		T155	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T188	11		T224	7		T302	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T15	7		T40	2		T142	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T225	5		T234	5		T288	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T15	17		T48	10		T151	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T160	12		T144	6		T83	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T164	8		T144	5		T83	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T150	12		T159	5		T42	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T160	9		T242	2		T259	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T6	20		T40	1		T143	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T40	2		T164	16		T153	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T42	2		T253	13		T245	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T136	13		T162	2		T36	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T149	12		T144	9		T221	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T106	12		T248	13		T298	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T41	2		T254	15		T303	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T8	3		T9	1		T48	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T301	11		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	354	1			T9	1		T49	4		T50	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T189	1		T245	11		T238	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T293	3		T300	2		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T186	1		T258	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T7	1		T136	11		T152	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T13	1		T48	12		T182	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1663	1			T2	1		T6	22		T12	24
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T140	10		T164	1		T53	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T8	3		T140	14		T219	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T9	1		T46	19		T198	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T142	1		T107	14		T54	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T183	3		T225	4		T188	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T7	1		T14	1		T15	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T111	1		T141	1		T218	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T15	10		T164	5		T175	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T150	1		T40	4		T183	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T8	4		T182	1		T160	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T11	12		T225	14		T221	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T40	3		T141	1		T189	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T6	19		T89	1		T220	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T111	1		T139	10		T164	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	322	1			T11	6		T14	2		T149	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15749	1			T1	20		T3	11		T5	17
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T245	11		T238	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T293	10		T300	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T186	3		T258	10		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T136	10		T44	4		T245	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T48	11		T142	8		T85	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1000	1			T6	18		T45	10		T140	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T140	12		T164	1		T53	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T8	2		T140	11		T43	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T224	7		T167	12		T247	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T142	13		T54	7		T16	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T225	5		T188	11		T234	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T15	7		T48	10		T40	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T160	12		T106	10		T259	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T15	17		T164	8		T83	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T150	12		T40	1		T159	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T160	9		T144	5		T242	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T225	14		T230	4		T248	30
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T40	2		T165	1		T297	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T6	20		T42	2		T245	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T164	16		T136	13		T162	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T149	12		T41	2		T144	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T8	3		T9	1		T48	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T7	1		T182	1		T136	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T13	1		T48	12		T140	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1377	1			T2	1		T6	19		T12	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T46	1		T182	1		T53	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T8	4		T219	1		T154	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T9	1		T183	1		T198	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T15	8		T40	5		T142	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T141	1		T225	6		T234	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T7	1		T14	1		T15	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T218	1		T183	1		T198	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T8	3		T182	1		T164	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T111	1		T150	13		T159	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T141	1		T160	10		T189	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T6	21		T11	1		T40	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T139	1		T40	3		T164	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T89	1		T220	2		T42	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T111	1		T136	14		T162	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T11	1		T14	1		T149	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T106	13		T248	14		T185	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T14	1		T41	4		T254	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16213	1			T1	20		T3	11		T5	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T145	1		T301	12		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T136	10		T162	6		T244	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T48	11		T140	9		T85	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1401	1			T6	21		T12	21		T26	20
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T46	18		T260	17		T33	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T8	1		T184	10		T155	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T183	2		T267	8		T304	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T15	7		T40	2		T43	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T225	3		T288	4		T192	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T15	9		T48	10		T139	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T218	10		T183	14		T160	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T8	1		T164	4		T231	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T159	11		T42	2		T248	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T160	11		T242	17		T259	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T6	18		T11	11		T40	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T139	9		T40	2		T164	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T42	2		T245	7		T207	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T162	4		T35	11		T276	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T11	5		T144	9		T221	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T106	13		T248	2		T185	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T41	3		T254	17		T303	12

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	342	1			T9	1		T49	4		T50	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T189	1		T245	12		T238	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T293	11		T300	2		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T186	4		T258	11		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T7	1		T136	11		T152	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T13	1		T48	12		T182	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1342	1			T2	1		T6	19		T12	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T140	13		T164	2		T53	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T8	4		T140	12		T219	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T9	1		T46	1		T198	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T142	14		T107	1		T54	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T183	1		T225	6		T188	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T7	1		T14	1		T15	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T111	1		T141	1		T218	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T15	18		T164	9		T175	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T150	13		T40	4		T183	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T8	3		T182	1		T160	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T11	1		T225	15		T221	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T40	3		T141	1		T189	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T6	21		T89	1		T220	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T111	1		T139	1		T164	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T11	1		T14	2		T149	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15872	1			T1	20		T3	11		T5	17
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T264	12		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T245	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T293	2		T300	1		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T136	10		T162	6		T244	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T48	11		T85	11		T265	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1321	1			T6	21		T12	21		T26	20
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T140	9		T260	17		T33	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T8	1		T140	13		T43	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T46	18		T239	14		T167	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T107	13		T54	9		T155	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T183	2		T225	3		T184	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T15	7		T48	10		T139	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T218	10		T160	2		T106	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T15	9		T164	4		T175	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T40	1		T183	14		T159	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T8	1		T160	11		T242	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T11	11		T225	13		T221	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T40	2		T217	13		T165	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T6	18		T42	2		T245	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T139	9		T164	11		T162	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T11	5		T41	3		T144	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20778

1

T1

20

T2

1

T3

11

auto[1]

auto[0]

4055

1

T6

39

T8

2

T11

16