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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.72 99.07 96.67 100.00 100.00 98.83 98.33 91.12


Total test records in report: 909
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T65 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.1614542598 Mar 19 12:27:02 PM PDT 24 Mar 19 12:27:07 PM PDT 24 524310301 ps
T112 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.2381364280 Mar 19 12:26:58 PM PDT 24 Mar 19 12:27:01 PM PDT 24 888485005 ps
T113 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.2296563499 Mar 19 12:27:08 PM PDT 24 Mar 19 12:27:15 PM PDT 24 740315035 ps
T69 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.1291383305 Mar 19 12:26:50 PM PDT 24 Mar 19 12:26:53 PM PDT 24 888961565 ps
T114 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.3276406543 Mar 19 12:26:49 PM PDT 24 Mar 19 12:26:55 PM PDT 24 1269209228 ps
T794 /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.3680438614 Mar 19 12:27:22 PM PDT 24 Mar 19 12:27:24 PM PDT 24 493720667 ps
T795 /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.334048678 Mar 19 12:27:20 PM PDT 24 Mar 19 12:27:21 PM PDT 24 556903573 ps
T74 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.3872640714 Mar 19 12:27:21 PM PDT 24 Mar 19 12:27:25 PM PDT 24 542996769 ps
T73 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.3883913089 Mar 19 12:26:50 PM PDT 24 Mar 19 12:26:55 PM PDT 24 645184548 ps
T796 /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.465178739 Mar 19 12:27:17 PM PDT 24 Mar 19 12:27:18 PM PDT 24 304796974 ps
T134 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.642874938 Mar 19 12:27:07 PM PDT 24 Mar 19 12:27:15 PM PDT 24 1088867623 ps
T63 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.3112231553 Mar 19 12:27:09 PM PDT 24 Mar 19 12:27:17 PM PDT 24 8614943792 ps
T102 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.3183141785 Mar 19 12:26:50 PM PDT 24 Mar 19 12:26:51 PM PDT 24 437649209 ps
T57 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.3841575369 Mar 19 12:27:17 PM PDT 24 Mar 19 12:30:56 PM PDT 24 52954449759 ps
T70 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.3285756540 Mar 19 12:27:11 PM PDT 24 Mar 19 12:27:15 PM PDT 24 470110203 ps
T135 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.100021502 Mar 19 12:27:10 PM PDT 24 Mar 19 12:27:13 PM PDT 24 530661475 ps
T58 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.373895528 Mar 19 12:27:01 PM PDT 24 Mar 19 12:28:58 PM PDT 24 27044123435 ps
T797 /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.771035955 Mar 19 12:27:17 PM PDT 24 Mar 19 12:27:18 PM PDT 24 443184671 ps
T71 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.3841133982 Mar 19 12:27:02 PM PDT 24 Mar 19 12:27:06 PM PDT 24 733489281 ps
T75 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.3392656982 Mar 19 12:26:52 PM PDT 24 Mar 19 12:26:55 PM PDT 24 694084803 ps
T64 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.839395815 Mar 19 12:26:56 PM PDT 24 Mar 19 12:27:05 PM PDT 24 8862994071 ps
T798 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.344344410 Mar 19 12:27:20 PM PDT 24 Mar 19 12:27:24 PM PDT 24 593860473 ps
T799 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.1572702311 Mar 19 12:26:54 PM PDT 24 Mar 19 12:26:56 PM PDT 24 564124771 ps
T59 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.3916804116 Mar 19 12:26:50 PM PDT 24 Mar 19 12:27:46 PM PDT 24 25147474611 ps
T77 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.2899007150 Mar 19 12:27:13 PM PDT 24 Mar 19 12:27:36 PM PDT 24 8246474318 ps
T800 /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.1586662671 Mar 19 12:27:20 PM PDT 24 Mar 19 12:27:23 PM PDT 24 506790453 ps
T127 /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.2711382203 Mar 19 12:26:48 PM PDT 24 Mar 19 12:26:53 PM PDT 24 4863436760 ps
T801 /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.3692718815 Mar 19 12:27:08 PM PDT 24 Mar 19 12:27:13 PM PDT 24 419282370 ps
T802 /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.2177790895 Mar 19 12:27:24 PM PDT 24 Mar 19 12:27:27 PM PDT 24 280695388 ps
T803 /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.267578951 Mar 19 12:26:53 PM PDT 24 Mar 19 12:26:54 PM PDT 24 377099316 ps
T804 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.1519536757 Mar 19 12:26:56 PM PDT 24 Mar 19 12:26:58 PM PDT 24 819127802 ps
T128 /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.2116943464 Mar 19 12:26:52 PM PDT 24 Mar 19 12:27:02 PM PDT 24 2564749716 ps
T338 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.144681125 Mar 19 12:26:49 PM PDT 24 Mar 19 12:27:01 PM PDT 24 4598666224 ps
T115 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.1008569871 Mar 19 12:27:20 PM PDT 24 Mar 19 12:27:24 PM PDT 24 399017863 ps
T805 /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.2682082829 Mar 19 12:27:05 PM PDT 24 Mar 19 12:27:07 PM PDT 24 442500928 ps
T116 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.2430564966 Mar 19 12:27:25 PM PDT 24 Mar 19 12:27:27 PM PDT 24 304514054 ps
T806 /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.3700511969 Mar 19 12:26:46 PM PDT 24 Mar 19 12:26:49 PM PDT 24 441593177 ps
T78 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.1037549723 Mar 19 12:27:13 PM PDT 24 Mar 19 12:27:26 PM PDT 24 4478403785 ps
T807 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.2203653739 Mar 19 12:26:49 PM PDT 24 Mar 19 12:26:51 PM PDT 24 388910393 ps
T808 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.3310029911 Mar 19 12:26:50 PM PDT 24 Mar 19 12:26:53 PM PDT 24 628424245 ps
T809 /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.3908762852 Mar 19 12:27:09 PM PDT 24 Mar 19 12:27:13 PM PDT 24 441547193 ps
T810 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.1717926003 Mar 19 12:27:02 PM PDT 24 Mar 19 12:27:05 PM PDT 24 441037944 ps
T129 /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.2953057874 Mar 19 12:27:19 PM PDT 24 Mar 19 12:27:31 PM PDT 24 4507101778 ps
T811 /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.3451441242 Mar 19 12:27:04 PM PDT 24 Mar 19 12:27:13 PM PDT 24 520393836 ps
T117 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.1192138955 Mar 19 12:26:51 PM PDT 24 Mar 19 12:26:54 PM PDT 24 455618290 ps
T118 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.2074270459 Mar 19 12:27:16 PM PDT 24 Mar 19 12:27:18 PM PDT 24 560377160 ps
T812 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.3346455389 Mar 19 12:27:02 PM PDT 24 Mar 19 12:27:06 PM PDT 24 548430860 ps
T813 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.953711433 Mar 19 12:27:01 PM PDT 24 Mar 19 12:27:17 PM PDT 24 8025745269 ps
T119 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.4065718366 Mar 19 12:26:44 PM PDT 24 Mar 19 12:26:45 PM PDT 24 407164166 ps
T814 /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.621242623 Mar 19 12:27:15 PM PDT 24 Mar 19 12:27:16 PM PDT 24 481721384 ps
T130 /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.589603716 Mar 19 12:27:17 PM PDT 24 Mar 19 12:27:23 PM PDT 24 3194204772 ps
T131 /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.4083461481 Mar 19 12:27:35 PM PDT 24 Mar 19 12:27:38 PM PDT 24 2334420146 ps
T76 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.3068153087 Mar 19 12:26:59 PM PDT 24 Mar 19 12:27:02 PM PDT 24 1012368046 ps
T132 /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.2484847092 Mar 19 12:27:09 PM PDT 24 Mar 19 12:27:14 PM PDT 24 2234469090 ps
T815 /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.2533715945 Mar 19 12:26:57 PM PDT 24 Mar 19 12:26:59 PM PDT 24 402381402 ps
T816 /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.3413497230 Mar 19 12:26:59 PM PDT 24 Mar 19 12:27:02 PM PDT 24 508815109 ps
T817 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.2184370370 Mar 19 12:27:22 PM PDT 24 Mar 19 12:27:24 PM PDT 24 500865313 ps
T818 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.809808712 Mar 19 12:27:39 PM PDT 24 Mar 19 12:27:40 PM PDT 24 462506944 ps
T79 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.598397188 Mar 19 12:27:04 PM PDT 24 Mar 19 12:27:20 PM PDT 24 4189987427 ps
T120 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.3886444982 Mar 19 12:27:08 PM PDT 24 Mar 19 12:27:13 PM PDT 24 343989487 ps
T819 /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.616409639 Mar 19 12:27:17 PM PDT 24 Mar 19 12:27:18 PM PDT 24 2948919562 ps
T820 /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.21122498 Mar 19 12:27:11 PM PDT 24 Mar 19 12:27:16 PM PDT 24 2756830460 ps
T821 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.1791996787 Mar 19 12:27:04 PM PDT 24 Mar 19 12:27:06 PM PDT 24 4989191513 ps
T822 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.2856837325 Mar 19 12:27:14 PM PDT 24 Mar 19 12:27:22 PM PDT 24 4441389790 ps
T823 /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.107115110 Mar 19 12:27:23 PM PDT 24 Mar 19 12:27:26 PM PDT 24 395356797 ps
T824 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.3889689530 Mar 19 12:26:52 PM PDT 24 Mar 19 12:26:56 PM PDT 24 393371896 ps
T825 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.1199421848 Mar 19 12:26:48 PM PDT 24 Mar 19 12:26:50 PM PDT 24 419192643 ps
T826 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.648572424 Mar 19 12:27:07 PM PDT 24 Mar 19 12:27:15 PM PDT 24 609781182 ps
T827 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.4158050436 Mar 19 12:27:04 PM PDT 24 Mar 19 12:27:08 PM PDT 24 496137660 ps
T828 /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.707636325 Mar 19 12:27:24 PM PDT 24 Mar 19 12:27:37 PM PDT 24 2668409058 ps
T829 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.2007992226 Mar 19 12:26:52 PM PDT 24 Mar 19 12:26:55 PM PDT 24 510277960 ps
T830 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.3099464226 Mar 19 12:27:02 PM PDT 24 Mar 19 12:27:05 PM PDT 24 437341955 ps
T831 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.3049729356 Mar 19 12:27:04 PM PDT 24 Mar 19 12:27:12 PM PDT 24 495197366 ps
T832 /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.3791941695 Mar 19 12:27:12 PM PDT 24 Mar 19 12:27:15 PM PDT 24 418957505 ps
T833 /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.965385382 Mar 19 12:27:00 PM PDT 24 Mar 19 12:27:12 PM PDT 24 2197177441 ps
T834 /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.1020678283 Mar 19 12:26:53 PM PDT 24 Mar 19 12:26:54 PM PDT 24 562537974 ps
T121 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.131962851 Mar 19 12:27:05 PM PDT 24 Mar 19 12:27:11 PM PDT 24 492591885 ps
T835 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.4070783475 Mar 19 12:27:12 PM PDT 24 Mar 19 12:27:16 PM PDT 24 554577233 ps
T836 /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.3632944122 Mar 19 12:26:55 PM PDT 24 Mar 19 12:26:56 PM PDT 24 399970625 ps
T837 /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.428677243 Mar 19 12:27:14 PM PDT 24 Mar 19 12:27:16 PM PDT 24 325308256 ps
T838 /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.781364954 Mar 19 12:27:14 PM PDT 24 Mar 19 12:27:21 PM PDT 24 5305461364 ps
T839 /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.3291344403 Mar 19 12:27:10 PM PDT 24 Mar 19 12:27:14 PM PDT 24 319158225 ps
T840 /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.2821833490 Mar 19 12:27:20 PM PDT 24 Mar 19 12:27:24 PM PDT 24 506512012 ps
T841 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.3779937702 Mar 19 12:27:13 PM PDT 24 Mar 19 12:27:39 PM PDT 24 52494592148 ps
T842 /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.139893459 Mar 19 12:27:05 PM PDT 24 Mar 19 12:27:11 PM PDT 24 1856614370 ps
T843 /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.3931130120 Mar 19 12:27:10 PM PDT 24 Mar 19 12:27:13 PM PDT 24 357218359 ps
T844 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.2179359075 Mar 19 12:26:52 PM PDT 24 Mar 19 12:26:54 PM PDT 24 520415346 ps
T122 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.1139579108 Mar 19 12:26:51 PM PDT 24 Mar 19 12:26:53 PM PDT 24 719084205 ps
T845 /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.3229295934 Mar 19 12:27:07 PM PDT 24 Mar 19 12:27:13 PM PDT 24 436326521 ps
T339 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.3260600027 Mar 19 12:26:49 PM PDT 24 Mar 19 12:27:13 PM PDT 24 8419731238 ps
T846 /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.1836597863 Mar 19 12:27:12 PM PDT 24 Mar 19 12:27:15 PM PDT 24 466364404 ps
T847 /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.611389874 Mar 19 12:26:50 PM PDT 24 Mar 19 12:26:52 PM PDT 24 324884970 ps
T848 /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.758067548 Mar 19 12:27:19 PM PDT 24 Mar 19 12:27:21 PM PDT 24 301867058 ps
T849 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.2844978130 Mar 19 12:27:00 PM PDT 24 Mar 19 12:27:03 PM PDT 24 475422240 ps
T850 /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.2020137392 Mar 19 12:27:21 PM PDT 24 Mar 19 12:27:23 PM PDT 24 333713292 ps
T851 /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.949592572 Mar 19 12:27:26 PM PDT 24 Mar 19 12:27:28 PM PDT 24 3580795998 ps
T852 /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.1544823438 Mar 19 12:27:12 PM PDT 24 Mar 19 12:27:15 PM PDT 24 534942720 ps
T340 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.2740515862 Mar 19 12:26:59 PM PDT 24 Mar 19 12:27:03 PM PDT 24 4928587735 ps
T853 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.587142868 Mar 19 12:27:12 PM PDT 24 Mar 19 12:27:20 PM PDT 24 9108374148 ps
T854 /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.374747167 Mar 19 12:26:52 PM PDT 24 Mar 19 12:26:54 PM PDT 24 418696481 ps
T855 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.1926614706 Mar 19 12:27:13 PM PDT 24 Mar 19 12:27:17 PM PDT 24 825119294 ps
T856 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.2855536180 Mar 19 12:26:49 PM PDT 24 Mar 19 12:26:50 PM PDT 24 431998876 ps
T857 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.2558240410 Mar 19 12:27:17 PM PDT 24 Mar 19 12:27:18 PM PDT 24 553341188 ps
T858 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.1243714873 Mar 19 12:27:14 PM PDT 24 Mar 19 12:27:34 PM PDT 24 7615209249 ps
T859 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.1252214802 Mar 19 12:26:49 PM PDT 24 Mar 19 12:26:51 PM PDT 24 433213363 ps
T860 /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.1521245294 Mar 19 12:27:12 PM PDT 24 Mar 19 12:27:15 PM PDT 24 2105661634 ps
T861 /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.921092129 Mar 19 12:26:52 PM PDT 24 Mar 19 12:26:54 PM PDT 24 459705812 ps
T862 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.102174976 Mar 19 12:27:07 PM PDT 24 Mar 19 12:27:14 PM PDT 24 640817415 ps
T863 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.1486714388 Mar 19 12:26:48 PM PDT 24 Mar 19 12:27:00 PM PDT 24 8471879158 ps
T864 /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.3999486324 Mar 19 12:27:00 PM PDT 24 Mar 19 12:27:02 PM PDT 24 445107625 ps
T865 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.4192657784 Mar 19 12:27:00 PM PDT 24 Mar 19 12:27:02 PM PDT 24 472387556 ps
T123 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.1175941942 Mar 19 12:26:51 PM PDT 24 Mar 19 12:27:02 PM PDT 24 20526246652 ps
T866 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.3080995715 Mar 19 12:27:19 PM PDT 24 Mar 19 12:27:21 PM PDT 24 468581863 ps
T867 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.2610307046 Mar 19 12:27:04 PM PDT 24 Mar 19 12:27:08 PM PDT 24 370389477 ps
T868 /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.155607092 Mar 19 12:27:18 PM PDT 24 Mar 19 12:27:21 PM PDT 24 306325485 ps
T869 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.827994015 Mar 19 12:27:22 PM PDT 24 Mar 19 12:27:24 PM PDT 24 448875984 ps
T870 /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.695584637 Mar 19 12:27:09 PM PDT 24 Mar 19 12:27:13 PM PDT 24 481116107 ps
T871 /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.3945291834 Mar 19 12:26:59 PM PDT 24 Mar 19 12:27:02 PM PDT 24 472889743 ps
T872 /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.2924964166 Mar 19 12:27:01 PM PDT 24 Mar 19 12:27:05 PM PDT 24 363300155 ps
T873 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.508180257 Mar 19 12:27:02 PM PDT 24 Mar 19 12:27:06 PM PDT 24 771481804 ps
T874 /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.3702605219 Mar 19 12:26:54 PM PDT 24 Mar 19 12:26:59 PM PDT 24 4402375781 ps
T875 /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.3096934625 Mar 19 12:27:15 PM PDT 24 Mar 19 12:27:16 PM PDT 24 543048039 ps
T876 /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.2975101809 Mar 19 12:26:53 PM PDT 24 Mar 19 12:27:02 PM PDT 24 3887879660 ps
T124 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.4218892247 Mar 19 12:26:55 PM PDT 24 Mar 19 12:26:58 PM PDT 24 806456288 ps
T877 /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.3215819644 Mar 19 12:27:06 PM PDT 24 Mar 19 12:27:08 PM PDT 24 467828655 ps
T878 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.2337055471 Mar 19 12:27:04 PM PDT 24 Mar 19 12:27:23 PM PDT 24 8222602595 ps
T879 /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.2223271361 Mar 19 12:27:11 PM PDT 24 Mar 19 12:27:14 PM PDT 24 281653471 ps
T880 /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.2869879722 Mar 19 12:26:47 PM PDT 24 Mar 19 12:26:52 PM PDT 24 2589796819 ps
T881 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.1455242851 Mar 19 12:26:42 PM PDT 24 Mar 19 12:26:45 PM PDT 24 426643321 ps
T125 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.2971337339 Mar 19 12:26:48 PM PDT 24 Mar 19 12:26:51 PM PDT 24 504251904 ps
T882 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.2595109994 Mar 19 12:26:54 PM PDT 24 Mar 19 12:26:56 PM PDT 24 566698121 ps
T883 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.318714797 Mar 19 12:27:01 PM PDT 24 Mar 19 12:27:11 PM PDT 24 8416493970 ps
T884 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.1464197478 Mar 19 12:27:12 PM PDT 24 Mar 19 12:27:15 PM PDT 24 588934647 ps
T885 /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.2639814919 Mar 19 12:27:10 PM PDT 24 Mar 19 12:27:14 PM PDT 24 1971459489 ps
T886 /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.597525269 Mar 19 12:27:08 PM PDT 24 Mar 19 12:27:13 PM PDT 24 390372311 ps
T887 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.1286100554 Mar 19 12:26:36 PM PDT 24 Mar 19 12:26:39 PM PDT 24 354226178 ps
T888 /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.823844288 Mar 19 12:27:11 PM PDT 24 Mar 19 12:27:19 PM PDT 24 2940737040 ps
T889 /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.2703714774 Mar 19 12:27:16 PM PDT 24 Mar 19 12:27:18 PM PDT 24 432336951 ps
T890 /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.3272840271 Mar 19 12:26:57 PM PDT 24 Mar 19 12:26:58 PM PDT 24 339401143 ps
T891 /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.3259852289 Mar 19 12:27:13 PM PDT 24 Mar 19 12:27:15 PM PDT 24 431721727 ps
T892 /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.239072690 Mar 19 12:27:25 PM PDT 24 Mar 19 12:27:27 PM PDT 24 546889347 ps
T893 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.2716783000 Mar 19 12:27:01 PM PDT 24 Mar 19 12:27:07 PM PDT 24 480793369 ps
T894 /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.225823732 Mar 19 12:27:12 PM PDT 24 Mar 19 12:27:13 PM PDT 24 456643115 ps
T895 /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.2353439304 Mar 19 12:27:18 PM PDT 24 Mar 19 12:27:21 PM PDT 24 448937936 ps
T896 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.3893115989 Mar 19 12:27:05 PM PDT 24 Mar 19 12:27:14 PM PDT 24 8653627826 ps
T897 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.3208919948 Mar 19 12:26:37 PM PDT 24 Mar 19 12:26:48 PM PDT 24 4025213073 ps
T898 /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.949942306 Mar 19 12:27:10 PM PDT 24 Mar 19 12:27:14 PM PDT 24 392808810 ps
T899 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.3618094258 Mar 19 12:27:35 PM PDT 24 Mar 19 12:27:38 PM PDT 24 492247257 ps
T900 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.2946218372 Mar 19 12:26:58 PM PDT 24 Mar 19 12:27:01 PM PDT 24 634062988 ps
T126 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.4168049652 Mar 19 12:26:48 PM PDT 24 Mar 19 12:26:51 PM PDT 24 1329000746 ps
T901 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.2473083138 Mar 19 12:27:02 PM PDT 24 Mar 19 12:27:05 PM PDT 24 547198510 ps
T902 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.1882324316 Mar 19 12:26:54 PM PDT 24 Mar 19 12:26:56 PM PDT 24 309290297 ps
T903 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.3991337237 Mar 19 12:27:18 PM PDT 24 Mar 19 12:27:21 PM PDT 24 401136909 ps
T904 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.879260826 Mar 19 12:27:21 PM PDT 24 Mar 19 12:27:24 PM PDT 24 350116178 ps
T905 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.288451055 Mar 19 12:27:27 PM PDT 24 Mar 19 12:27:29 PM PDT 24 611331181 ps
T906 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.3531959416 Mar 19 12:27:12 PM PDT 24 Mar 19 12:27:15 PM PDT 24 1866010577 ps
T907 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.2972521198 Mar 19 12:26:48 PM PDT 24 Mar 19 12:26:55 PM PDT 24 7715224337 ps
T908 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.2863838274 Mar 19 12:26:58 PM PDT 24 Mar 19 12:27:03 PM PDT 24 1409915016 ps
T909 /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.2493982458 Mar 19 12:27:10 PM PDT 24 Mar 19 12:27:14 PM PDT 24 473603384 ps

Test location /workspace/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.797618587
Short name T8
Test name
Test status
Simulation time 60459063425 ps
CPU time 107.1 seconds
Started Mar 19 12:30:21 PM PDT 24
Finished Mar 19 12:32:09 PM PDT 24
Peak memory 210080 kb
Host smart-c707b9f8-f997-4853-a1bc-c0b1c472c9ad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797618587 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all_with_rand_reset.797618587
Directory /workspace/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_both.3241087811
Short name T6
Test name
Test status
Simulation time 371078905401 ps
CPU time 446.44 seconds
Started Mar 19 12:28:44 PM PDT 24
Finished Mar 19 12:36:11 PM PDT 24
Peak memory 201844 kb
Host smart-18d79a4b-63e0-4c55-9902-d4cd0a234008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241087811 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.3241087811
Directory /workspace/7.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/9.adc_ctrl_fsm_reset.497494803
Short name T49
Test name
Test status
Simulation time 114349725872 ps
CPU time 670.24 seconds
Started Mar 19 12:29:02 PM PDT 24
Finished Mar 19 12:40:12 PM PDT 24
Peak memory 202176 kb
Host smart-f31b3c7e-43eb-4ff9-ab07-b6ec0d29b338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497494803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.497494803
Directory /workspace/9.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all.2169561184
Short name T144
Test name
Test status
Simulation time 543537560889 ps
CPU time 329.8 seconds
Started Mar 19 12:30:32 PM PDT 24
Finished Mar 19 12:36:02 PM PDT 24
Peak memory 201792 kb
Host smart-87909832-a529-4951-b880-24d71c455660
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169561184 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all
.2169561184
Directory /workspace/49.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.1846114959
Short name T42
Test name
Test status
Simulation time 86827352603 ps
CPU time 171.07 seconds
Started Mar 19 12:29:26 PM PDT 24
Finished Mar 19 12:32:17 PM PDT 24
Peak memory 218336 kb
Host smart-fc3128e5-c11e-4f4b-9c41-e6739a5b4823
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846114959 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all_with_rand_reset.1846114959
Directory /workspace/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_clock_gating.497942795
Short name T164
Test name
Test status
Simulation time 524430221724 ps
CPU time 395.85 seconds
Started Mar 19 12:29:24 PM PDT 24
Finished Mar 19 12:36:00 PM PDT 24
Peak memory 201796 kb
Host smart-db4dd0a8-5d75-4f40-bfa9-e7b7df67bfce
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497942795 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gati
ng.497942795
Directory /workspace/27.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all.2582032638
Short name T48
Test name
Test status
Simulation time 353265020955 ps
CPU time 404.53 seconds
Started Mar 19 12:29:54 PM PDT 24
Finished Mar 19 12:36:39 PM PDT 24
Peak memory 201776 kb
Host smart-28fd5a15-cad4-40c0-8ea4-7b8ba52b6703
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582032638 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all
.2582032638
Directory /workspace/40.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all.1347651997
Short name T54
Test name
Test status
Simulation time 277950756844 ps
CPU time 844.13 seconds
Started Mar 19 12:29:23 PM PDT 24
Finished Mar 19 12:43:27 PM PDT 24
Peak memory 202152 kb
Host smart-d0dfad8d-7b50-4d79-8acd-c26738eb5b4f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347651997 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all
.1347651997
Directory /workspace/21.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_both.514709525
Short name T140
Test name
Test status
Simulation time 501183981994 ps
CPU time 1092.57 seconds
Started Mar 19 12:29:34 PM PDT 24
Finished Mar 19 12:47:47 PM PDT 24
Peak memory 201816 kb
Host smart-122e732c-d1f1-4bb4-b3fd-961a9162d430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514709525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.514709525
Directory /workspace/26.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.468632512
Short name T165
Test name
Test status
Simulation time 373835712744 ps
CPU time 110.78 seconds
Started Mar 19 12:30:08 PM PDT 24
Finished Mar 19 12:32:00 PM PDT 24
Peak memory 210096 kb
Host smart-265b04b7-4795-479c-9109-a52788cd24be
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468632512 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all_with_rand_reset.468632512
Directory /workspace/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled.480129104
Short name T14
Test name
Test status
Simulation time 494007097726 ps
CPU time 280.47 seconds
Started Mar 19 12:28:48 PM PDT 24
Finished Mar 19 12:33:28 PM PDT 24
Peak memory 201740 kb
Host smart-ec1c2974-efa5-483f-925c-e6de6e20cb31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480129104 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.480129104
Directory /workspace/4.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/1.adc_ctrl_clock_gating.1083354809
Short name T162
Test name
Test status
Simulation time 382627626171 ps
CPU time 409.85 seconds
Started Mar 19 12:28:47 PM PDT 24
Finished Mar 19 12:35:37 PM PDT 24
Peak memory 201804 kb
Host smart-a6a1d658-6054-4dcc-8a3b-0728a10667ad
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083354809 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gati
ng.1083354809
Directory /workspace/1.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_sec_cm.4108432198
Short name T66
Test name
Test status
Simulation time 8677917461 ps
CPU time 2.7 seconds
Started Mar 19 12:28:59 PM PDT 24
Finished Mar 19 12:29:02 PM PDT 24
Peak memory 218420 kb
Host smart-215d52e7-c4d5-4454-b6c1-f066c7c8c5f5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108432198 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.4108432198
Directory /workspace/0.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.1730219392
Short name T44
Test name
Test status
Simulation time 438449592847 ps
CPU time 59.12 seconds
Started Mar 19 12:30:07 PM PDT 24
Finished Mar 19 12:31:06 PM PDT 24
Peak memory 201900 kb
Host smart-6db4c57e-e334-40a0-ab74-f9fa4cdf4eb8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730219392 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all_with_rand_reset.1730219392
Directory /workspace/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt.3278447979
Short name T235
Test name
Test status
Simulation time 495165573423 ps
CPU time 1036.98 seconds
Started Mar 19 12:30:22 PM PDT 24
Finished Mar 19 12:47:39 PM PDT 24
Peak memory 201752 kb
Host smart-13a20fd1-3551-42e0-bb6d-e62b5e3c7a9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278447979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.3278447979
Directory /workspace/49.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt.994489069
Short name T188
Test name
Test status
Simulation time 502082671894 ps
CPU time 307.17 seconds
Started Mar 19 12:29:42 PM PDT 24
Finished Mar 19 12:34:50 PM PDT 24
Peak memory 201720 kb
Host smart-f71e727d-3798-4488-a7ad-87cb6d54ebc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994489069 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.994489069
Directory /workspace/37.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_both.254786071
Short name T222
Test name
Test status
Simulation time 517265477384 ps
CPU time 255.51 seconds
Started Mar 19 12:29:20 PM PDT 24
Finished Mar 19 12:33:36 PM PDT 24
Peak memory 201760 kb
Host smart-965e5736-b4a7-47a1-9a52-d1f011ff937c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254786071 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.254786071
Directory /workspace/15.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.373895528
Short name T58
Test name
Test status
Simulation time 27044123435 ps
CPU time 113.99 seconds
Started Mar 19 12:27:01 PM PDT 24
Finished Mar 19 12:28:58 PM PDT 24
Peak memory 201792 kb
Host smart-aa44ec2e-ea72-4de9-ab73-ad3b64eaa66c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373895528 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_b
ash.373895528
Directory /workspace/2.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.1291383305
Short name T69
Test name
Test status
Simulation time 888961565 ps
CPU time 2.64 seconds
Started Mar 19 12:26:50 PM PDT 24
Finished Mar 19 12:26:53 PM PDT 24
Peak memory 218212 kb
Host smart-c3aec698-15b8-4587-a50a-949eaab70df8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291383305 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.1291383305
Directory /workspace/14.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup_fixed.3963662950
Short name T12
Test name
Test status
Simulation time 592949712032 ps
CPU time 118.25 seconds
Started Mar 19 12:29:38 PM PDT 24
Finished Mar 19 12:31:41 PM PDT 24
Peak memory 201768 kb
Host smart-dbccd566-2629-4066-9645-5c45ee053114
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963662950 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33
.adc_ctrl_filters_wakeup_fixed.3963662950
Directory /workspace/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_both.2534523569
Short name T99
Test name
Test status
Simulation time 507284739389 ps
CPU time 326.33 seconds
Started Mar 19 12:29:35 PM PDT 24
Finished Mar 19 12:35:02 PM PDT 24
Peak memory 201832 kb
Host smart-ad76e905-52e0-4e3e-af5c-6a87e7178a2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534523569 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.2534523569
Directory /workspace/23.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all.1124037346
Short name T242
Test name
Test status
Simulation time 373414022009 ps
CPU time 876.01 seconds
Started Mar 19 12:29:35 PM PDT 24
Finished Mar 19 12:44:11 PM PDT 24
Peak memory 201084 kb
Host smart-d3721482-2233-49eb-8689-682bc0189325
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124037346 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all
.1124037346
Directory /workspace/13.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.adc_ctrl_clock_gating.1268631285
Short name T106
Test name
Test status
Simulation time 349377609851 ps
CPU time 797.54 seconds
Started Mar 19 12:29:41 PM PDT 24
Finished Mar 19 12:42:59 PM PDT 24
Peak memory 201776 kb
Host smart-6eda45d1-13dd-4b98-b497-03048276e571
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268631285 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gat
ing.1268631285
Directory /workspace/37.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup.1320967813
Short name T192
Test name
Test status
Simulation time 524868343736 ps
CPU time 565.45 seconds
Started Mar 19 12:29:12 PM PDT 24
Finished Mar 19 12:38:40 PM PDT 24
Peak memory 201728 kb
Host smart-ec68daa3-0150-4d93-a913-03368516e387
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320967813 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters
_wakeup.1320967813
Directory /workspace/17.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_both.4135423053
Short name T167
Test name
Test status
Simulation time 506443036161 ps
CPU time 98.49 seconds
Started Mar 19 12:28:52 PM PDT 24
Finished Mar 19 12:30:31 PM PDT 24
Peak memory 201364 kb
Host smart-8bac944f-b387-4031-9956-0606e69d8a26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135423053 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.4135423053
Directory /workspace/9.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.2279285673
Short name T288
Test name
Test status
Simulation time 292856459653 ps
CPU time 151.37 seconds
Started Mar 19 12:29:24 PM PDT 24
Finished Mar 19 12:31:55 PM PDT 24
Peak memory 210476 kb
Host smart-38ebc4f2-55ed-41bc-b457-b123db3ce85e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279285673 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all_with_rand_reset.2279285673
Directory /workspace/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup.2186345992
Short name T217
Test name
Test status
Simulation time 543700256658 ps
CPU time 288.39 seconds
Started Mar 19 12:29:36 PM PDT 24
Finished Mar 19 12:34:24 PM PDT 24
Peak memory 201784 kb
Host smart-21b89aeb-ed95-4829-8201-58f21e329c6a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186345992 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters
_wakeup.2186345992
Directory /workspace/21.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_both.4019610641
Short name T254
Test name
Test status
Simulation time 515223496460 ps
CPU time 573.89 seconds
Started Mar 19 12:30:00 PM PDT 24
Finished Mar 19 12:39:34 PM PDT 24
Peak memory 201756 kb
Host smart-77196627-b288-40db-b697-db44f9bf0fc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019610641 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.4019610641
Directory /workspace/37.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_both.2018715331
Short name T294
Test name
Test status
Simulation time 333225484322 ps
CPU time 797.95 seconds
Started Mar 19 12:29:37 PM PDT 24
Finished Mar 19 12:42:56 PM PDT 24
Peak memory 201760 kb
Host smart-ca13b49b-e72b-426b-8eeb-cda2db6249df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018715331 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.2018715331
Directory /workspace/24.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_both.1151778855
Short name T226
Test name
Test status
Simulation time 507210219821 ps
CPU time 1285.87 seconds
Started Mar 19 12:30:09 PM PDT 24
Finished Mar 19 12:51:35 PM PDT 24
Peak memory 201824 kb
Host smart-ced7c1f4-b803-4c7f-9fa2-57ca46ff3e17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151778855 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.1151778855
Directory /workspace/42.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.2899007150
Short name T77
Test name
Test status
Simulation time 8246474318 ps
CPU time 21.73 seconds
Started Mar 19 12:27:13 PM PDT 24
Finished Mar 19 12:27:36 PM PDT 24
Peak memory 201804 kb
Host smart-cb97115c-62f9-4181-9e4d-dc36b148fe5c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899007150 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_i
ntg_err.2899007150
Directory /workspace/13.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/14.adc_ctrl_alert_test.4293747204
Short name T4
Test name
Test status
Simulation time 315959259 ps
CPU time 1.37 seconds
Started Mar 19 12:29:24 PM PDT 24
Finished Mar 19 12:29:25 PM PDT 24
Peak memory 201512 kb
Host smart-a3477a26-9867-4f19-86c2-9a53816ddd0e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293747204 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.4293747204
Directory /workspace/14.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.adc_ctrl_clock_gating.2951422170
Short name T271
Test name
Test status
Simulation time 167872659961 ps
CPU time 123.48 seconds
Started Mar 19 12:28:59 PM PDT 24
Finished Mar 19 12:31:03 PM PDT 24
Peak memory 201788 kb
Host smart-8b957897-738e-4ea4-9430-db4a2e4cfcb5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951422170 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gati
ng.2951422170
Directory /workspace/8.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.976271952
Short name T17
Test name
Test status
Simulation time 95627712521 ps
CPU time 210.56 seconds
Started Mar 19 12:29:39 PM PDT 24
Finished Mar 19 12:33:09 PM PDT 24
Peak memory 210508 kb
Host smart-b9fee9ea-1823-40cc-b082-b88c94f1246d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976271952 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all_with_rand_reset.976271952
Directory /workspace/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup.668060144
Short name T184
Test name
Test status
Simulation time 567971851835 ps
CPU time 202.31 seconds
Started Mar 19 12:30:04 PM PDT 24
Finished Mar 19 12:33:26 PM PDT 24
Peak memory 201844 kb
Host smart-754e2297-30dc-4a1d-9bcd-6ed53f4ccb21
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668060144 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_
wakeup.668060144
Directory /workspace/38.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.4065718366
Short name T119
Test name
Test status
Simulation time 407164166 ps
CPU time 1.3 seconds
Started Mar 19 12:26:44 PM PDT 24
Finished Mar 19 12:26:45 PM PDT 24
Peak memory 201568 kb
Host smart-1252b826-f8b3-4203-be85-9a7ab796486e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065718366 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.4065718366
Directory /workspace/0.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_both.1834505234
Short name T248
Test name
Test status
Simulation time 523647545900 ps
CPU time 903.91 seconds
Started Mar 19 12:29:28 PM PDT 24
Finished Mar 19 12:44:32 PM PDT 24
Peak memory 201764 kb
Host smart-613fcc4e-a1f4-412d-b564-8a8725f7cda5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834505234 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.1834505234
Directory /workspace/14.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt.3248330211
Short name T258
Test name
Test status
Simulation time 166736146652 ps
CPU time 109.15 seconds
Started Mar 19 12:30:09 PM PDT 24
Finished Mar 19 12:31:59 PM PDT 24
Peak memory 201756 kb
Host smart-8ad93aeb-e7f0-4501-a8a9-9b8b0cac589a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248330211 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.3248330211
Directory /workspace/44.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/24.adc_ctrl_clock_gating.2130044515
Short name T263
Test name
Test status
Simulation time 340041789085 ps
CPU time 197.78 seconds
Started Mar 19 12:29:37 PM PDT 24
Finished Mar 19 12:32:55 PM PDT 24
Peak memory 201736 kb
Host smart-9273a7c9-5bba-4cac-b1cf-9460b17a514d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130044515 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gat
ing.2130044515
Directory /workspace/24.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt.2759191874
Short name T238
Test name
Test status
Simulation time 490271410884 ps
CPU time 1154.26 seconds
Started Mar 19 12:29:22 PM PDT 24
Finished Mar 19 12:48:37 PM PDT 24
Peak memory 201896 kb
Host smart-f9021581-7e80-4246-a3f2-bdd681ab6b06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759191874 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.2759191874
Directory /workspace/28.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all.214283394
Short name T207
Test name
Test status
Simulation time 481681304478 ps
CPU time 1460.78 seconds
Started Mar 19 12:30:17 PM PDT 24
Finished Mar 19 12:54:38 PM PDT 24
Peak memory 212984 kb
Host smart-3fe7f6ae-d4f7-4ce4-a71e-13d4a04eed6f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214283394 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all.
214283394
Directory /workspace/41.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.adc_ctrl_clock_gating.2583158861
Short name T318
Test name
Test status
Simulation time 502986443203 ps
CPU time 363.11 seconds
Started Mar 19 12:29:09 PM PDT 24
Finished Mar 19 12:35:13 PM PDT 24
Peak memory 201812 kb
Host smart-98bd18d9-2bd4-488c-a4b9-3b5e2eb6dd5a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583158861 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gat
ing.2583158861
Directory /workspace/21.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/47.adc_ctrl_clock_gating.2873691162
Short name T143
Test name
Test status
Simulation time 385335755927 ps
CPU time 873.15 seconds
Started Mar 19 12:30:17 PM PDT 24
Finished Mar 19 12:44:51 PM PDT 24
Peak memory 201836 kb
Host smart-fd751024-b65a-4df3-a342-38c4e9a7fc7a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873691162 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gat
ing.2873691162
Directory /workspace/47.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_both.3961205380
Short name T293
Test name
Test status
Simulation time 498188571889 ps
CPU time 563.01 seconds
Started Mar 19 12:29:07 PM PDT 24
Finished Mar 19 12:38:31 PM PDT 24
Peak memory 201808 kb
Host smart-baf2ce96-0f66-468f-9c4a-6453b19d08d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961205380 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.3961205380
Directory /workspace/12.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup.3871810545
Short name T319
Test name
Test status
Simulation time 564858504087 ps
CPU time 835.45 seconds
Started Mar 19 12:29:25 PM PDT 24
Finished Mar 19 12:43:21 PM PDT 24
Peak memory 201736 kb
Host smart-cae9f1c2-dfe5-4eb6-b424-d6266a2ea673
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871810545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters
_wakeup.3871810545
Directory /workspace/20.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled.1160060288
Short name T275
Test name
Test status
Simulation time 326985304056 ps
CPU time 382.72 seconds
Started Mar 19 12:29:03 PM PDT 24
Finished Mar 19 12:35:26 PM PDT 24
Peak memory 201880 kb
Host smart-bdf071db-d487-4fe5-9df1-cc9cb1439d81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160060288 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.1160060288
Directory /workspace/11.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_both.3348776039
Short name T276
Test name
Test status
Simulation time 163750441069 ps
CPU time 379.81 seconds
Started Mar 19 12:29:01 PM PDT 24
Finished Mar 19 12:35:21 PM PDT 24
Peak memory 201764 kb
Host smart-158af8ba-bdf5-4672-9221-70fd68905abd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348776039 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.3348776039
Directory /workspace/2.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.805164416
Short name T40
Test name
Test status
Simulation time 855749116117 ps
CPU time 281.28 seconds
Started Mar 19 12:29:12 PM PDT 24
Finished Mar 19 12:33:54 PM PDT 24
Peak memory 210180 kb
Host smart-e4947908-d963-44b8-b10c-244ac90fbe87
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805164416 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all_with_rand_reset.805164416
Directory /workspace/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.3075271946
Short name T23
Test name
Test status
Simulation time 102428369389 ps
CPU time 207.8 seconds
Started Mar 19 12:30:23 PM PDT 24
Finished Mar 19 12:33:51 PM PDT 24
Peak memory 210868 kb
Host smart-3a8dd4f0-e43a-4de1-b9f0-0cd20e0db032
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075271946 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all_with_rand_reset.3075271946
Directory /workspace/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.3284845973
Short name T330
Test name
Test status
Simulation time 35954908164 ps
CPU time 100.97 seconds
Started Mar 19 12:29:55 PM PDT 24
Finished Mar 19 12:31:36 PM PDT 24
Peak memory 218680 kb
Host smart-d2b185ea-41f6-446b-b3c4-935439b38032
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284845973 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all_with_rand_reset.3284845973
Directory /workspace/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.648572424
Short name T826
Test name
Test status
Simulation time 609781182 ps
CPU time 2.6 seconds
Started Mar 19 12:27:07 PM PDT 24
Finished Mar 19 12:27:15 PM PDT 24
Peak memory 201864 kb
Host smart-2e80513f-4029-4378-a985-b384d9caea34
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648572424 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.648572424
Directory /workspace/11.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all.942885
Short name T301
Test name
Test status
Simulation time 168776837515 ps
CPU time 404.63 seconds
Started Mar 19 12:28:51 PM PDT 24
Finished Mar 19 12:35:36 PM PDT 24
Peak memory 201812 kb
Host smart-89e4fc9c-16fd-4cf1-bd7f-3195c51c7801
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942885 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all.942885
Directory /workspace/10.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all.339203532
Short name T34
Test name
Test status
Simulation time 223748525196 ps
CPU time 793.73 seconds
Started Mar 19 12:29:27 PM PDT 24
Finished Mar 19 12:42:41 PM PDT 24
Peak memory 210344 kb
Host smart-f012438b-5fe7-47bb-a3fc-553daad11b8a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339203532 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all.
339203532
Directory /workspace/12.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all.2427328673
Short name T95
Test name
Test status
Simulation time 3623639912664 ps
CPU time 8358.57 seconds
Started Mar 19 12:29:13 PM PDT 24
Finished Mar 19 02:48:34 PM PDT 24
Peak memory 212760 kb
Host smart-4e63a741-86a1-4b05-8839-79230e8b2347
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427328673 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all
.2427328673
Directory /workspace/17.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.adc_ctrl_clock_gating.3182335529
Short name T313
Test name
Test status
Simulation time 210309656585 ps
CPU time 55.67 seconds
Started Mar 19 12:29:39 PM PDT 24
Finished Mar 19 12:30:40 PM PDT 24
Peak memory 201760 kb
Host smart-43a8371d-3181-46c9-8420-9ae9ad1bf6c8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182335529 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gat
ing.3182335529
Directory /workspace/33.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_both.241511397
Short name T321
Test name
Test status
Simulation time 331910358991 ps
CPU time 502.79 seconds
Started Mar 19 12:29:38 PM PDT 24
Finished Mar 19 12:38:01 PM PDT 24
Peak memory 201844 kb
Host smart-200a40f3-9b59-4e34-8ad1-6a4a0135d243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241511397 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.241511397
Directory /workspace/35.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_both.2931479233
Short name T247
Test name
Test status
Simulation time 512049638013 ps
CPU time 1225.35 seconds
Started Mar 19 12:29:42 PM PDT 24
Finished Mar 19 12:50:08 PM PDT 24
Peak memory 201748 kb
Host smart-e9f7d74f-3bbc-4c6f-bb8b-6e247c65ed44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931479233 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.2931479233
Directory /workspace/36.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled.4036241324
Short name T89
Test name
Test status
Simulation time 169225728075 ps
CPU time 199.59 seconds
Started Mar 19 12:30:22 PM PDT 24
Finished Mar 19 12:33:42 PM PDT 24
Peak memory 201748 kb
Host smart-3bc87617-d7c0-459c-b35c-cc827420fe63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036241324 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.4036241324
Directory /workspace/48.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt.1288262757
Short name T202
Test name
Test status
Simulation time 497240220774 ps
CPU time 279.19 seconds
Started Mar 19 12:29:15 PM PDT 24
Finished Mar 19 12:33:56 PM PDT 24
Peak memory 201664 kb
Host smart-b76550ae-f9ba-41b2-b517-bcf1aa1e6922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288262757 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.1288262757
Directory /workspace/7.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_both.1975646492
Short name T296
Test name
Test status
Simulation time 162355853097 ps
CPU time 82.01 seconds
Started Mar 19 12:29:20 PM PDT 24
Finished Mar 19 12:30:42 PM PDT 24
Peak memory 201740 kb
Host smart-2f7b43fe-c8e2-4dfb-9179-a2b62241f4b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975646492 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.1975646492
Directory /workspace/22.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all.3917660259
Short name T240
Test name
Test status
Simulation time 495896262172 ps
CPU time 637.42 seconds
Started Mar 19 12:29:27 PM PDT 24
Finished Mar 19 12:40:05 PM PDT 24
Peak memory 202092 kb
Host smart-cd059124-1254-4e83-a164-7e1e5a4cf205
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917660259 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all
.3917660259
Directory /workspace/28.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt.3309872853
Short name T315
Test name
Test status
Simulation time 491479701733 ps
CPU time 259.21 seconds
Started Mar 19 12:29:36 PM PDT 24
Finished Mar 19 12:33:55 PM PDT 24
Peak memory 201732 kb
Host smart-3c86c183-351e-4c75-9f68-a9901994408d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309872853 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.3309872853
Directory /workspace/35.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled.1421227819
Short name T152
Test name
Test status
Simulation time 499983125594 ps
CPU time 137.31 seconds
Started Mar 19 12:30:04 PM PDT 24
Finished Mar 19 12:32:21 PM PDT 24
Peak memory 201800 kb
Host smart-dd7f109d-8673-4259-a061-61fc3c0d8bf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421227819 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.1421227819
Directory /workspace/38.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_both.3455877087
Short name T256
Test name
Test status
Simulation time 520101653960 ps
CPU time 1273.84 seconds
Started Mar 19 12:30:06 PM PDT 24
Finished Mar 19 12:51:20 PM PDT 24
Peak memory 201884 kb
Host smart-0c48a1aa-f722-4075-90c7-54ac2ee1ad18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455877087 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.3455877087
Directory /workspace/44.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.2740515862
Short name T340
Test name
Test status
Simulation time 4928587735 ps
CPU time 2.31 seconds
Started Mar 19 12:26:59 PM PDT 24
Finished Mar 19 12:27:03 PM PDT 24
Peak memory 201812 kb
Host smart-4e04e25b-303e-4bfd-b354-8f00e46f7912
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740515862 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_i
ntg_err.2740515862
Directory /workspace/11.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled.1640725797
Short name T307
Test name
Test status
Simulation time 316314335538 ps
CPU time 176.71 seconds
Started Mar 19 12:28:46 PM PDT 24
Finished Mar 19 12:31:43 PM PDT 24
Peak memory 201652 kb
Host smart-9cac463d-7b5c-44f3-9c20-e59b477caa6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640725797 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.1640725797
Directory /workspace/0.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt_fixed.149038535
Short name T360
Test name
Test status
Simulation time 163938333060 ps
CPU time 65.59 seconds
Started Mar 19 12:29:18 PM PDT 24
Finished Mar 19 12:30:24 PM PDT 24
Peak memory 201740 kb
Host smart-1725c85f-fa54-4015-97f7-1c5bf472d6e0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=149038535 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrup
t_fixed.149038535
Directory /workspace/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all.3755795780
Short name T716
Test name
Test status
Simulation time 275770159743 ps
CPU time 451.79 seconds
Started Mar 19 12:29:16 PM PDT 24
Finished Mar 19 12:36:49 PM PDT 24
Peak memory 212144 kb
Host smart-ef80cb5e-f7e5-4d0c-881b-42e1882b548e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755795780 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all
.3755795780
Directory /workspace/22.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_both.1744292861
Short name T195
Test name
Test status
Simulation time 363066460284 ps
CPU time 233.83 seconds
Started Mar 19 12:29:42 PM PDT 24
Finished Mar 19 12:33:36 PM PDT 24
Peak memory 201900 kb
Host smart-1c73a99b-fe1b-431a-b1af-bdde41634284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744292861 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.1744292861
Directory /workspace/27.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all.124061265
Short name T53
Test name
Test status
Simulation time 273998692286 ps
CPU time 540.82 seconds
Started Mar 19 12:28:32 PM PDT 24
Finished Mar 19 12:37:33 PM PDT 24
Peak memory 218408 kb
Host smart-a6f74275-ebdb-4029-8e41-5ba0cc2aa9ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124061265 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.124061265
Directory /workspace/0.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.1462694062
Short name T341
Test name
Test status
Simulation time 362483124373 ps
CPU time 417.98 seconds
Started Mar 19 12:28:49 PM PDT 24
Finished Mar 19 12:35:47 PM PDT 24
Peak memory 202560 kb
Host smart-64d6de15-7032-473d-aca9-85997f3d47c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462694062 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all_with_rand_reset.1462694062
Directory /workspace/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup.676848973
Short name T180
Test name
Test status
Simulation time 563031731014 ps
CPU time 332.29 seconds
Started Mar 19 12:29:20 PM PDT 24
Finished Mar 19 12:34:52 PM PDT 24
Peak memory 201776 kb
Host smart-69547556-ee66-4f36-8c2e-a7f8a59b52c9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676848973 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_
wakeup.676848973
Directory /workspace/10.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/10.adc_ctrl_fsm_reset.4173964483
Short name T214
Test name
Test status
Simulation time 77308365385 ps
CPU time 228.83 seconds
Started Mar 19 12:28:50 PM PDT 24
Finished Mar 19 12:32:40 PM PDT 24
Peak memory 202040 kb
Host smart-b76ada46-f26c-470d-83ce-b0b2661c91d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173964483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.4173964483
Directory /workspace/10.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup.3402734873
Short name T264
Test name
Test status
Simulation time 379700624455 ps
CPU time 904.95 seconds
Started Mar 19 12:29:10 PM PDT 24
Finished Mar 19 12:44:15 PM PDT 24
Peak memory 201812 kb
Host smart-ce67c322-f1f5-4723-b3b5-7f931f59e5d1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402734873 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters
_wakeup.3402734873
Directory /workspace/15.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/16.adc_ctrl_clock_gating.4176756423
Short name T245
Test name
Test status
Simulation time 553273708822 ps
CPU time 688.72 seconds
Started Mar 19 12:29:11 PM PDT 24
Finished Mar 19 12:40:41 PM PDT 24
Peak memory 201812 kb
Host smart-528746ea-7237-4719-97a6-505d629834ef
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176756423 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gat
ing.4176756423
Directory /workspace/16.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_both.1981221498
Short name T250
Test name
Test status
Simulation time 357641577612 ps
CPU time 778.27 seconds
Started Mar 19 12:29:10 PM PDT 24
Finished Mar 19 12:42:09 PM PDT 24
Peak memory 201724 kb
Host smart-899c6884-4d3e-4233-8491-ce21bb5ecab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981221498 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.1981221498
Directory /workspace/18.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt.813837663
Short name T230
Test name
Test status
Simulation time 166379914417 ps
CPU time 386.05 seconds
Started Mar 19 12:29:08 PM PDT 24
Finished Mar 19 12:35:35 PM PDT 24
Peak memory 201828 kb
Host smart-ccada36f-37ff-497c-a15f-aecab40f29f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813837663 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.813837663
Directory /workspace/19.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/21.adc_ctrl_fsm_reset.557843825
Short name T55
Test name
Test status
Simulation time 82993336220 ps
CPU time 402.41 seconds
Started Mar 19 12:29:08 PM PDT 24
Finished Mar 19 12:35:51 PM PDT 24
Peak memory 202048 kb
Host smart-358e9ad3-6d39-4970-919d-0df1e53502ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557843825 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.557843825
Directory /workspace/21.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_fsm_reset.2756839167
Short name T345
Test name
Test status
Simulation time 106487260732 ps
CPU time 338.02 seconds
Started Mar 19 12:29:32 PM PDT 24
Finished Mar 19 12:35:10 PM PDT 24
Peak memory 202092 kb
Host smart-8644217e-2146-43a6-bbf2-1eae66c0fcf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756839167 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.2756839167
Directory /workspace/28.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all.349467338
Short name T310
Test name
Test status
Simulation time 328073786753 ps
CPU time 1055.97 seconds
Started Mar 19 12:29:31 PM PDT 24
Finished Mar 19 12:47:07 PM PDT 24
Peak memory 202156 kb
Host smart-8d48ca09-c585-4bc6-a844-1efdaf966b4a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349467338 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all.
349467338
Directory /workspace/29.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt.532062410
Short name T322
Test name
Test status
Simulation time 491194538052 ps
CPU time 317 seconds
Started Mar 19 12:31:26 PM PDT 24
Finished Mar 19 12:36:43 PM PDT 24
Peak memory 201696 kb
Host smart-9f054209-a85a-4cc6-9837-a74c1a3ce289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532062410 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.532062410
Directory /workspace/30.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/31.adc_ctrl_clock_gating.1313278647
Short name T273
Test name
Test status
Simulation time 399961675640 ps
CPU time 242.44 seconds
Started Mar 19 12:29:34 PM PDT 24
Finished Mar 19 12:33:36 PM PDT 24
Peak memory 201716 kb
Host smart-147b1c6c-cccf-4685-9fa0-1aa8a0f9e865
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313278647 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gat
ing.1313278647
Directory /workspace/31.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.1139579108
Short name T122
Test name
Test status
Simulation time 719084205 ps
CPU time 1.82 seconds
Started Mar 19 12:26:51 PM PDT 24
Finished Mar 19 12:26:53 PM PDT 24
Peak memory 201712 kb
Host smart-42d588ff-454f-417f-a594-e8406570b27f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139579108 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_alia
sing.1139579108
Directory /workspace/0.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.1175941942
Short name T123
Test name
Test status
Simulation time 20526246652 ps
CPU time 11.37 seconds
Started Mar 19 12:26:51 PM PDT 24
Finished Mar 19 12:27:02 PM PDT 24
Peak memory 201832 kb
Host smart-824336f2-a805-42f2-8563-6153e1b0c565
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175941942 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_
bash.1175941942
Directory /workspace/0.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.508180257
Short name T873
Test name
Test status
Simulation time 771481804 ps
CPU time 2.78 seconds
Started Mar 19 12:27:02 PM PDT 24
Finished Mar 19 12:27:06 PM PDT 24
Peak memory 201528 kb
Host smart-0e4f479a-c04f-43cb-9bbe-2b9449fc2b10
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508180257 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_re
set.508180257
Directory /workspace/0.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.4192657784
Short name T865
Test name
Test status
Simulation time 472387556 ps
CPU time 1.09 seconds
Started Mar 19 12:27:00 PM PDT 24
Finished Mar 19 12:27:02 PM PDT 24
Peak memory 201616 kb
Host smart-34f2d69c-70b0-4b39-8994-4b958b80aade
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192657784 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.adc_ctrl_csr_mem_rw_with_rand_reset.4192657784
Directory /workspace/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.374747167
Short name T854
Test name
Test status
Simulation time 418696481 ps
CPU time 1.56 seconds
Started Mar 19 12:26:52 PM PDT 24
Finished Mar 19 12:26:54 PM PDT 24
Peak memory 201544 kb
Host smart-d0852915-b03f-4579-bbb9-46a7aaba66b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374747167 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.374747167
Directory /workspace/0.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.2953057874
Short name T129
Test name
Test status
Simulation time 4507101778 ps
CPU time 11.19 seconds
Started Mar 19 12:27:19 PM PDT 24
Finished Mar 19 12:27:31 PM PDT 24
Peak memory 201808 kb
Host smart-16456d36-6f1b-4e93-a7c3-b50abe292b67
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953057874 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_c
trl_same_csr_outstanding.2953057874
Directory /workspace/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.1455242851
Short name T881
Test name
Test status
Simulation time 426643321 ps
CPU time 3.57 seconds
Started Mar 19 12:26:42 PM PDT 24
Finished Mar 19 12:26:45 PM PDT 24
Peak memory 201804 kb
Host smart-a7ce8186-2b4f-4c8a-a879-fc51519ca0e4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455242851 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.1455242851
Directory /workspace/0.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.3208919948
Short name T897
Test name
Test status
Simulation time 4025213073 ps
CPU time 11.09 seconds
Started Mar 19 12:26:37 PM PDT 24
Finished Mar 19 12:26:48 PM PDT 24
Peak memory 201852 kb
Host smart-4859e82e-3422-45d2-b889-3f968f1bc2ae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208919948 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_in
tg_err.3208919948
Directory /workspace/0.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.3276406543
Short name T114
Test name
Test status
Simulation time 1269209228 ps
CPU time 5.87 seconds
Started Mar 19 12:26:49 PM PDT 24
Finished Mar 19 12:26:55 PM PDT 24
Peak memory 201760 kb
Host smart-4fc90127-d550-4d5b-9204-0e72a26290c7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276406543 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_alia
sing.3276406543
Directory /workspace/1.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.3779937702
Short name T841
Test name
Test status
Simulation time 52494592148 ps
CPU time 24.03 seconds
Started Mar 19 12:27:13 PM PDT 24
Finished Mar 19 12:27:39 PM PDT 24
Peak memory 201824 kb
Host smart-45ac4151-8a26-4937-b93b-05cc6170bfcf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779937702 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_
bash.3779937702
Directory /workspace/1.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.1926614706
Short name T855
Test name
Test status
Simulation time 825119294 ps
CPU time 2.68 seconds
Started Mar 19 12:27:13 PM PDT 24
Finished Mar 19 12:27:17 PM PDT 24
Peak memory 201608 kb
Host smart-e704ff33-a563-4f20-862a-915df7aa92fe
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926614706 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_r
eset.1926614706
Directory /workspace/1.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.1199421848
Short name T825
Test name
Test status
Simulation time 419192643 ps
CPU time 1.74 seconds
Started Mar 19 12:26:48 PM PDT 24
Finished Mar 19 12:26:50 PM PDT 24
Peak memory 201668 kb
Host smart-8ec1a6c3-9a72-4c93-84b0-19390610b96d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199421848 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.adc_ctrl_csr_mem_rw_with_rand_reset.1199421848
Directory /workspace/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.2971337339
Short name T125
Test name
Test status
Simulation time 504251904 ps
CPU time 1.93 seconds
Started Mar 19 12:26:48 PM PDT 24
Finished Mar 19 12:26:51 PM PDT 24
Peak memory 201592 kb
Host smart-f40e3a39-0eb5-419e-a279-c661afe7f97b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971337339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.2971337339
Directory /workspace/1.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.3413497230
Short name T816
Test name
Test status
Simulation time 508815109 ps
CPU time 1.78 seconds
Started Mar 19 12:26:59 PM PDT 24
Finished Mar 19 12:27:02 PM PDT 24
Peak memory 201292 kb
Host smart-4c669768-27c9-4043-8678-1c5a27b77ece
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413497230 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.3413497230
Directory /workspace/1.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.2869879722
Short name T880
Test name
Test status
Simulation time 2589796819 ps
CPU time 4.52 seconds
Started Mar 19 12:26:47 PM PDT 24
Finished Mar 19 12:26:52 PM PDT 24
Peak memory 202040 kb
Host smart-de87a36c-e119-4c1b-a636-b7c2caf8c1a8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869879722 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_c
trl_same_csr_outstanding.2869879722
Directory /workspace/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.1286100554
Short name T887
Test name
Test status
Simulation time 354226178 ps
CPU time 1.9 seconds
Started Mar 19 12:26:36 PM PDT 24
Finished Mar 19 12:26:39 PM PDT 24
Peak memory 208992 kb
Host smart-910482c5-df31-4443-b13d-8fd72e146d7b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286100554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.1286100554
Directory /workspace/1.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.2972521198
Short name T907
Test name
Test status
Simulation time 7715224337 ps
CPU time 7.34 seconds
Started Mar 19 12:26:48 PM PDT 24
Finished Mar 19 12:26:55 PM PDT 24
Peak memory 201804 kb
Host smart-78d1f798-1b46-4b76-a37a-f373c8c4d875
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972521198 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_in
tg_err.2972521198
Directory /workspace/1.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.1572702311
Short name T799
Test name
Test status
Simulation time 564124771 ps
CPU time 1.44 seconds
Started Mar 19 12:26:54 PM PDT 24
Finished Mar 19 12:26:56 PM PDT 24
Peak memory 201580 kb
Host smart-efd6a906-0c09-464c-9b7b-ca0bddeb3dc7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572702311 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.adc_ctrl_csr_mem_rw_with_rand_reset.1572702311
Directory /workspace/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.131962851
Short name T121
Test name
Test status
Simulation time 492591885 ps
CPU time 1.9 seconds
Started Mar 19 12:27:05 PM PDT 24
Finished Mar 19 12:27:11 PM PDT 24
Peak memory 201532 kb
Host smart-24574bc3-369a-41e7-a237-f0bf2ba644ba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131962851 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.131962851
Directory /workspace/10.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.2493982458
Short name T909
Test name
Test status
Simulation time 473603384 ps
CPU time 1.28 seconds
Started Mar 19 12:27:10 PM PDT 24
Finished Mar 19 12:27:14 PM PDT 24
Peak memory 201620 kb
Host smart-d0050853-6e95-49fa-bdb1-8262fe336032
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493982458 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.2493982458
Directory /workspace/10.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.21122498
Short name T820
Test name
Test status
Simulation time 2756830460 ps
CPU time 3.49 seconds
Started Mar 19 12:27:11 PM PDT 24
Finished Mar 19 12:27:16 PM PDT 24
Peak memory 201636 kb
Host smart-f584401a-a5ab-46d5-a8aa-bac98d499fd7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21122498 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ct
rl_same_csr_outstanding.21122498
Directory /workspace/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.1614542598
Short name T65
Test name
Test status
Simulation time 524310301 ps
CPU time 3.71 seconds
Started Mar 19 12:27:02 PM PDT 24
Finished Mar 19 12:27:07 PM PDT 24
Peak memory 209992 kb
Host smart-0281bdd0-373e-4b16-a80d-cd5f5e85907f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614542598 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.1614542598
Directory /workspace/10.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.318714797
Short name T883
Test name
Test status
Simulation time 8416493970 ps
CPU time 7.08 seconds
Started Mar 19 12:27:01 PM PDT 24
Finished Mar 19 12:27:11 PM PDT 24
Peak memory 201764 kb
Host smart-cfd1af9f-278c-4d29-ab44-3bc10fd3b2b2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318714797 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_in
tg_err.318714797
Directory /workspace/10.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.3872640714
Short name T74
Test name
Test status
Simulation time 542996769 ps
CPU time 2.14 seconds
Started Mar 19 12:27:21 PM PDT 24
Finished Mar 19 12:27:25 PM PDT 24
Peak memory 201684 kb
Host smart-7a88e733-d7ce-4fa4-8765-4327cd0a5c34
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872640714 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.adc_ctrl_csr_mem_rw_with_rand_reset.3872640714
Directory /workspace/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.1192138955
Short name T117
Test name
Test status
Simulation time 455618290 ps
CPU time 1.01 seconds
Started Mar 19 12:26:51 PM PDT 24
Finished Mar 19 12:26:54 PM PDT 24
Peak memory 201556 kb
Host smart-61f9a9e6-c65c-4bbc-807a-2c93979f21be
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192138955 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.1192138955
Directory /workspace/11.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.597525269
Short name T886
Test name
Test status
Simulation time 390372311 ps
CPU time 1.1 seconds
Started Mar 19 12:27:08 PM PDT 24
Finished Mar 19 12:27:13 PM PDT 24
Peak memory 201504 kb
Host smart-6329cc5c-320f-4cdf-8e20-448a83e2a9ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597525269 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.597525269
Directory /workspace/11.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.707636325
Short name T828
Test name
Test status
Simulation time 2668409058 ps
CPU time 11.62 seconds
Started Mar 19 12:27:24 PM PDT 24
Finished Mar 19 12:27:37 PM PDT 24
Peak memory 201816 kb
Host smart-8afe01ac-4b66-4236-bfad-ff0aabcea6e4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707636325 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_c
trl_same_csr_outstanding.707636325
Directory /workspace/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.1464197478
Short name T884
Test name
Test status
Simulation time 588934647 ps
CPU time 2.36 seconds
Started Mar 19 12:27:12 PM PDT 24
Finished Mar 19 12:27:15 PM PDT 24
Peak memory 201608 kb
Host smart-b3517cf7-705e-4140-bb6b-846b72f8a720
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464197478 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.adc_ctrl_csr_mem_rw_with_rand_reset.1464197478
Directory /workspace/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.1008569871
Short name T115
Test name
Test status
Simulation time 399017863 ps
CPU time 1.26 seconds
Started Mar 19 12:27:20 PM PDT 24
Finished Mar 19 12:27:24 PM PDT 24
Peak memory 201560 kb
Host smart-8e10936e-3c2c-4afe-9d99-a3f549682b3f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008569871 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.1008569871
Directory /workspace/12.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.3692718815
Short name T801
Test name
Test status
Simulation time 419282370 ps
CPU time 0.88 seconds
Started Mar 19 12:27:08 PM PDT 24
Finished Mar 19 12:27:13 PM PDT 24
Peak memory 201556 kb
Host smart-50b98df6-d205-406a-9ec9-f28c489565dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692718815 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.3692718815
Directory /workspace/12.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.949592572
Short name T851
Test name
Test status
Simulation time 3580795998 ps
CPU time 2.79 seconds
Started Mar 19 12:27:26 PM PDT 24
Finished Mar 19 12:27:28 PM PDT 24
Peak memory 201824 kb
Host smart-27e14858-8c88-4b87-9f76-968457c9aec8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949592572 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_c
trl_same_csr_outstanding.949592572
Directory /workspace/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.1252214802
Short name T859
Test name
Test status
Simulation time 433213363 ps
CPU time 2.24 seconds
Started Mar 19 12:26:49 PM PDT 24
Finished Mar 19 12:26:51 PM PDT 24
Peak memory 201828 kb
Host smart-4711667d-73e6-48e7-b57a-9ba3d800b424
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252214802 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.1252214802
Directory /workspace/12.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.3112231553
Short name T63
Test name
Test status
Simulation time 8614943792 ps
CPU time 4.93 seconds
Started Mar 19 12:27:09 PM PDT 24
Finished Mar 19 12:27:17 PM PDT 24
Peak memory 201880 kb
Host smart-91879150-0d69-4e34-a685-7ab7bee1ebae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112231553 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_i
ntg_err.3112231553
Directory /workspace/12.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.2558240410
Short name T857
Test name
Test status
Simulation time 553341188 ps
CPU time 1.13 seconds
Started Mar 19 12:27:17 PM PDT 24
Finished Mar 19 12:27:18 PM PDT 24
Peak memory 201612 kb
Host smart-1e33f32d-4fef-4086-a30a-d72e8d64e394
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558240410 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.adc_ctrl_csr_mem_rw_with_rand_reset.2558240410
Directory /workspace/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.879260826
Short name T904
Test name
Test status
Simulation time 350116178 ps
CPU time 1.16 seconds
Started Mar 19 12:27:21 PM PDT 24
Finished Mar 19 12:27:24 PM PDT 24
Peak memory 201580 kb
Host smart-41179e61-7066-4036-b6be-04e2a819813a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879260826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.879260826
Directory /workspace/13.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.758067548
Short name T848
Test name
Test status
Simulation time 301867058 ps
CPU time 0.98 seconds
Started Mar 19 12:27:19 PM PDT 24
Finished Mar 19 12:27:21 PM PDT 24
Peak memory 201592 kb
Host smart-9f8a6b50-ee52-4317-b669-493f16cad70b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758067548 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.758067548
Directory /workspace/13.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.589603716
Short name T130
Test name
Test status
Simulation time 3194204772 ps
CPU time 5.94 seconds
Started Mar 19 12:27:17 PM PDT 24
Finished Mar 19 12:27:23 PM PDT 24
Peak memory 201852 kb
Host smart-d1ef7aa9-2684-42e2-bd2d-aa2c27b51650
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589603716 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_c
trl_same_csr_outstanding.589603716
Directory /workspace/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.3841133982
Short name T71
Test name
Test status
Simulation time 733489281 ps
CPU time 2.27 seconds
Started Mar 19 12:27:02 PM PDT 24
Finished Mar 19 12:27:06 PM PDT 24
Peak memory 201804 kb
Host smart-4820a3d4-4778-4e93-8ddf-906fb2279430
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841133982 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.3841133982
Directory /workspace/13.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.2184370370
Short name T817
Test name
Test status
Simulation time 500865313 ps
CPU time 1.98 seconds
Started Mar 19 12:27:22 PM PDT 24
Finished Mar 19 12:27:24 PM PDT 24
Peak memory 201676 kb
Host smart-d6828c1a-c8d3-43e9-a2b7-7b521f8b2a77
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184370370 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.adc_ctrl_csr_mem_rw_with_rand_reset.2184370370
Directory /workspace/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.3449375480
Short name T133
Test name
Test status
Simulation time 515043887 ps
CPU time 0.92 seconds
Started Mar 19 12:27:27 PM PDT 24
Finished Mar 19 12:27:28 PM PDT 24
Peak memory 201608 kb
Host smart-d011ad04-888a-44c7-a21d-c9df450dc54e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449375480 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.3449375480
Directory /workspace/14.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.611389874
Short name T847
Test name
Test status
Simulation time 324884970 ps
CPU time 1.2 seconds
Started Mar 19 12:26:50 PM PDT 24
Finished Mar 19 12:26:52 PM PDT 24
Peak memory 201548 kb
Host smart-0d93ffce-2bd7-4525-acaf-5992f4d0f74f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611389874 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.611389874
Directory /workspace/14.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.616409639
Short name T819
Test name
Test status
Simulation time 2948919562 ps
CPU time 1.26 seconds
Started Mar 19 12:27:17 PM PDT 24
Finished Mar 19 12:27:18 PM PDT 24
Peak memory 201608 kb
Host smart-d8543967-769e-4c17-aaa6-a45252e559dd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616409639 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_c
trl_same_csr_outstanding.616409639
Directory /workspace/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.1037549723
Short name T78
Test name
Test status
Simulation time 4478403785 ps
CPU time 11.83 seconds
Started Mar 19 12:27:13 PM PDT 24
Finished Mar 19 12:27:26 PM PDT 24
Peak memory 201816 kb
Host smart-caa30087-46ca-468a-8d92-e411fa6c7e9b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037549723 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_i
ntg_err.1037549723
Directory /workspace/14.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.2179359075
Short name T844
Test name
Test status
Simulation time 520415346 ps
CPU time 1.59 seconds
Started Mar 19 12:26:52 PM PDT 24
Finished Mar 19 12:26:54 PM PDT 24
Peak memory 201556 kb
Host smart-559db335-038b-4e7f-acf4-b6b75865e1e0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179359075 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.adc_ctrl_csr_mem_rw_with_rand_reset.2179359075
Directory /workspace/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.3886444982
Short name T120
Test name
Test status
Simulation time 343989487 ps
CPU time 1.2 seconds
Started Mar 19 12:27:08 PM PDT 24
Finished Mar 19 12:27:13 PM PDT 24
Peak memory 201608 kb
Host smart-44eb241e-8715-43ef-af5c-274b25b6dbaa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886444982 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.3886444982
Directory /workspace/15.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.2924964166
Short name T872
Test name
Test status
Simulation time 363300155 ps
CPU time 0.82 seconds
Started Mar 19 12:27:01 PM PDT 24
Finished Mar 19 12:27:05 PM PDT 24
Peak memory 201528 kb
Host smart-1d5e263b-c10b-4eea-b020-5f7548e8089b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924964166 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.2924964166
Directory /workspace/15.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.2975101809
Short name T876
Test name
Test status
Simulation time 3887879660 ps
CPU time 9.55 seconds
Started Mar 19 12:26:53 PM PDT 24
Finished Mar 19 12:27:02 PM PDT 24
Peak memory 201816 kb
Host smart-7083401c-fa8a-44df-b7ea-450c51cceab4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975101809 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_
ctrl_same_csr_outstanding.2975101809
Directory /workspace/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.4158050436
Short name T827
Test name
Test status
Simulation time 496137660 ps
CPU time 1.99 seconds
Started Mar 19 12:27:04 PM PDT 24
Finished Mar 19 12:27:08 PM PDT 24
Peak memory 201904 kb
Host smart-3e8bb3d3-ee16-44a7-bc73-46b1d2be96c5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158050436 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.4158050436
Directory /workspace/15.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.2856837325
Short name T822
Test name
Test status
Simulation time 4441389790 ps
CPU time 6.94 seconds
Started Mar 19 12:27:14 PM PDT 24
Finished Mar 19 12:27:22 PM PDT 24
Peak memory 201836 kb
Host smart-08b52d90-2073-426e-b169-fb2a98e91421
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856837325 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_i
ntg_err.2856837325
Directory /workspace/15.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.2855536180
Short name T856
Test name
Test status
Simulation time 431998876 ps
CPU time 1.06 seconds
Started Mar 19 12:26:49 PM PDT 24
Finished Mar 19 12:26:50 PM PDT 24
Peak memory 201724 kb
Host smart-a65b9992-1bcc-4151-af4b-277d56880d3d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855536180 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.adc_ctrl_csr_mem_rw_with_rand_reset.2855536180
Directory /workspace/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.2430564966
Short name T116
Test name
Test status
Simulation time 304514054 ps
CPU time 1.43 seconds
Started Mar 19 12:27:25 PM PDT 24
Finished Mar 19 12:27:27 PM PDT 24
Peak memory 201552 kb
Host smart-84c509ff-d988-4a13-aeac-a63252de3d59
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430564966 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.2430564966
Directory /workspace/16.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.1020678283
Short name T834
Test name
Test status
Simulation time 562537974 ps
CPU time 0.9 seconds
Started Mar 19 12:26:53 PM PDT 24
Finished Mar 19 12:26:54 PM PDT 24
Peak memory 201512 kb
Host smart-93896ecd-29e5-408b-a1b4-5b3b64e26c10
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020678283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.1020678283
Directory /workspace/16.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.2484847092
Short name T132
Test name
Test status
Simulation time 2234469090 ps
CPU time 1.94 seconds
Started Mar 19 12:27:09 PM PDT 24
Finished Mar 19 12:27:14 PM PDT 24
Peak memory 201628 kb
Host smart-64afa70c-402e-4491-9e72-96d3802de727
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484847092 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_
ctrl_same_csr_outstanding.2484847092
Directory /workspace/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.2946218372
Short name T900
Test name
Test status
Simulation time 634062988 ps
CPU time 2.06 seconds
Started Mar 19 12:26:58 PM PDT 24
Finished Mar 19 12:27:01 PM PDT 24
Peak memory 201896 kb
Host smart-52608e30-8dff-42fc-9d73-bfb16405dfca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946218372 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.2946218372
Directory /workspace/16.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.203416827
Short name T62
Test name
Test status
Simulation time 8240607770 ps
CPU time 11.33 seconds
Started Mar 19 12:27:11 PM PDT 24
Finished Mar 19 12:27:24 PM PDT 24
Peak memory 201936 kb
Host smart-31a08321-9bb0-49af-b07b-9b8530d45f00
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203416827 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_in
tg_err.203416827
Directory /workspace/16.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.3310029911
Short name T808
Test name
Test status
Simulation time 628424245 ps
CPU time 1.21 seconds
Started Mar 19 12:26:50 PM PDT 24
Finished Mar 19 12:26:53 PM PDT 24
Peak memory 201620 kb
Host smart-b1f41a1a-09c4-4b3e-987e-47bf65ef5f50
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310029911 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.adc_ctrl_csr_mem_rw_with_rand_reset.3310029911
Directory /workspace/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.100021502
Short name T135
Test name
Test status
Simulation time 530661475 ps
CPU time 1.07 seconds
Started Mar 19 12:27:10 PM PDT 24
Finished Mar 19 12:27:13 PM PDT 24
Peak memory 201608 kb
Host smart-3737868c-5fb5-472b-857b-05f3ecaabe56
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100021502 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.100021502
Directory /workspace/17.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.3999486324
Short name T864
Test name
Test status
Simulation time 445107625 ps
CPU time 0.91 seconds
Started Mar 19 12:27:00 PM PDT 24
Finished Mar 19 12:27:02 PM PDT 24
Peak memory 201544 kb
Host smart-c5603ef9-735b-4cf7-a503-3ae848975b04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999486324 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.3999486324
Directory /workspace/17.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.1521245294
Short name T860
Test name
Test status
Simulation time 2105661634 ps
CPU time 2.51 seconds
Started Mar 19 12:27:12 PM PDT 24
Finished Mar 19 12:27:15 PM PDT 24
Peak memory 201552 kb
Host smart-127f24f0-b644-4b18-8498-9a8900a6ef7f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521245294 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_
ctrl_same_csr_outstanding.1521245294
Directory /workspace/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.3531959416
Short name T906
Test name
Test status
Simulation time 1866010577 ps
CPU time 2.97 seconds
Started Mar 19 12:27:12 PM PDT 24
Finished Mar 19 12:27:15 PM PDT 24
Peak memory 217724 kb
Host smart-5111a323-892c-4d1b-a6c6-1b2a0d158b00
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531959416 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.3531959416
Directory /workspace/17.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.1791996787
Short name T821
Test name
Test status
Simulation time 4989191513 ps
CPU time 2.56 seconds
Started Mar 19 12:27:04 PM PDT 24
Finished Mar 19 12:27:06 PM PDT 24
Peak memory 201976 kb
Host smart-3b70a598-0c56-4db3-8706-68f349add8e0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791996787 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_i
ntg_err.1791996787
Directory /workspace/17.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.809808712
Short name T818
Test name
Test status
Simulation time 462506944 ps
CPU time 1.11 seconds
Started Mar 19 12:27:39 PM PDT 24
Finished Mar 19 12:27:40 PM PDT 24
Peak memory 201592 kb
Host smart-6ff9263f-5f52-478c-9375-681cdb18f1b5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809808712 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.adc_ctrl_csr_mem_rw_with_rand_reset.809808712
Directory /workspace/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.3991337237
Short name T903
Test name
Test status
Simulation time 401136909 ps
CPU time 1.28 seconds
Started Mar 19 12:27:18 PM PDT 24
Finished Mar 19 12:27:21 PM PDT 24
Peak memory 201568 kb
Host smart-48ae658f-8b37-4b25-8a33-8ca0a7f49639
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991337237 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.3991337237
Directory /workspace/18.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.2682082829
Short name T805
Test name
Test status
Simulation time 442500928 ps
CPU time 1.07 seconds
Started Mar 19 12:27:05 PM PDT 24
Finished Mar 19 12:27:07 PM PDT 24
Peak memory 201552 kb
Host smart-7207a5a1-23cd-4734-b956-c6ce52525cc0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682082829 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.2682082829
Directory /workspace/18.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.2639814919
Short name T885
Test name
Test status
Simulation time 1971459489 ps
CPU time 2.11 seconds
Started Mar 19 12:27:10 PM PDT 24
Finished Mar 19 12:27:14 PM PDT 24
Peak memory 201520 kb
Host smart-5afca698-fb57-4113-84ec-c976dca45245
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639814919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_
ctrl_same_csr_outstanding.2639814919
Directory /workspace/18.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.827994015
Short name T869
Test name
Test status
Simulation time 448875984 ps
CPU time 1.67 seconds
Started Mar 19 12:27:22 PM PDT 24
Finished Mar 19 12:27:24 PM PDT 24
Peak memory 201756 kb
Host smart-36138445-3a6e-499a-bc2e-1a50d5b6628a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827994015 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.827994015
Directory /workspace/18.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.2337055471
Short name T878
Test name
Test status
Simulation time 8222602595 ps
CPU time 16.77 seconds
Started Mar 19 12:27:04 PM PDT 24
Finished Mar 19 12:27:23 PM PDT 24
Peak memory 201784 kb
Host smart-77c2cd99-41b8-4e16-a46f-b9ba21d598da
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337055471 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_i
ntg_err.2337055471
Directory /workspace/18.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.344344410
Short name T798
Test name
Test status
Simulation time 593860473 ps
CPU time 1.65 seconds
Started Mar 19 12:27:20 PM PDT 24
Finished Mar 19 12:27:24 PM PDT 24
Peak memory 201616 kb
Host smart-7ff3b541-43ca-480a-93bd-0f551ca52768
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344344410 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.adc_ctrl_csr_mem_rw_with_rand_reset.344344410
Directory /workspace/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.2074270459
Short name T118
Test name
Test status
Simulation time 560377160 ps
CPU time 0.99 seconds
Started Mar 19 12:27:16 PM PDT 24
Finished Mar 19 12:27:18 PM PDT 24
Peak memory 201548 kb
Host smart-4d0f3e64-808a-4696-8dd3-a77b1132d029
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074270459 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.2074270459
Directory /workspace/19.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.3272840271
Short name T890
Test name
Test status
Simulation time 339401143 ps
CPU time 0.99 seconds
Started Mar 19 12:26:57 PM PDT 24
Finished Mar 19 12:26:58 PM PDT 24
Peak memory 201620 kb
Host smart-32efd4d2-ef91-432a-8ecf-df7d71ed2aeb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272840271 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.3272840271
Directory /workspace/19.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.781364954
Short name T838
Test name
Test status
Simulation time 5305461364 ps
CPU time 6.37 seconds
Started Mar 19 12:27:14 PM PDT 24
Finished Mar 19 12:27:21 PM PDT 24
Peak memory 201788 kb
Host smart-c3a8798e-57fb-427b-94bd-022095fee6a2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781364954 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_c
trl_same_csr_outstanding.781364954
Directory /workspace/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.3618094258
Short name T899
Test name
Test status
Simulation time 492247257 ps
CPU time 3.23 seconds
Started Mar 19 12:27:35 PM PDT 24
Finished Mar 19 12:27:38 PM PDT 24
Peak memory 201864 kb
Host smart-6a883b8f-4359-47b8-a44b-92d9944771b3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618094258 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.3618094258
Directory /workspace/19.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.598397188
Short name T79
Test name
Test status
Simulation time 4189987427 ps
CPU time 11.02 seconds
Started Mar 19 12:27:04 PM PDT 24
Finished Mar 19 12:27:20 PM PDT 24
Peak memory 201884 kb
Host smart-bfba2424-64d5-40bc-8d81-ae1f3760e23c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598397188 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_in
tg_err.598397188
Directory /workspace/19.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.4168049652
Short name T126
Test name
Test status
Simulation time 1329000746 ps
CPU time 2.97 seconds
Started Mar 19 12:26:48 PM PDT 24
Finished Mar 19 12:26:51 PM PDT 24
Peak memory 201780 kb
Host smart-f1cd582b-0f06-453d-9845-7620f3bb64a0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168049652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_alia
sing.4168049652
Directory /workspace/2.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.2296563499
Short name T113
Test name
Test status
Simulation time 740315035 ps
CPU time 2.5 seconds
Started Mar 19 12:27:08 PM PDT 24
Finished Mar 19 12:27:15 PM PDT 24
Peak memory 201552 kb
Host smart-a4402650-9fc5-46fd-be7c-3a579e57d09e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296563499 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_r
eset.2296563499
Directory /workspace/2.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.2595109994
Short name T882
Test name
Test status
Simulation time 566698121 ps
CPU time 1.55 seconds
Started Mar 19 12:26:54 PM PDT 24
Finished Mar 19 12:26:56 PM PDT 24
Peak memory 201876 kb
Host smart-8427cb4d-2a26-4142-8fa8-086fa4f43fec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595109994 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.adc_ctrl_csr_mem_rw_with_rand_reset.2595109994
Directory /workspace/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.2473083138
Short name T901
Test name
Test status
Simulation time 547198510 ps
CPU time 1.17 seconds
Started Mar 19 12:27:02 PM PDT 24
Finished Mar 19 12:27:05 PM PDT 24
Peak memory 201652 kb
Host smart-0d851182-6efb-4cd9-86b7-515310588989
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473083138 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.2473083138
Directory /workspace/2.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.949942306
Short name T898
Test name
Test status
Simulation time 392808810 ps
CPU time 1.35 seconds
Started Mar 19 12:27:10 PM PDT 24
Finished Mar 19 12:27:14 PM PDT 24
Peak memory 201556 kb
Host smart-0423e241-e006-44f1-843a-4921cae1dc17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949942306 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.949942306
Directory /workspace/2.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.3661994966
Short name T60
Test name
Test status
Simulation time 3955898893 ps
CPU time 5.93 seconds
Started Mar 19 12:26:51 PM PDT 24
Finished Mar 19 12:26:57 PM PDT 24
Peak memory 201824 kb
Host smart-6e6baff2-87eb-4981-8fe0-814218e7cb83
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661994966 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_c
trl_same_csr_outstanding.3661994966
Directory /workspace/2.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.3285756540
Short name T70
Test name
Test status
Simulation time 470110203 ps
CPU time 2.71 seconds
Started Mar 19 12:27:11 PM PDT 24
Finished Mar 19 12:27:15 PM PDT 24
Peak memory 218148 kb
Host smart-27de9099-7c7c-4d14-a4e3-42ade9b00a83
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285756540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.3285756540
Directory /workspace/2.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.839395815
Short name T64
Test name
Test status
Simulation time 8862994071 ps
CPU time 7.8 seconds
Started Mar 19 12:26:56 PM PDT 24
Finished Mar 19 12:27:05 PM PDT 24
Peak memory 201756 kb
Host smart-28606440-fd63-47c5-9359-790783d30bba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839395815 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_int
g_err.839395815
Directory /workspace/2.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.3902087471
Short name T793
Test name
Test status
Simulation time 448840544 ps
CPU time 0.9 seconds
Started Mar 19 12:27:39 PM PDT 24
Finished Mar 19 12:27:40 PM PDT 24
Peak memory 201528 kb
Host smart-47d95b3a-4bf4-4935-bcb7-9e780b42a071
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902087471 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.3902087471
Directory /workspace/20.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.1985658960
Short name T792
Test name
Test status
Simulation time 379853359 ps
CPU time 1.53 seconds
Started Mar 19 12:27:16 PM PDT 24
Finished Mar 19 12:27:19 PM PDT 24
Peak memory 201556 kb
Host smart-30a8d981-55f5-4aa2-abb5-d64713bd7cfd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985658960 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.1985658960
Directory /workspace/21.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.107115110
Short name T823
Test name
Test status
Simulation time 395356797 ps
CPU time 1.12 seconds
Started Mar 19 12:27:23 PM PDT 24
Finished Mar 19 12:27:26 PM PDT 24
Peak memory 201588 kb
Host smart-cd9d55b1-d33e-4419-a297-0fdc55404672
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107115110 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.107115110
Directory /workspace/22.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.621242623
Short name T814
Test name
Test status
Simulation time 481721384 ps
CPU time 1.24 seconds
Started Mar 19 12:27:15 PM PDT 24
Finished Mar 19 12:27:16 PM PDT 24
Peak memory 201504 kb
Host smart-d0db0dd8-5a38-4f20-80cc-26c6d168d1bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621242623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.621242623
Directory /workspace/23.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.2533715945
Short name T815
Test name
Test status
Simulation time 402381402 ps
CPU time 0.69 seconds
Started Mar 19 12:26:57 PM PDT 24
Finished Mar 19 12:26:59 PM PDT 24
Peak memory 201608 kb
Host smart-1f0775bf-fe34-4987-b256-49aa91c6c6f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533715945 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.2533715945
Directory /workspace/24.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.3931130120
Short name T843
Test name
Test status
Simulation time 357218359 ps
CPU time 0.89 seconds
Started Mar 19 12:27:10 PM PDT 24
Finished Mar 19 12:27:13 PM PDT 24
Peak memory 201544 kb
Host smart-6e962948-7aaa-44f8-ac0a-baa3379f6e07
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931130120 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.3931130120
Directory /workspace/25.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.3632944122
Short name T836
Test name
Test status
Simulation time 399970625 ps
CPU time 0.82 seconds
Started Mar 19 12:26:55 PM PDT 24
Finished Mar 19 12:26:56 PM PDT 24
Peak memory 201552 kb
Host smart-0263e156-0758-4f3a-a010-9d87f54df9ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632944122 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.3632944122
Directory /workspace/26.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.2703714774
Short name T889
Test name
Test status
Simulation time 432336951 ps
CPU time 0.97 seconds
Started Mar 19 12:27:16 PM PDT 24
Finished Mar 19 12:27:18 PM PDT 24
Peak memory 201500 kb
Host smart-3fe9ca3a-1bc4-4667-8d47-b72f4244477d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703714774 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.2703714774
Directory /workspace/27.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.695584637
Short name T870
Test name
Test status
Simulation time 481116107 ps
CPU time 1.17 seconds
Started Mar 19 12:27:09 PM PDT 24
Finished Mar 19 12:27:13 PM PDT 24
Peak memory 201532 kb
Host smart-62d4a34a-0f7c-4a2d-b652-b59bc01e3cc0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695584637 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.695584637
Directory /workspace/28.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.771035955
Short name T797
Test name
Test status
Simulation time 443184671 ps
CPU time 1.19 seconds
Started Mar 19 12:27:17 PM PDT 24
Finished Mar 19 12:27:18 PM PDT 24
Peak memory 201524 kb
Host smart-09a868c5-aa0d-4edd-bc7a-6ce89824b88e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771035955 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.771035955
Directory /workspace/29.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.2381364280
Short name T112
Test name
Test status
Simulation time 888485005 ps
CPU time 2.73 seconds
Started Mar 19 12:26:58 PM PDT 24
Finished Mar 19 12:27:01 PM PDT 24
Peak memory 201776 kb
Host smart-e27344f9-ed3a-4425-b1c8-aa9d3509ff34
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381364280 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_alia
sing.2381364280
Directory /workspace/3.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.3916804116
Short name T59
Test name
Test status
Simulation time 25147474611 ps
CPU time 56.27 seconds
Started Mar 19 12:26:50 PM PDT 24
Finished Mar 19 12:27:46 PM PDT 24
Peak memory 201676 kb
Host smart-90be1c67-642e-4150-a471-471dbb602d2a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916804116 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_
bash.3916804116
Directory /workspace/3.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.642874938
Short name T134
Test name
Test status
Simulation time 1088867623 ps
CPU time 3.38 seconds
Started Mar 19 12:27:07 PM PDT 24
Finished Mar 19 12:27:15 PM PDT 24
Peak memory 201580 kb
Host smart-84917a19-a294-4d40-b16d-ad55eec2d46a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642874938 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_re
set.642874938
Directory /workspace/3.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.288451055
Short name T905
Test name
Test status
Simulation time 611331181 ps
CPU time 1.7 seconds
Started Mar 19 12:27:27 PM PDT 24
Finished Mar 19 12:27:29 PM PDT 24
Peak memory 201644 kb
Host smart-b9f73ab6-da9f-438f-ace9-16890c7389ef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288451055 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.adc_ctrl_csr_mem_rw_with_rand_reset.288451055
Directory /workspace/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.4070783475
Short name T835
Test name
Test status
Simulation time 554577233 ps
CPU time 2.25 seconds
Started Mar 19 12:27:12 PM PDT 24
Finished Mar 19 12:27:16 PM PDT 24
Peak memory 201548 kb
Host smart-6641803e-57b1-4165-b2df-850530ea2568
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070783475 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.4070783475
Directory /workspace/3.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.267578951
Short name T803
Test name
Test status
Simulation time 377099316 ps
CPU time 0.71 seconds
Started Mar 19 12:26:53 PM PDT 24
Finished Mar 19 12:26:54 PM PDT 24
Peak memory 201292 kb
Host smart-5e194db9-8ceb-4bab-86d9-8d37d70e85af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267578951 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.267578951
Directory /workspace/3.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.3702605219
Short name T874
Test name
Test status
Simulation time 4402375781 ps
CPU time 5 seconds
Started Mar 19 12:26:54 PM PDT 24
Finished Mar 19 12:26:59 PM PDT 24
Peak memory 201868 kb
Host smart-d57783be-a905-4323-af33-a955742b1552
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702605219 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_c
trl_same_csr_outstanding.3702605219
Directory /workspace/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.3889689530
Short name T824
Test name
Test status
Simulation time 393371896 ps
CPU time 3.11 seconds
Started Mar 19 12:26:52 PM PDT 24
Finished Mar 19 12:26:56 PM PDT 24
Peak memory 217508 kb
Host smart-14427b31-c8fb-4025-92a5-abb08157fbcd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889689530 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.3889689530
Directory /workspace/3.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.144681125
Short name T338
Test name
Test status
Simulation time 4598666224 ps
CPU time 11.89 seconds
Started Mar 19 12:26:49 PM PDT 24
Finished Mar 19 12:27:01 PM PDT 24
Peak memory 201632 kb
Host smart-e22506a4-572c-4fdf-8105-3b0cd3062f73
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144681125 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_int
g_err.144681125
Directory /workspace/3.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.465178739
Short name T796
Test name
Test status
Simulation time 304796974 ps
CPU time 0.99 seconds
Started Mar 19 12:27:17 PM PDT 24
Finished Mar 19 12:27:18 PM PDT 24
Peak memory 201584 kb
Host smart-9d20d6f2-e2ac-494a-a853-5113392770c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465178739 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.465178739
Directory /workspace/30.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.225823732
Short name T894
Test name
Test status
Simulation time 456643115 ps
CPU time 0.92 seconds
Started Mar 19 12:27:12 PM PDT 24
Finished Mar 19 12:27:13 PM PDT 24
Peak memory 201544 kb
Host smart-1a6aa5a8-9b9f-4fd4-abad-2dc859dc43bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225823732 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.225823732
Directory /workspace/31.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.3259852289
Short name T891
Test name
Test status
Simulation time 431721727 ps
CPU time 0.73 seconds
Started Mar 19 12:27:13 PM PDT 24
Finished Mar 19 12:27:15 PM PDT 24
Peak memory 201536 kb
Host smart-dfbd47ed-9f1f-4d90-98e8-4196339d74af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259852289 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.3259852289
Directory /workspace/32.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.2177790895
Short name T802
Test name
Test status
Simulation time 280695388 ps
CPU time 1.18 seconds
Started Mar 19 12:27:24 PM PDT 24
Finished Mar 19 12:27:27 PM PDT 24
Peak memory 201552 kb
Host smart-34c36a9c-fd10-4494-b572-f883f84c1f15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177790895 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.2177790895
Directory /workspace/33.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.428677243
Short name T837
Test name
Test status
Simulation time 325308256 ps
CPU time 0.82 seconds
Started Mar 19 12:27:14 PM PDT 24
Finished Mar 19 12:27:16 PM PDT 24
Peak memory 201524 kb
Host smart-df6c9e29-bb3a-422d-9995-de8365260703
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428677243 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.428677243
Directory /workspace/34.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.1544823438
Short name T852
Test name
Test status
Simulation time 534942720 ps
CPU time 1.31 seconds
Started Mar 19 12:27:12 PM PDT 24
Finished Mar 19 12:27:15 PM PDT 24
Peak memory 201532 kb
Host smart-dfb3890c-582c-41f0-b414-65deb67f2126
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544823438 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.1544823438
Directory /workspace/35.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.1836597863
Short name T846
Test name
Test status
Simulation time 466364404 ps
CPU time 0.92 seconds
Started Mar 19 12:27:12 PM PDT 24
Finished Mar 19 12:27:15 PM PDT 24
Peak memory 201544 kb
Host smart-3e8e03de-9e4f-44e1-81d0-218ce64f4212
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836597863 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.1836597863
Directory /workspace/36.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.3791941695
Short name T832
Test name
Test status
Simulation time 418957505 ps
CPU time 0.84 seconds
Started Mar 19 12:27:12 PM PDT 24
Finished Mar 19 12:27:15 PM PDT 24
Peak memory 201552 kb
Host smart-8db39bae-8ca6-433d-9482-8bf85fc412a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791941695 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.3791941695
Directory /workspace/37.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.2223271361
Short name T879
Test name
Test status
Simulation time 281653471 ps
CPU time 1.29 seconds
Started Mar 19 12:27:11 PM PDT 24
Finished Mar 19 12:27:14 PM PDT 24
Peak memory 201536 kb
Host smart-5f4933c3-e510-4e2d-b79e-6d49894853d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223271361 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.2223271361
Directory /workspace/38.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.239072690
Short name T892
Test name
Test status
Simulation time 546889347 ps
CPU time 0.99 seconds
Started Mar 19 12:27:25 PM PDT 24
Finished Mar 19 12:27:27 PM PDT 24
Peak memory 201560 kb
Host smart-92ddf2ec-ba56-41bb-ad72-f070f639a7cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239072690 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.239072690
Directory /workspace/39.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.4218892247
Short name T124
Test name
Test status
Simulation time 806456288 ps
CPU time 3.13 seconds
Started Mar 19 12:26:55 PM PDT 24
Finished Mar 19 12:26:58 PM PDT 24
Peak memory 201732 kb
Host smart-3acd1b4c-d6ba-4061-984c-b1508fa3aa74
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218892247 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_alia
sing.4218892247
Directory /workspace/4.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.3841575369
Short name T57
Test name
Test status
Simulation time 52954449759 ps
CPU time 218.48 seconds
Started Mar 19 12:27:17 PM PDT 24
Finished Mar 19 12:30:56 PM PDT 24
Peak memory 201824 kb
Host smart-56858807-f54b-4117-a354-53612658135c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841575369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_
bash.3841575369
Directory /workspace/4.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.2863838274
Short name T908
Test name
Test status
Simulation time 1409915016 ps
CPU time 4.05 seconds
Started Mar 19 12:26:58 PM PDT 24
Finished Mar 19 12:27:03 PM PDT 24
Peak memory 201540 kb
Host smart-a4c51626-80be-4e09-880c-d7b2e1c49f18
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863838274 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_r
eset.2863838274
Directory /workspace/4.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.2203653739
Short name T807
Test name
Test status
Simulation time 388910393 ps
CPU time 1.3 seconds
Started Mar 19 12:26:49 PM PDT 24
Finished Mar 19 12:26:51 PM PDT 24
Peak memory 201592 kb
Host smart-87fb0d1f-f2cb-4773-b6b1-0e74dbe92730
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203653739 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.adc_ctrl_csr_mem_rw_with_rand_reset.2203653739
Directory /workspace/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.3099464226
Short name T830
Test name
Test status
Simulation time 437341955 ps
CPU time 1.03 seconds
Started Mar 19 12:27:02 PM PDT 24
Finished Mar 19 12:27:05 PM PDT 24
Peak memory 201532 kb
Host smart-0bfcfb43-8635-4e40-a77b-3cc102e9dac4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099464226 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.3099464226
Directory /workspace/4.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.921092129
Short name T861
Test name
Test status
Simulation time 459705812 ps
CPU time 1.65 seconds
Started Mar 19 12:26:52 PM PDT 24
Finished Mar 19 12:26:54 PM PDT 24
Peak memory 201488 kb
Host smart-e556c167-d052-4f1e-a84e-07c9ba945008
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921092129 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.921092129
Directory /workspace/4.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.2711382203
Short name T127
Test name
Test status
Simulation time 4863436760 ps
CPU time 3.96 seconds
Started Mar 19 12:26:48 PM PDT 24
Finished Mar 19 12:26:53 PM PDT 24
Peak memory 201808 kb
Host smart-72098a3e-5ecd-469e-8a22-eb3612ceb504
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711382203 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_c
trl_same_csr_outstanding.2711382203
Directory /workspace/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.2716783000
Short name T893
Test name
Test status
Simulation time 480793369 ps
CPU time 3.35 seconds
Started Mar 19 12:27:01 PM PDT 24
Finished Mar 19 12:27:07 PM PDT 24
Peak memory 218008 kb
Host smart-148bf58d-8ad0-45ab-9bc7-1e446d1dd242
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716783000 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.2716783000
Directory /workspace/4.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.1486714388
Short name T863
Test name
Test status
Simulation time 8471879158 ps
CPU time 10.66 seconds
Started Mar 19 12:26:48 PM PDT 24
Finished Mar 19 12:27:00 PM PDT 24
Peak memory 201760 kb
Host smart-0f56dcd1-8572-4c52-8d38-7acedc779f04
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486714388 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_in
tg_err.1486714388
Directory /workspace/4.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.1586662671
Short name T800
Test name
Test status
Simulation time 506790453 ps
CPU time 1.2 seconds
Started Mar 19 12:27:20 PM PDT 24
Finished Mar 19 12:27:23 PM PDT 24
Peak memory 201516 kb
Host smart-24b7cb45-7446-4369-bcd7-a538e2c8d1cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586662671 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.1586662671
Directory /workspace/40.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.3945291834
Short name T871
Test name
Test status
Simulation time 472889743 ps
CPU time 1.85 seconds
Started Mar 19 12:26:59 PM PDT 24
Finished Mar 19 12:27:02 PM PDT 24
Peak memory 201532 kb
Host smart-08e3aa3c-2ecd-4392-adaa-f17f812fdac6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945291834 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.3945291834
Directory /workspace/41.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.2821833490
Short name T840
Test name
Test status
Simulation time 506512012 ps
CPU time 1.75 seconds
Started Mar 19 12:27:20 PM PDT 24
Finished Mar 19 12:27:24 PM PDT 24
Peak memory 201532 kb
Host smart-f73eb704-62c0-4433-a27c-79c70a3dc31d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821833490 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.2821833490
Directory /workspace/42.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.2020137392
Short name T850
Test name
Test status
Simulation time 333713292 ps
CPU time 0.86 seconds
Started Mar 19 12:27:21 PM PDT 24
Finished Mar 19 12:27:23 PM PDT 24
Peak memory 201452 kb
Host smart-a7916a46-6408-4169-8e9e-d53d055b1b27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020137392 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.2020137392
Directory /workspace/43.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.3451441242
Short name T811
Test name
Test status
Simulation time 520393836 ps
CPU time 0.96 seconds
Started Mar 19 12:27:04 PM PDT 24
Finished Mar 19 12:27:13 PM PDT 24
Peak memory 201556 kb
Host smart-aee2faae-1b3f-426e-aaee-fd0a84622833
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451441242 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.3451441242
Directory /workspace/44.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.155607092
Short name T868
Test name
Test status
Simulation time 306325485 ps
CPU time 1.4 seconds
Started Mar 19 12:27:18 PM PDT 24
Finished Mar 19 12:27:21 PM PDT 24
Peak memory 201588 kb
Host smart-1688c5e3-9792-432d-8c59-b7e8ca8e3d94
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155607092 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.155607092
Directory /workspace/45.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.334048678
Short name T795
Test name
Test status
Simulation time 556903573 ps
CPU time 0.93 seconds
Started Mar 19 12:27:20 PM PDT 24
Finished Mar 19 12:27:21 PM PDT 24
Peak memory 201548 kb
Host smart-8c76d389-f49b-4781-83af-2b1aaabe2f2f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334048678 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.334048678
Directory /workspace/46.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.2353439304
Short name T895
Test name
Test status
Simulation time 448937936 ps
CPU time 0.93 seconds
Started Mar 19 12:27:18 PM PDT 24
Finished Mar 19 12:27:21 PM PDT 24
Peak memory 201532 kb
Host smart-127a22af-a59d-4996-8758-e0527118df1d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353439304 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.2353439304
Directory /workspace/47.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.3680438614
Short name T794
Test name
Test status
Simulation time 493720667 ps
CPU time 1.69 seconds
Started Mar 19 12:27:22 PM PDT 24
Finished Mar 19 12:27:24 PM PDT 24
Peak memory 201548 kb
Host smart-029a265c-a763-4dee-8985-7dfd717f8e58
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680438614 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.3680438614
Directory /workspace/48.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.3908762852
Short name T809
Test name
Test status
Simulation time 441547193 ps
CPU time 1.1 seconds
Started Mar 19 12:27:09 PM PDT 24
Finished Mar 19 12:27:13 PM PDT 24
Peak memory 201552 kb
Host smart-f2d772a5-d499-42b1-b99e-89a7839b0741
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908762852 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.3908762852
Directory /workspace/49.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.3346455389
Short name T812
Test name
Test status
Simulation time 548430860 ps
CPU time 2.4 seconds
Started Mar 19 12:27:02 PM PDT 24
Finished Mar 19 12:27:06 PM PDT 24
Peak memory 201676 kb
Host smart-4fa21759-7278-44a9-a9de-65fc0e532e07
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346455389 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.adc_ctrl_csr_mem_rw_with_rand_reset.3346455389
Directory /workspace/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.1717926003
Short name T810
Test name
Test status
Simulation time 441037944 ps
CPU time 0.97 seconds
Started Mar 19 12:27:02 PM PDT 24
Finished Mar 19 12:27:05 PM PDT 24
Peak memory 201396 kb
Host smart-d4777ec8-33b3-4427-8285-cfa44c3b6302
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717926003 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.1717926003
Directory /workspace/5.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.3700511969
Short name T806
Test name
Test status
Simulation time 441593177 ps
CPU time 0.98 seconds
Started Mar 19 12:26:46 PM PDT 24
Finished Mar 19 12:26:49 PM PDT 24
Peak memory 201472 kb
Host smart-125be93d-0c81-466a-953b-06a25d2cb791
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700511969 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.3700511969
Directory /workspace/5.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.965385382
Short name T833
Test name
Test status
Simulation time 2197177441 ps
CPU time 11.07 seconds
Started Mar 19 12:27:00 PM PDT 24
Finished Mar 19 12:27:12 PM PDT 24
Peak memory 201616 kb
Host smart-3f83b769-78bc-4809-a1db-e7309e103e11
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965385382 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ct
rl_same_csr_outstanding.965385382
Directory /workspace/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.3883913089
Short name T73
Test name
Test status
Simulation time 645184548 ps
CPU time 1.73 seconds
Started Mar 19 12:26:50 PM PDT 24
Finished Mar 19 12:26:55 PM PDT 24
Peak memory 201804 kb
Host smart-0fa5a50c-c7df-4bbf-9e07-c118f4998f10
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883913089 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.3883913089
Directory /workspace/5.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.3893115989
Short name T896
Test name
Test status
Simulation time 8653627826 ps
CPU time 7.32 seconds
Started Mar 19 12:27:05 PM PDT 24
Finished Mar 19 12:27:14 PM PDT 24
Peak memory 201812 kb
Host smart-835b07c4-ebae-44e2-b351-7a2c26972946
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893115989 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_in
tg_err.3893115989
Directory /workspace/5.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.102174976
Short name T862
Test name
Test status
Simulation time 640817415 ps
CPU time 1.68 seconds
Started Mar 19 12:27:07 PM PDT 24
Finished Mar 19 12:27:14 PM PDT 24
Peak memory 201640 kb
Host smart-8f631f04-87c4-481d-88e1-fdb9bbc02a58
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102174976 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.adc_ctrl_csr_mem_rw_with_rand_reset.102174976
Directory /workspace/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.2610307046
Short name T867
Test name
Test status
Simulation time 370389477 ps
CPU time 1.45 seconds
Started Mar 19 12:27:04 PM PDT 24
Finished Mar 19 12:27:08 PM PDT 24
Peak memory 201544 kb
Host smart-0d615499-c4cd-422e-90dc-19f6cfe1cf76
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610307046 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.2610307046
Directory /workspace/6.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.3291344403
Short name T839
Test name
Test status
Simulation time 319158225 ps
CPU time 1.33 seconds
Started Mar 19 12:27:10 PM PDT 24
Finished Mar 19 12:27:14 PM PDT 24
Peak memory 201616 kb
Host smart-29063720-8815-442b-a963-d1af3507323c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291344403 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.3291344403
Directory /workspace/6.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.4083461481
Short name T131
Test name
Test status
Simulation time 2334420146 ps
CPU time 3.48 seconds
Started Mar 19 12:27:35 PM PDT 24
Finished Mar 19 12:27:38 PM PDT 24
Peak memory 201656 kb
Host smart-482be8c7-1cce-4878-a5ac-499b4a50f157
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083461481 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_c
trl_same_csr_outstanding.4083461481
Directory /workspace/6.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.3049729356
Short name T831
Test name
Test status
Simulation time 495197366 ps
CPU time 3.03 seconds
Started Mar 19 12:27:04 PM PDT 24
Finished Mar 19 12:27:12 PM PDT 24
Peak memory 201896 kb
Host smart-473b2162-38d8-4ff7-94f6-d3b84438fd22
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049729356 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.3049729356
Directory /workspace/6.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.953711433
Short name T813
Test name
Test status
Simulation time 8025745269 ps
CPU time 12.98 seconds
Started Mar 19 12:27:01 PM PDT 24
Finished Mar 19 12:27:17 PM PDT 24
Peak memory 201856 kb
Host smart-ee853a7d-75c0-4ea4-91fa-998d2ce72d5a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953711433 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_int
g_err.953711433
Directory /workspace/6.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.2844978130
Short name T849
Test name
Test status
Simulation time 475422240 ps
CPU time 1.94 seconds
Started Mar 19 12:27:00 PM PDT 24
Finished Mar 19 12:27:03 PM PDT 24
Peak memory 200780 kb
Host smart-dc092b67-e081-40ae-bb5d-7f053d854748
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844978130 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.adc_ctrl_csr_mem_rw_with_rand_reset.2844978130
Directory /workspace/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.1882324316
Short name T902
Test name
Test status
Simulation time 309290297 ps
CPU time 1.4 seconds
Started Mar 19 12:26:54 PM PDT 24
Finished Mar 19 12:26:56 PM PDT 24
Peak memory 201556 kb
Host smart-dd565111-7afd-4bd8-b383-4bf3a5b67814
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882324316 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.1882324316
Directory /workspace/7.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.3215819644
Short name T877
Test name
Test status
Simulation time 467828655 ps
CPU time 1.72 seconds
Started Mar 19 12:27:06 PM PDT 24
Finished Mar 19 12:27:08 PM PDT 24
Peak memory 201536 kb
Host smart-ec2a4367-0343-4467-b3ac-0570608946b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215819644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.3215819644
Directory /workspace/7.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.823844288
Short name T888
Test name
Test status
Simulation time 2940737040 ps
CPU time 6.94 seconds
Started Mar 19 12:27:11 PM PDT 24
Finished Mar 19 12:27:19 PM PDT 24
Peak memory 201616 kb
Host smart-9686a9d6-05c0-4813-8ba6-aaae42a1d5d6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823844288 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ct
rl_same_csr_outstanding.823844288
Directory /workspace/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.3392656982
Short name T75
Test name
Test status
Simulation time 694084803 ps
CPU time 2.57 seconds
Started Mar 19 12:26:52 PM PDT 24
Finished Mar 19 12:26:55 PM PDT 24
Peak memory 210012 kb
Host smart-9917b209-c3e3-4776-a414-f8d4f3ba9964
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392656982 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.3392656982
Directory /workspace/7.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.1243714873
Short name T858
Test name
Test status
Simulation time 7615209249 ps
CPU time 19.14 seconds
Started Mar 19 12:27:14 PM PDT 24
Finished Mar 19 12:27:34 PM PDT 24
Peak memory 201776 kb
Host smart-9fd1e99a-f53e-4ed5-8ccc-1c0aa7dfbbc4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243714873 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_in
tg_err.1243714873
Directory /workspace/7.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.1519536757
Short name T804
Test name
Test status
Simulation time 819127802 ps
CPU time 1.1 seconds
Started Mar 19 12:26:56 PM PDT 24
Finished Mar 19 12:26:58 PM PDT 24
Peak memory 201616 kb
Host smart-dd6808d2-ae32-4db7-8d17-a383d9c2603c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519536757 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.adc_ctrl_csr_mem_rw_with_rand_reset.1519536757
Directory /workspace/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.2703232536
Short name T61
Test name
Test status
Simulation time 462281830 ps
CPU time 1.9 seconds
Started Mar 19 12:27:16 PM PDT 24
Finished Mar 19 12:27:19 PM PDT 24
Peak memory 201516 kb
Host smart-71964499-44c4-4fcb-a9f9-d6a58f9f28d9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703232536 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.2703232536
Directory /workspace/8.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.3096934625
Short name T875
Test name
Test status
Simulation time 543048039 ps
CPU time 0.98 seconds
Started Mar 19 12:27:15 PM PDT 24
Finished Mar 19 12:27:16 PM PDT 24
Peak memory 201556 kb
Host smart-07400681-8cb0-4011-94fb-5b880dbb319b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096934625 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.3096934625
Directory /workspace/8.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.2116943464
Short name T128
Test name
Test status
Simulation time 2564749716 ps
CPU time 9.64 seconds
Started Mar 19 12:26:52 PM PDT 24
Finished Mar 19 12:27:02 PM PDT 24
Peak memory 201624 kb
Host smart-46906d8d-8510-4db2-ad0a-9a5c365de9e9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116943464 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_c
trl_same_csr_outstanding.2116943464
Directory /workspace/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.2007992226
Short name T829
Test name
Test status
Simulation time 510277960 ps
CPU time 1.93 seconds
Started Mar 19 12:26:52 PM PDT 24
Finished Mar 19 12:26:55 PM PDT 24
Peak memory 201868 kb
Host smart-967166d9-be27-471e-b789-c55abd2ab843
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007992226 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.2007992226
Directory /workspace/8.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.587142868
Short name T853
Test name
Test status
Simulation time 9108374148 ps
CPU time 7.41 seconds
Started Mar 19 12:27:12 PM PDT 24
Finished Mar 19 12:27:20 PM PDT 24
Peak memory 201844 kb
Host smart-feffba5a-1dcf-4ae6-af2a-2c71d7cb8d98
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587142868 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_int
g_err.587142868
Directory /workspace/8.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.3183141785
Short name T102
Test name
Test status
Simulation time 437649209 ps
CPU time 1.28 seconds
Started Mar 19 12:26:50 PM PDT 24
Finished Mar 19 12:26:51 PM PDT 24
Peak memory 201616 kb
Host smart-4611139a-9961-47c7-a3a9-02598509b9dc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183141785 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.adc_ctrl_csr_mem_rw_with_rand_reset.3183141785
Directory /workspace/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.3080995715
Short name T866
Test name
Test status
Simulation time 468581863 ps
CPU time 1.4 seconds
Started Mar 19 12:27:19 PM PDT 24
Finished Mar 19 12:27:21 PM PDT 24
Peak memory 201552 kb
Host smart-a1d07790-7c32-440c-9f5d-72525d40336e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080995715 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.3080995715
Directory /workspace/9.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.3229295934
Short name T845
Test name
Test status
Simulation time 436326521 ps
CPU time 1.1 seconds
Started Mar 19 12:27:07 PM PDT 24
Finished Mar 19 12:27:13 PM PDT 24
Peak memory 201552 kb
Host smart-c21b6829-200a-48ab-b10c-59b643f78331
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229295934 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.3229295934
Directory /workspace/9.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.139893459
Short name T842
Test name
Test status
Simulation time 1856614370 ps
CPU time 4.66 seconds
Started Mar 19 12:27:05 PM PDT 24
Finished Mar 19 12:27:11 PM PDT 24
Peak memory 201564 kb
Host smart-3860a4ab-7514-44b5-851f-dcd0477a9081
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139893459 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ct
rl_same_csr_outstanding.139893459
Directory /workspace/9.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.3068153087
Short name T76
Test name
Test status
Simulation time 1012368046 ps
CPU time 2.79 seconds
Started Mar 19 12:26:59 PM PDT 24
Finished Mar 19 12:27:02 PM PDT 24
Peak memory 218164 kb
Host smart-ff108e2f-31b2-4355-a54f-60f203ca4ead
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068153087 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.3068153087
Directory /workspace/9.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.3260600027
Short name T339
Test name
Test status
Simulation time 8419731238 ps
CPU time 23.88 seconds
Started Mar 19 12:26:49 PM PDT 24
Finished Mar 19 12:27:13 PM PDT 24
Peak memory 201772 kb
Host smart-ffc684bc-d948-4d57-a629-dfe6b485bec8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260600027 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_in
tg_err.3260600027
Directory /workspace/9.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_alert_test.2978733012
Short name T409
Test name
Test status
Simulation time 397837353 ps
CPU time 0.81 seconds
Started Mar 19 12:28:29 PM PDT 24
Finished Mar 19 12:28:30 PM PDT 24
Peak memory 201512 kb
Host smart-30be8c88-3af8-4e9d-a5ca-2617323f93c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978733012 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.2978733012
Directory /workspace/0.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.adc_ctrl_clock_gating.4206747502
Short name T642
Test name
Test status
Simulation time 368214605052 ps
CPU time 935.68 seconds
Started Mar 19 12:28:41 PM PDT 24
Finished Mar 19 12:44:17 PM PDT 24
Peak memory 201748 kb
Host smart-ab95a65d-86b7-405a-9de0-47c2596ddb85
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206747502 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gati
ng.4206747502
Directory /workspace/0.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_both.2634435098
Short name T681
Test name
Test status
Simulation time 328038109531 ps
CPU time 210.19 seconds
Started Mar 19 12:28:48 PM PDT 24
Finished Mar 19 12:32:20 PM PDT 24
Peak memory 201748 kb
Host smart-039053bf-1fae-46c3-ad9a-fe6c9a8ca456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634435098 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.2634435098
Directory /workspace/0.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt.3047418211
Short name T465
Test name
Test status
Simulation time 163961477949 ps
CPU time 385 seconds
Started Mar 19 12:29:37 PM PDT 24
Finished Mar 19 12:36:02 PM PDT 24
Peak memory 201748 kb
Host smart-b180bb21-ec82-4915-8365-4413d53d2921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047418211 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.3047418211
Directory /workspace/0.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt_fixed.2358404396
Short name T31
Test name
Test status
Simulation time 494628737551 ps
CPU time 589.64 seconds
Started Mar 19 12:28:41 PM PDT 24
Finished Mar 19 12:38:31 PM PDT 24
Peak memory 201728 kb
Host smart-bf6202d1-5418-4353-89d6-a18b505adea5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358404396 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrup
t_fixed.2358404396
Directory /workspace/0.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled_fixed.2125045784
Short name T516
Test name
Test status
Simulation time 157677377205 ps
CPU time 29.37 seconds
Started Mar 19 12:28:41 PM PDT 24
Finished Mar 19 12:29:11 PM PDT 24
Peak memory 201720 kb
Host smart-88a24b58-d11c-4523-8b2e-c8d835c578e9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125045784 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixe
d.2125045784
Directory /workspace/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup.184795278
Short name T183
Test name
Test status
Simulation time 435470338921 ps
CPU time 261.18 seconds
Started Mar 19 12:28:43 PM PDT 24
Finished Mar 19 12:33:04 PM PDT 24
Peak memory 201732 kb
Host smart-ef038ad6-7e65-4f52-90e0-c464bb13b173
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184795278 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_w
akeup.184795278
Directory /workspace/0.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup_fixed.2670352249
Short name T172
Test name
Test status
Simulation time 193254830336 ps
CPU time 117.95 seconds
Started Mar 19 12:29:35 PM PDT 24
Finished Mar 19 12:31:33 PM PDT 24
Peak memory 201864 kb
Host smart-1258577b-1726-4543-bec0-3d4561698ebe
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670352249 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.
adc_ctrl_filters_wakeup_fixed.2670352249
Directory /workspace/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_fsm_reset.3605536978
Short name T730
Test name
Test status
Simulation time 105787094645 ps
CPU time 409.95 seconds
Started Mar 19 12:28:39 PM PDT 24
Finished Mar 19 12:35:30 PM PDT 24
Peak memory 202120 kb
Host smart-c8f11ada-52a7-4617-a60f-97016a496feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605536978 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.3605536978
Directory /workspace/0.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_lowpower_counter.1583147211
Short name T692
Test name
Test status
Simulation time 27167049144 ps
CPU time 15.96 seconds
Started Mar 19 12:28:48 PM PDT 24
Finished Mar 19 12:29:05 PM PDT 24
Peak memory 201568 kb
Host smart-1345f85e-5575-4b38-8d01-fb310a324aee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583147211 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.1583147211
Directory /workspace/0.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_poweron_counter.3494863906
Short name T466
Test name
Test status
Simulation time 4964397245 ps
CPU time 3.67 seconds
Started Mar 19 12:28:44 PM PDT 24
Finished Mar 19 12:28:48 PM PDT 24
Peak memory 201548 kb
Host smart-8255d8de-d46d-4c07-a808-a5280a8ae5fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494863906 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.3494863906
Directory /workspace/0.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_smoke.3797074647
Short name T382
Test name
Test status
Simulation time 5684720170 ps
CPU time 14.54 seconds
Started Mar 19 12:28:40 PM PDT 24
Finished Mar 19 12:28:55 PM PDT 24
Peak memory 201560 kb
Host smart-f3918c48-f27b-4944-a6f9-7b5cc891d0bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797074647 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.3797074647
Directory /workspace/0.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.adc_ctrl_alert_test.2218180369
Short name T431
Test name
Test status
Simulation time 505793817 ps
CPU time 0.84 seconds
Started Mar 19 12:28:47 PM PDT 24
Finished Mar 19 12:28:47 PM PDT 24
Peak memory 201432 kb
Host smart-f80c08e6-37d7-4142-b024-78b1202e2b12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218180369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.2218180369
Directory /workspace/1.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_both.1733643073
Short name T665
Test name
Test status
Simulation time 211720314484 ps
CPU time 132.64 seconds
Started Mar 19 12:28:57 PM PDT 24
Finished Mar 19 12:31:10 PM PDT 24
Peak memory 201712 kb
Host smart-600d29c3-2b22-43ba-8718-4e27a7cb4676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733643073 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.1733643073
Directory /workspace/1.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt.2515529682
Short name T705
Test name
Test status
Simulation time 487275562307 ps
CPU time 1089.61 seconds
Started Mar 19 12:28:44 PM PDT 24
Finished Mar 19 12:46:55 PM PDT 24
Peak memory 201668 kb
Host smart-cd6cead9-5210-4250-ae1e-4f4c31e53c8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515529682 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.2515529682
Directory /workspace/1.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt_fixed.2843658799
Short name T661
Test name
Test status
Simulation time 322566618885 ps
CPU time 823.36 seconds
Started Mar 19 12:28:46 PM PDT 24
Finished Mar 19 12:42:30 PM PDT 24
Peak memory 201740 kb
Host smart-0e9cda4c-4750-41bd-86b7-7bf8b65f79e0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843658799 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrup
t_fixed.2843658799
Directory /workspace/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled.166901239
Short name T758
Test name
Test status
Simulation time 159494917593 ps
CPU time 89.19 seconds
Started Mar 19 12:28:31 PM PDT 24
Finished Mar 19 12:30:00 PM PDT 24
Peak memory 201796 kb
Host smart-accc7f4a-411d-4bab-8f6a-442855f02a4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166901239 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.166901239
Directory /workspace/1.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled_fixed.4139321137
Short name T463
Test name
Test status
Simulation time 333261205561 ps
CPU time 226.82 seconds
Started Mar 19 12:28:54 PM PDT 24
Finished Mar 19 12:32:42 PM PDT 24
Peak memory 201848 kb
Host smart-e76900ae-be2f-4a44-b11b-c07c13a8d746
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139321137 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixe
d.4139321137
Directory /workspace/1.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup.379397243
Short name T244
Test name
Test status
Simulation time 359316474666 ps
CPU time 795.99 seconds
Started Mar 19 12:28:45 PM PDT 24
Finished Mar 19 12:42:01 PM PDT 24
Peak memory 201808 kb
Host smart-061e1d71-4260-49c4-a492-9a5ccedbeb87
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379397243 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_w
akeup.379397243
Directory /workspace/1.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup_fixed.1575248619
Short name T414
Test name
Test status
Simulation time 189705514329 ps
CPU time 428.31 seconds
Started Mar 19 12:28:47 PM PDT 24
Finished Mar 19 12:35:55 PM PDT 24
Peak memory 201920 kb
Host smart-88797f4c-528a-4075-a049-17f9aaeb3bfb
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575248619 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
adc_ctrl_filters_wakeup_fixed.1575248619
Directory /workspace/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_fsm_reset.2431671058
Short name T520
Test name
Test status
Simulation time 118847689941 ps
CPU time 417.65 seconds
Started Mar 19 12:28:47 PM PDT 24
Finished Mar 19 12:35:44 PM PDT 24
Peak memory 202052 kb
Host smart-0947d36b-3ae1-486a-a7cd-f84d676404fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431671058 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.2431671058
Directory /workspace/1.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_lowpower_counter.4216453592
Short name T646
Test name
Test status
Simulation time 45803715884 ps
CPU time 97.55 seconds
Started Mar 19 12:28:57 PM PDT 24
Finished Mar 19 12:30:35 PM PDT 24
Peak memory 201552 kb
Host smart-45eadd28-5359-4b44-baf7-faf4ee0f7d64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216453592 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.4216453592
Directory /workspace/1.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_poweron_counter.2915109993
Short name T786
Test name
Test status
Simulation time 5027260758 ps
CPU time 6.25 seconds
Started Mar 19 12:28:35 PM PDT 24
Finished Mar 19 12:28:42 PM PDT 24
Peak memory 201604 kb
Host smart-18231dfc-9a08-49e0-a142-2d483dcad800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915109993 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.2915109993
Directory /workspace/1.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_sec_cm.739130506
Short name T80
Test name
Test status
Simulation time 7952873903 ps
CPU time 5.36 seconds
Started Mar 19 12:28:51 PM PDT 24
Finished Mar 19 12:28:57 PM PDT 24
Peak memory 218376 kb
Host smart-11f6be2d-25d3-4d78-a56b-c0a56150be52
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739130506 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.739130506
Directory /workspace/1.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.adc_ctrl_smoke.3850198368
Short name T450
Test name
Test status
Simulation time 5838807954 ps
CPU time 4.28 seconds
Started Mar 19 12:28:46 PM PDT 24
Finished Mar 19 12:28:50 PM PDT 24
Peak memory 201560 kb
Host smart-d35ec02a-4435-4638-85d9-19365e7b1c08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850198368 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.3850198368
Directory /workspace/1.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.1712122081
Short name T702
Test name
Test status
Simulation time 75464047617 ps
CPU time 93.59 seconds
Started Mar 19 12:28:50 PM PDT 24
Finished Mar 19 12:30:24 PM PDT 24
Peak memory 210152 kb
Host smart-f88acdb1-e082-4d87-af8c-ae0b779d62fa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712122081 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all_with_rand_reset.1712122081
Directory /workspace/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_alert_test.2766728824
Short name T650
Test name
Test status
Simulation time 487278738 ps
CPU time 0.91 seconds
Started Mar 19 12:29:04 PM PDT 24
Finished Mar 19 12:29:05 PM PDT 24
Peak memory 201492 kb
Host smart-35127214-e0c3-400b-a7e1-aa652056d9dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766728824 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.2766728824
Directory /workspace/10.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.adc_ctrl_clock_gating.1511677618
Short name T286
Test name
Test status
Simulation time 163005311675 ps
CPU time 63.84 seconds
Started Mar 19 12:29:02 PM PDT 24
Finished Mar 19 12:30:06 PM PDT 24
Peak memory 201828 kb
Host smart-50521f7e-5fc1-47de-b889-8325c1acf6e0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511677618 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gat
ing.1511677618
Directory /workspace/10.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_both.2480457264
Short name T689
Test name
Test status
Simulation time 538435976189 ps
CPU time 351.94 seconds
Started Mar 19 12:29:03 PM PDT 24
Finished Mar 19 12:34:55 PM PDT 24
Peak memory 201804 kb
Host smart-2fb713bf-67d6-474f-99d4-5b1c5b411508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480457264 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.2480457264
Directory /workspace/10.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt.1281492678
Short name T311
Test name
Test status
Simulation time 325658062985 ps
CPU time 168.8 seconds
Started Mar 19 12:28:52 PM PDT 24
Finished Mar 19 12:31:41 PM PDT 24
Peak memory 201172 kb
Host smart-61d8ba5c-8881-4530-ae1a-2050d1f7d86b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281492678 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.1281492678
Directory /workspace/10.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt_fixed.2300067464
Short name T559
Test name
Test status
Simulation time 156956783868 ps
CPU time 344.72 seconds
Started Mar 19 12:29:02 PM PDT 24
Finished Mar 19 12:34:47 PM PDT 24
Peak memory 201716 kb
Host smart-483bab4c-7465-4d75-a499-8bed8c3b65c4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300067464 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interru
pt_fixed.2300067464
Directory /workspace/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled.2198959332
Short name T733
Test name
Test status
Simulation time 330307838593 ps
CPU time 730.45 seconds
Started Mar 19 12:28:51 PM PDT 24
Finished Mar 19 12:41:02 PM PDT 24
Peak memory 201804 kb
Host smart-360f36db-093c-4914-a406-0135d485c96f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198959332 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.2198959332
Directory /workspace/10.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled_fixed.1179747581
Short name T746
Test name
Test status
Simulation time 322936053146 ps
CPU time 771.18 seconds
Started Mar 19 12:29:21 PM PDT 24
Finished Mar 19 12:42:12 PM PDT 24
Peak memory 201772 kb
Host smart-0330e299-95fe-49cc-8f80-bdfdf920cfee
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179747581 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fix
ed.1179747581
Directory /workspace/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup_fixed.1092523069
Short name T717
Test name
Test status
Simulation time 199818330458 ps
CPU time 127.17 seconds
Started Mar 19 12:28:57 PM PDT 24
Finished Mar 19 12:31:05 PM PDT 24
Peak memory 201748 kb
Host smart-66efc4ab-ada2-4127-be58-609c96f3d2a3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092523069 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10
.adc_ctrl_filters_wakeup_fixed.1092523069
Directory /workspace/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_lowpower_counter.1723551676
Short name T421
Test name
Test status
Simulation time 37142885236 ps
CPU time 84.72 seconds
Started Mar 19 12:29:19 PM PDT 24
Finished Mar 19 12:30:44 PM PDT 24
Peak memory 201572 kb
Host smart-5db51f04-da69-4a71-b78b-07420a21acbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723551676 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.1723551676
Directory /workspace/10.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_poweron_counter.2010540677
Short name T691
Test name
Test status
Simulation time 2891957123 ps
CPU time 4.16 seconds
Started Mar 19 12:28:52 PM PDT 24
Finished Mar 19 12:28:57 PM PDT 24
Peak memory 201572 kb
Host smart-43f0bef3-1c82-4710-83f6-518a7a5869aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010540677 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.2010540677
Directory /workspace/10.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_smoke.329089083
Short name T656
Test name
Test status
Simulation time 5723850725 ps
CPU time 7.6 seconds
Started Mar 19 12:29:05 PM PDT 24
Finished Mar 19 12:29:13 PM PDT 24
Peak memory 201584 kb
Host smart-13feb37c-bf26-4cf5-86e0-9648e5d8728f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329089083 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.329089083
Directory /workspace/10.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.1687496482
Short name T332
Test name
Test status
Simulation time 1760128049332 ps
CPU time 262.54 seconds
Started Mar 19 12:29:02 PM PDT 24
Finished Mar 19 12:33:25 PM PDT 24
Peak memory 210448 kb
Host smart-2a60ba33-1de5-46cb-8da5-f2365e6afcc4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687496482 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all_with_rand_reset.1687496482
Directory /workspace/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_alert_test.870958494
Short name T518
Test name
Test status
Simulation time 423130292 ps
CPU time 0.84 seconds
Started Mar 19 12:29:03 PM PDT 24
Finished Mar 19 12:29:04 PM PDT 24
Peak memory 201456 kb
Host smart-74f50653-71e8-4a60-ac1b-64e1d521851e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870958494 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.870958494
Directory /workspace/11.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.adc_ctrl_clock_gating.812056675
Short name T329
Test name
Test status
Simulation time 339605187361 ps
CPU time 815.9 seconds
Started Mar 19 12:29:05 PM PDT 24
Finished Mar 19 12:42:41 PM PDT 24
Peak memory 201752 kb
Host smart-af72eb20-5d9f-4ba6-a000-5aa3c743ac53
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812056675 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gati
ng.812056675
Directory /workspace/11.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_both.4203012552
Short name T761
Test name
Test status
Simulation time 505962192236 ps
CPU time 1253.17 seconds
Started Mar 19 12:29:01 PM PDT 24
Finished Mar 19 12:49:54 PM PDT 24
Peak memory 201836 kb
Host smart-951b74be-f02a-4669-ab86-cba5c6e21712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203012552 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.4203012552
Directory /workspace/11.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt.1872363378
Short name T312
Test name
Test status
Simulation time 160908190611 ps
CPU time 392.03 seconds
Started Mar 19 12:28:57 PM PDT 24
Finished Mar 19 12:35:30 PM PDT 24
Peak memory 201756 kb
Host smart-795839cd-8158-4abf-a8c5-cd99fa5a617b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872363378 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.1872363378
Directory /workspace/11.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.31671717
Short name T623
Test name
Test status
Simulation time 328425547724 ps
CPU time 791.62 seconds
Started Mar 19 12:29:06 PM PDT 24
Finished Mar 19 12:42:19 PM PDT 24
Peak memory 201732 kb
Host smart-1116e799-1779-4210-9295-aa9b886155a8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=31671717 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt
_fixed.31671717
Directory /workspace/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled_fixed.4261720053
Short name T419
Test name
Test status
Simulation time 325429557152 ps
CPU time 198.87 seconds
Started Mar 19 12:28:47 PM PDT 24
Finished Mar 19 12:32:06 PM PDT 24
Peak memory 201732 kb
Host smart-42fb12a9-1074-466c-ac40-62585236e2e3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261720053 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fix
ed.4261720053
Directory /workspace/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup.4145195805
Short name T11
Test name
Test status
Simulation time 362003064816 ps
CPU time 867.5 seconds
Started Mar 19 12:29:03 PM PDT 24
Finished Mar 19 12:43:30 PM PDT 24
Peak memory 201816 kb
Host smart-326e672e-a2aa-4a12-bfb0-80edb37d61f4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145195805 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters
_wakeup.4145195805
Directory /workspace/11.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.1949488914
Short name T96
Test name
Test status
Simulation time 616693258835 ps
CPU time 1400.26 seconds
Started Mar 19 12:29:10 PM PDT 24
Finished Mar 19 12:52:30 PM PDT 24
Peak memory 201816 kb
Host smart-c904df3d-a16f-422b-83ef-7ca1242d63e1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949488914 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11
.adc_ctrl_filters_wakeup_fixed.1949488914
Directory /workspace/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_fsm_reset.4049288258
Short name T461
Test name
Test status
Simulation time 72292882195 ps
CPU time 412.68 seconds
Started Mar 19 12:29:07 PM PDT 24
Finished Mar 19 12:36:00 PM PDT 24
Peak memory 202120 kb
Host smart-eac8e1ad-2afa-42a6-a16e-e10ef2f9b67d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049288258 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.4049288258
Directory /workspace/11.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_lowpower_counter.39929441
Short name T568
Test name
Test status
Simulation time 42883828928 ps
CPU time 7.83 seconds
Started Mar 19 12:29:14 PM PDT 24
Finished Mar 19 12:29:24 PM PDT 24
Peak memory 201528 kb
Host smart-0a8685b4-a8d5-4a8d-962d-3dc450be3d8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39929441 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.39929441
Directory /workspace/11.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_poweron_counter.1853051238
Short name T755
Test name
Test status
Simulation time 3570387028 ps
CPU time 9.66 seconds
Started Mar 19 12:28:52 PM PDT 24
Finished Mar 19 12:29:02 PM PDT 24
Peak memory 201612 kb
Host smart-b3007712-c69b-4ff1-aa43-a39b74ff698a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853051238 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.1853051238
Directory /workspace/11.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_smoke.3241233240
Short name T695
Test name
Test status
Simulation time 5836795793 ps
CPU time 1.83 seconds
Started Mar 19 12:29:01 PM PDT 24
Finished Mar 19 12:29:03 PM PDT 24
Peak memory 201644 kb
Host smart-dd622cb0-c2f3-4b5d-8bf5-c93c7130d719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241233240 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.3241233240
Directory /workspace/11.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all.781845183
Short name T267
Test name
Test status
Simulation time 292374711650 ps
CPU time 924.04 seconds
Started Mar 19 12:29:07 PM PDT 24
Finished Mar 19 12:44:32 PM PDT 24
Peak memory 210340 kb
Host smart-a7f39771-be37-46f2-9e47-8c4f7dc5a0ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781845183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all.
781845183
Directory /workspace/11.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.116165928
Short name T27
Test name
Test status
Simulation time 1044669117354 ps
CPU time 497.25 seconds
Started Mar 19 12:29:02 PM PDT 24
Finished Mar 19 12:37:20 PM PDT 24
Peak memory 217776 kb
Host smart-df8b373f-3b60-4b2d-8b6d-223053195c4a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116165928 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all_with_rand_reset.116165928
Directory /workspace/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_alert_test.3410580081
Short name T440
Test name
Test status
Simulation time 311151207 ps
CPU time 1.29 seconds
Started Mar 19 12:29:38 PM PDT 24
Finished Mar 19 12:29:39 PM PDT 24
Peak memory 201444 kb
Host smart-3aab7fb4-0ac3-4a4b-9a95-aba28ea03946
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410580081 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.3410580081
Directory /workspace/12.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.adc_ctrl_clock_gating.1071143984
Short name T325
Test name
Test status
Simulation time 177045177277 ps
CPU time 453.47 seconds
Started Mar 19 12:29:13 PM PDT 24
Finished Mar 19 12:36:48 PM PDT 24
Peak memory 201812 kb
Host smart-4c6227e5-2699-4992-bd12-340cda5fee6e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071143984 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gat
ing.1071143984
Directory /workspace/12.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt.1083590321
Short name T302
Test name
Test status
Simulation time 323464343088 ps
CPU time 717.55 seconds
Started Mar 19 12:29:16 PM PDT 24
Finished Mar 19 12:41:15 PM PDT 24
Peak memory 201884 kb
Host smart-638b36d7-8864-455b-97ca-5d76a43d0b4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083590321 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.1083590321
Directory /workspace/12.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.3685281590
Short name T575
Test name
Test status
Simulation time 332096921158 ps
CPU time 379.73 seconds
Started Mar 19 12:28:49 PM PDT 24
Finished Mar 19 12:35:09 PM PDT 24
Peak memory 201784 kb
Host smart-bb55eabd-9008-46aa-a306-d0c8ed68d6a6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685281590 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interru
pt_fixed.3685281590
Directory /workspace/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled.1946933770
Short name T660
Test name
Test status
Simulation time 484573591981 ps
CPU time 309.62 seconds
Started Mar 19 12:28:47 PM PDT 24
Finished Mar 19 12:33:57 PM PDT 24
Peak memory 201724 kb
Host smart-68ad43df-7cdc-42f2-b9a4-ea8cd6844946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946933770 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.1946933770
Directory /workspace/12.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.1281336570
Short name T605
Test name
Test status
Simulation time 499609615344 ps
CPU time 1208.29 seconds
Started Mar 19 12:29:09 PM PDT 24
Finished Mar 19 12:49:18 PM PDT 24
Peak memory 201884 kb
Host smart-29e955a6-9235-4a5f-9f11-68afa4592241
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281336570 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fix
ed.1281336570
Directory /workspace/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup.2080754586
Short name T175
Test name
Test status
Simulation time 174959470872 ps
CPU time 197.76 seconds
Started Mar 19 12:28:45 PM PDT 24
Finished Mar 19 12:32:03 PM PDT 24
Peak memory 201820 kb
Host smart-437f1d12-b913-4d9c-a5ef-d342e2a17599
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080754586 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters
_wakeup.2080754586
Directory /workspace/12.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup_fixed.3378214265
Short name T593
Test name
Test status
Simulation time 195743991422 ps
CPU time 107.04 seconds
Started Mar 19 12:29:07 PM PDT 24
Finished Mar 19 12:30:55 PM PDT 24
Peak memory 201872 kb
Host smart-83c5d6ba-d851-4f9b-8592-47da9b3afc03
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378214265 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12
.adc_ctrl_filters_wakeup_fixed.3378214265
Directory /workspace/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_fsm_reset.1805138487
Short name T444
Test name
Test status
Simulation time 85143380283 ps
CPU time 268.78 seconds
Started Mar 19 12:29:34 PM PDT 24
Finished Mar 19 12:34:03 PM PDT 24
Peak memory 202036 kb
Host smart-a8214a97-abd0-4fcb-8f7c-84af4f37d888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805138487 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.1805138487
Directory /workspace/12.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_lowpower_counter.636676557
Short name T690
Test name
Test status
Simulation time 25162963591 ps
CPU time 15.8 seconds
Started Mar 19 12:29:11 PM PDT 24
Finished Mar 19 12:29:28 PM PDT 24
Peak memory 201572 kb
Host smart-2ea2eb8e-6e4b-4c8c-950f-7710f2eabd8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636676557 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.636676557
Directory /workspace/12.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_poweron_counter.3074581584
Short name T579
Test name
Test status
Simulation time 3291667978 ps
CPU time 1.47 seconds
Started Mar 19 12:29:24 PM PDT 24
Finished Mar 19 12:29:26 PM PDT 24
Peak memory 201568 kb
Host smart-43d0241d-b3a4-4733-b2dc-e40935f99d6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074581584 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.3074581584
Directory /workspace/12.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_smoke.3726527865
Short name T374
Test name
Test status
Simulation time 5626845003 ps
CPU time 3.41 seconds
Started Mar 19 12:28:57 PM PDT 24
Finished Mar 19 12:29:01 PM PDT 24
Peak memory 201548 kb
Host smart-e9269a81-72c1-4ce9-9bf4-e3410183894b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726527865 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.3726527865
Directory /workspace/12.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.2174955222
Short name T21
Test name
Test status
Simulation time 9193609725 ps
CPU time 27.02 seconds
Started Mar 19 12:29:18 PM PDT 24
Finished Mar 19 12:29:45 PM PDT 24
Peak memory 210244 kb
Host smart-d484b248-cdeb-436e-9216-b18e45c5d307
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174955222 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all_with_rand_reset.2174955222
Directory /workspace/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_alert_test.3307475967
Short name T591
Test name
Test status
Simulation time 382564518 ps
CPU time 1.45 seconds
Started Mar 19 12:29:12 PM PDT 24
Finished Mar 19 12:29:15 PM PDT 24
Peak memory 201276 kb
Host smart-7bc24227-4abe-4fc3-b6ac-152e1d9e7cd0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307475967 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.3307475967
Directory /workspace/13.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.adc_ctrl_clock_gating.700046768
Short name T281
Test name
Test status
Simulation time 344635596554 ps
CPU time 788.03 seconds
Started Mar 19 12:29:06 PM PDT 24
Finished Mar 19 12:42:14 PM PDT 24
Peak memory 201800 kb
Host smart-f698e214-f00d-4c42-9782-abea197dcadf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700046768 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gati
ng.700046768
Directory /workspace/13.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_both.595118367
Short name T323
Test name
Test status
Simulation time 162153954223 ps
CPU time 359.74 seconds
Started Mar 19 12:29:29 PM PDT 24
Finished Mar 19 12:35:29 PM PDT 24
Peak memory 201736 kb
Host smart-91c45f3f-d813-4098-a8c0-0a494a2dbe2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595118367 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.595118367
Directory /workspace/13.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt.803456856
Short name T236
Test name
Test status
Simulation time 168533804490 ps
CPU time 206.98 seconds
Started Mar 19 12:29:12 PM PDT 24
Finished Mar 19 12:32:41 PM PDT 24
Peak memory 201724 kb
Host smart-9d1d8491-fbef-4be1-8c46-edb713607ab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803456856 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.803456856
Directory /workspace/13.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt_fixed.2537012029
Short name T602
Test name
Test status
Simulation time 328360071159 ps
CPU time 767.99 seconds
Started Mar 19 12:29:11 PM PDT 24
Finished Mar 19 12:42:00 PM PDT 24
Peak memory 201808 kb
Host smart-03a22571-a539-4a90-8527-e7c9f5f65b7b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537012029 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interru
pt_fixed.2537012029
Directory /workspace/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled.3792162396
Short name T98
Test name
Test status
Simulation time 322450864524 ps
CPU time 663.68 seconds
Started Mar 19 12:29:09 PM PDT 24
Finished Mar 19 12:40:13 PM PDT 24
Peak memory 201796 kb
Host smart-9c0b1919-1dc2-45a2-93b4-baf85b161f72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792162396 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.3792162396
Directory /workspace/13.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled_fixed.3406832967
Short name T757
Test name
Test status
Simulation time 162905804215 ps
CPU time 399.17 seconds
Started Mar 19 12:29:12 PM PDT 24
Finished Mar 19 12:35:53 PM PDT 24
Peak memory 201596 kb
Host smart-d141b31c-cec9-49fa-bb3d-c80185af15df
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406832967 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fix
ed.3406832967
Directory /workspace/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup.4521652
Short name T139
Test name
Test status
Simulation time 351095010135 ps
CPU time 334.48 seconds
Started Mar 19 12:28:58 PM PDT 24
Finished Mar 19 12:34:34 PM PDT 24
Peak memory 201880 kb
Host smart-c324767b-c012-4a17-aeb2-34e2b989ae73
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4521652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_w
akeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_wa
keup.4521652
Directory /workspace/13.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup_fixed.2995774507
Short name T109
Test name
Test status
Simulation time 598678794551 ps
CPU time 1266.89 seconds
Started Mar 19 12:29:07 PM PDT 24
Finished Mar 19 12:50:15 PM PDT 24
Peak memory 201804 kb
Host smart-2e663e1e-28ee-4ecb-bb11-8f80800ad324
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995774507 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13
.adc_ctrl_filters_wakeup_fixed.2995774507
Directory /workspace/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_fsm_reset.2172254411
Short name T697
Test name
Test status
Simulation time 64122077489 ps
CPU time 256.2 seconds
Started Mar 19 12:29:28 PM PDT 24
Finished Mar 19 12:33:44 PM PDT 24
Peak memory 202116 kb
Host smart-de4e33e6-5ba1-4119-a09c-5877e19b516b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172254411 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.2172254411
Directory /workspace/13.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_lowpower_counter.1364399408
Short name T783
Test name
Test status
Simulation time 26298130643 ps
CPU time 63.43 seconds
Started Mar 19 12:29:33 PM PDT 24
Finished Mar 19 12:30:37 PM PDT 24
Peak memory 201608 kb
Host smart-3ca546ae-ff58-4ea2-9ee8-0fc757a4a02e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364399408 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.1364399408
Directory /workspace/13.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_poweron_counter.4135728994
Short name T628
Test name
Test status
Simulation time 3095407628 ps
CPU time 7.34 seconds
Started Mar 19 12:29:09 PM PDT 24
Finished Mar 19 12:29:17 PM PDT 24
Peak memory 201636 kb
Host smart-368fc6e9-3a6d-4d6b-b2e5-93139c793846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135728994 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.4135728994
Directory /workspace/13.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_smoke.250875690
Short name T392
Test name
Test status
Simulation time 6206235620 ps
CPU time 8.69 seconds
Started Mar 19 12:29:35 PM PDT 24
Finished Mar 19 12:29:43 PM PDT 24
Peak memory 200948 kb
Host smart-efaae2c4-e983-4b58-8fca-c8e3486ec07f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250875690 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.250875690
Directory /workspace/13.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.3992825101
Short name T270
Test name
Test status
Simulation time 113252326110 ps
CPU time 73.02 seconds
Started Mar 19 12:29:05 PM PDT 24
Finished Mar 19 12:30:18 PM PDT 24
Peak memory 202164 kb
Host smart-9f0d70de-2d08-4cdf-8fe3-cdad7f342dd7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992825101 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all_with_rand_reset.3992825101
Directory /workspace/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_clock_gating.4052811837
Short name T601
Test name
Test status
Simulation time 196454522533 ps
CPU time 241.07 seconds
Started Mar 19 12:29:08 PM PDT 24
Finished Mar 19 12:33:10 PM PDT 24
Peak memory 201832 kb
Host smart-829aadeb-8231-4c90-bea2-1916e0ca0529
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052811837 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gat
ing.4052811837
Directory /workspace/14.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt.2022694238
Short name T253
Test name
Test status
Simulation time 165368879922 ps
CPU time 391.72 seconds
Started Mar 19 12:29:11 PM PDT 24
Finished Mar 19 12:35:44 PM PDT 24
Peak memory 201748 kb
Host smart-04ff8ae9-ff05-4c39-8316-8a886d0eaacf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022694238 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.2022694238
Directory /workspace/14.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt_fixed.1999946410
Short name T503
Test name
Test status
Simulation time 168839158973 ps
CPU time 367.35 seconds
Started Mar 19 12:29:04 PM PDT 24
Finished Mar 19 12:35:11 PM PDT 24
Peak memory 201732 kb
Host smart-899cdb59-2e8a-4986-8069-282316ac9f4a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999946410 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interru
pt_fixed.1999946410
Directory /workspace/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled.488013180
Short name T683
Test name
Test status
Simulation time 163311449384 ps
CPU time 102.92 seconds
Started Mar 19 12:29:09 PM PDT 24
Finished Mar 19 12:30:52 PM PDT 24
Peak memory 201784 kb
Host smart-24772dc7-1fbb-487c-b50c-ce046d66ff21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488013180 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.488013180
Directory /workspace/14.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled_fixed.2737998381
Short name T713
Test name
Test status
Simulation time 494117139077 ps
CPU time 1240.55 seconds
Started Mar 19 12:29:23 PM PDT 24
Finished Mar 19 12:50:03 PM PDT 24
Peak memory 201836 kb
Host smart-06e936c8-4277-4566-85c0-1465e7642a10
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737998381 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fix
ed.2737998381
Directory /workspace/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup.145651792
Short name T617
Test name
Test status
Simulation time 479159600742 ps
CPU time 150.28 seconds
Started Mar 19 12:29:30 PM PDT 24
Finished Mar 19 12:32:01 PM PDT 24
Peak memory 201760 kb
Host smart-a8c47231-65d1-4eee-9bf7-e6211e5d49d4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145651792 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_
wakeup.145651792
Directory /workspace/14.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup_fixed.257158998
Short name T368
Test name
Test status
Simulation time 412278941715 ps
CPU time 1018.94 seconds
Started Mar 19 12:29:27 PM PDT 24
Finished Mar 19 12:46:26 PM PDT 24
Peak memory 201772 kb
Host smart-61609ff7-e756-4c0c-8da7-66becf04209a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257158998 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.
adc_ctrl_filters_wakeup_fixed.257158998
Directory /workspace/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_fsm_reset.1787105125
Short name T408
Test name
Test status
Simulation time 126553742483 ps
CPU time 497.71 seconds
Started Mar 19 12:29:18 PM PDT 24
Finished Mar 19 12:37:36 PM PDT 24
Peak memory 202180 kb
Host smart-402b9237-41b0-4163-bcae-eaa4022f5d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787105125 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.1787105125
Directory /workspace/14.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_lowpower_counter.3394534785
Short name T641
Test name
Test status
Simulation time 41892631687 ps
CPU time 50.41 seconds
Started Mar 19 12:29:20 PM PDT 24
Finished Mar 19 12:30:11 PM PDT 24
Peak memory 201544 kb
Host smart-671a8c65-55d9-4150-b3af-ac8aae390e97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394534785 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.3394534785
Directory /workspace/14.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_poweron_counter.81762345
Short name T626
Test name
Test status
Simulation time 5132175710 ps
CPU time 6.74 seconds
Started Mar 19 12:29:11 PM PDT 24
Finished Mar 19 12:29:19 PM PDT 24
Peak memory 201548 kb
Host smart-58ab3e31-5c29-4fe0-879a-01606147df22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81762345 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.81762345
Directory /workspace/14.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_smoke.948421248
Short name T710
Test name
Test status
Simulation time 5637371653 ps
CPU time 4.28 seconds
Started Mar 19 12:29:13 PM PDT 24
Finished Mar 19 12:29:19 PM PDT 24
Peak memory 201560 kb
Host smart-e05af27f-0f2b-4b39-8e15-b82af31d3374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948421248 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.948421248
Directory /workspace/14.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.4274573529
Short name T305
Test name
Test status
Simulation time 36093981232 ps
CPU time 30.81 seconds
Started Mar 19 12:29:07 PM PDT 24
Finished Mar 19 12:29:38 PM PDT 24
Peak memory 201932 kb
Host smart-29a1c5a1-6a89-481a-8c5c-909414f4cee2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274573529 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all_with_rand_reset.4274573529
Directory /workspace/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_alert_test.2507999206
Short name T25
Test name
Test status
Simulation time 577936268 ps
CPU time 0.71 seconds
Started Mar 19 12:29:06 PM PDT 24
Finished Mar 19 12:29:08 PM PDT 24
Peak memory 201436 kb
Host smart-357d670a-b310-4404-922c-057c7ad5cc4c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507999206 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.2507999206
Directory /workspace/15.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.adc_ctrl_clock_gating.3526101892
Short name T185
Test name
Test status
Simulation time 512460602214 ps
CPU time 49.27 seconds
Started Mar 19 12:29:27 PM PDT 24
Finished Mar 19 12:30:16 PM PDT 24
Peak memory 201740 kb
Host smart-81ebb3af-1294-42e2-83b2-48aa5ec1c681
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526101892 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gat
ing.3526101892
Directory /workspace/15.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt.2014735743
Short name T268
Test name
Test status
Simulation time 332306152016 ps
CPU time 589.97 seconds
Started Mar 19 12:29:34 PM PDT 24
Finished Mar 19 12:39:24 PM PDT 24
Peak memory 201740 kb
Host smart-08e476eb-7e5b-4f5f-b099-1fabb962f581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014735743 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.2014735743
Directory /workspace/15.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt_fixed.1421599211
Short name T732
Test name
Test status
Simulation time 163400053591 ps
CPU time 377.93 seconds
Started Mar 19 12:29:06 PM PDT 24
Finished Mar 19 12:35:24 PM PDT 24
Peak memory 201788 kb
Host smart-4a5d4e0c-41a6-4630-aee2-282c4bbd8d53
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421599211 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interru
pt_fixed.1421599211
Directory /workspace/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled.879307113
Short name T320
Test name
Test status
Simulation time 157727438236 ps
CPU time 173.68 seconds
Started Mar 19 12:29:33 PM PDT 24
Finished Mar 19 12:32:27 PM PDT 24
Peak memory 201752 kb
Host smart-455238da-fd13-4682-a872-7064760bc024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879307113 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.879307113
Directory /workspace/15.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled_fixed.3153036336
Short name T372
Test name
Test status
Simulation time 491191451480 ps
CPU time 293.05 seconds
Started Mar 19 12:29:09 PM PDT 24
Finished Mar 19 12:34:02 PM PDT 24
Peak memory 201888 kb
Host smart-51d87538-5655-4c97-a5ab-97905cdc46e9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153036336 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fix
ed.3153036336
Directory /workspace/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup_fixed.3342247437
Short name T725
Test name
Test status
Simulation time 405561397090 ps
CPU time 432.58 seconds
Started Mar 19 12:29:27 PM PDT 24
Finished Mar 19 12:36:39 PM PDT 24
Peak memory 201812 kb
Host smart-17712c12-5f4e-412d-a3f0-6ecd000bc64d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342247437 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.adc_ctrl_filters_wakeup_fixed.3342247437
Directory /workspace/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_fsm_reset.685449322
Short name T668
Test name
Test status
Simulation time 98492731646 ps
CPU time 407.28 seconds
Started Mar 19 12:29:09 PM PDT 24
Finished Mar 19 12:35:57 PM PDT 24
Peak memory 202112 kb
Host smart-31671bcd-ffc6-4b77-911b-b6a691f8ab84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685449322 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.685449322
Directory /workspace/15.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_lowpower_counter.1883369101
Short name T543
Test name
Test status
Simulation time 22755145757 ps
CPU time 12.85 seconds
Started Mar 19 12:29:26 PM PDT 24
Finished Mar 19 12:29:39 PM PDT 24
Peak memory 201572 kb
Host smart-b6856d86-1913-41bc-8d44-f1a8a4013906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883369101 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.1883369101
Directory /workspace/15.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_poweron_counter.939720211
Short name T5
Test name
Test status
Simulation time 4552656895 ps
CPU time 10.92 seconds
Started Mar 19 12:29:15 PM PDT 24
Finished Mar 19 12:29:28 PM PDT 24
Peak memory 201520 kb
Host smart-2dc7aefe-0681-4abb-b43c-47adbc23ff9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939720211 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.939720211
Directory /workspace/15.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_smoke.2259154668
Short name T496
Test name
Test status
Simulation time 6005229266 ps
CPU time 10.17 seconds
Started Mar 19 12:29:13 PM PDT 24
Finished Mar 19 12:29:24 PM PDT 24
Peak memory 201584 kb
Host smart-e80730bb-b97d-4d06-a193-780fd0e40437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259154668 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.2259154668
Directory /workspace/15.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all.3402372926
Short name T38
Test name
Test status
Simulation time 80445054850 ps
CPU time 391.89 seconds
Started Mar 19 12:29:25 PM PDT 24
Finished Mar 19 12:35:57 PM PDT 24
Peak memory 210328 kb
Host smart-ab2bf45d-f40c-41e0-bc80-ff5d4c26c7c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402372926 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all
.3402372926
Directory /workspace/15.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.2886660357
Short name T578
Test name
Test status
Simulation time 109373487701 ps
CPU time 125.77 seconds
Started Mar 19 12:29:07 PM PDT 24
Finished Mar 19 12:31:13 PM PDT 24
Peak memory 210216 kb
Host smart-4ec6260b-2b2c-416d-abd7-73b83b588f38
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886660357 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all_with_rand_reset.2886660357
Directory /workspace/15.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_alert_test.2215846061
Short name T652
Test name
Test status
Simulation time 424428464 ps
CPU time 1.62 seconds
Started Mar 19 12:29:12 PM PDT 24
Finished Mar 19 12:29:14 PM PDT 24
Peak memory 201464 kb
Host smart-78489672-766e-4e0e-b054-169fb4162fc0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215846061 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.2215846061
Directory /workspace/16.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_both.3198130400
Short name T317
Test name
Test status
Simulation time 168195856169 ps
CPU time 387.46 seconds
Started Mar 19 12:29:15 PM PDT 24
Finished Mar 19 12:35:44 PM PDT 24
Peak memory 202152 kb
Host smart-922124a1-0612-4902-b542-2dbe35980925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198130400 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.3198130400
Directory /workspace/16.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt.1207263417
Short name T149
Test name
Test status
Simulation time 166005381794 ps
CPU time 27.42 seconds
Started Mar 19 12:29:25 PM PDT 24
Finished Mar 19 12:29:53 PM PDT 24
Peak memory 201768 kb
Host smart-8846e229-1b15-4c2a-b0f0-8e4fd26115df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207263417 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.1207263417
Directory /workspace/16.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt_fixed.1765183238
Short name T616
Test name
Test status
Simulation time 167967660183 ps
CPU time 422.09 seconds
Started Mar 19 12:29:07 PM PDT 24
Finished Mar 19 12:36:09 PM PDT 24
Peak memory 201784 kb
Host smart-fb55484b-daa7-4f01-8491-7f4fdbf26501
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765183238 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interru
pt_fixed.1765183238
Directory /workspace/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled.2644149803
Short name T781
Test name
Test status
Simulation time 324674451208 ps
CPU time 107.06 seconds
Started Mar 19 12:29:16 PM PDT 24
Finished Mar 19 12:31:04 PM PDT 24
Peak memory 201720 kb
Host smart-b6f3a33c-ec23-444c-825a-9f48b3d6f915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644149803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.2644149803
Directory /workspace/16.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled_fixed.198253599
Short name T427
Test name
Test status
Simulation time 494045229183 ps
CPU time 238.01 seconds
Started Mar 19 12:29:06 PM PDT 24
Finished Mar 19 12:33:05 PM PDT 24
Peak memory 201772 kb
Host smart-a0e717d3-7499-406f-af1d-5f0fe5c4ad1c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=198253599 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fixe
d.198253599
Directory /workspace/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup.1270519465
Short name T239
Test name
Test status
Simulation time 388185122788 ps
CPU time 918.01 seconds
Started Mar 19 12:29:12 PM PDT 24
Finished Mar 19 12:44:33 PM PDT 24
Peak memory 201804 kb
Host smart-a8f95022-89f5-45c5-8297-e5f6939eadb5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270519465 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters
_wakeup.1270519465
Directory /workspace/16.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup_fixed.1123526230
Short name T422
Test name
Test status
Simulation time 621094137218 ps
CPU time 1554.45 seconds
Started Mar 19 12:29:27 PM PDT 24
Finished Mar 19 12:55:22 PM PDT 24
Peak memory 201816 kb
Host smart-c035d222-14da-4e99-aaa3-5beab292136d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123526230 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16
.adc_ctrl_filters_wakeup_fixed.1123526230
Directory /workspace/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_fsm_reset.3628217287
Short name T636
Test name
Test status
Simulation time 66429996862 ps
CPU time 354.84 seconds
Started Mar 19 12:29:20 PM PDT 24
Finished Mar 19 12:35:16 PM PDT 24
Peak memory 202108 kb
Host smart-fb9f0fcc-8805-46f6-a2e8-d961b9b7c750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628217287 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.3628217287
Directory /workspace/16.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_lowpower_counter.500997366
Short name T658
Test name
Test status
Simulation time 38395674414 ps
CPU time 24.01 seconds
Started Mar 19 12:29:15 PM PDT 24
Finished Mar 19 12:29:41 PM PDT 24
Peak memory 201524 kb
Host smart-302d97a7-2dbc-4efc-8c17-f5bc1174077e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500997366 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.500997366
Directory /workspace/16.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_poweron_counter.383209227
Short name T742
Test name
Test status
Simulation time 3235954909 ps
CPU time 4.55 seconds
Started Mar 19 12:29:11 PM PDT 24
Finished Mar 19 12:29:17 PM PDT 24
Peak memory 201576 kb
Host smart-264d107b-fdb6-4732-b379-6da3923f9575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383209227 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.383209227
Directory /workspace/16.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_smoke.3450265587
Short name T607
Test name
Test status
Simulation time 5645327381 ps
CPU time 7.91 seconds
Started Mar 19 12:29:10 PM PDT 24
Finished Mar 19 12:29:18 PM PDT 24
Peak memory 201576 kb
Host smart-0a7bc547-b760-49da-ae59-85d48ace87a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450265587 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.3450265587
Directory /workspace/16.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.3916396247
Short name T671
Test name
Test status
Simulation time 15928781487 ps
CPU time 37.4 seconds
Started Mar 19 12:29:08 PM PDT 24
Finished Mar 19 12:29:47 PM PDT 24
Peak memory 201936 kb
Host smart-463333c6-63d9-46b4-bbf6-a812ea02a845
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916396247 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all_with_rand_reset.3916396247
Directory /workspace/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_alert_test.2216759014
Short name T349
Test name
Test status
Simulation time 323581253 ps
CPU time 1.12 seconds
Started Mar 19 12:29:28 PM PDT 24
Finished Mar 19 12:29:29 PM PDT 24
Peak memory 201472 kb
Host smart-da0b0b11-fb1b-4c8b-a7b5-e78aaa3e4af1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216759014 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.2216759014
Directory /workspace/17.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.adc_ctrl_clock_gating.1635461013
Short name T306
Test name
Test status
Simulation time 186800320851 ps
CPU time 435.86 seconds
Started Mar 19 12:29:10 PM PDT 24
Finished Mar 19 12:36:26 PM PDT 24
Peak memory 201724 kb
Host smart-a422b02b-3199-4d75-a554-16d3d0cdb830
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635461013 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gat
ing.1635461013
Directory /workspace/17.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt.4028961585
Short name T528
Test name
Test status
Simulation time 163602042635 ps
CPU time 106.36 seconds
Started Mar 19 12:29:09 PM PDT 24
Finished Mar 19 12:30:56 PM PDT 24
Peak memory 201820 kb
Host smart-8499694a-e3fe-427b-979f-95d590300a1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028961585 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.4028961585
Directory /workspace/17.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.2336360639
Short name T471
Test name
Test status
Simulation time 492068416169 ps
CPU time 1220.19 seconds
Started Mar 19 12:29:29 PM PDT 24
Finished Mar 19 12:49:49 PM PDT 24
Peak memory 201728 kb
Host smart-88e52e49-8ea2-4c64-b64b-8824cbe13fb8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336360639 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interru
pt_fixed.2336360639
Directory /workspace/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled.2079386619
Short name T181
Test name
Test status
Simulation time 168726372646 ps
CPU time 410.05 seconds
Started Mar 19 12:29:07 PM PDT 24
Finished Mar 19 12:35:58 PM PDT 24
Peak memory 201800 kb
Host smart-3cc06929-1747-4c5a-b57e-d91b3acca884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079386619 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.2079386619
Directory /workspace/17.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled_fixed.4008339878
Short name T513
Test name
Test status
Simulation time 499216958553 ps
CPU time 77.65 seconds
Started Mar 19 12:29:24 PM PDT 24
Finished Mar 19 12:30:42 PM PDT 24
Peak memory 201728 kb
Host smart-4e94c1c7-9faf-40a0-9834-d33a291b3f15
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008339878 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fix
ed.4008339878
Directory /workspace/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup_fixed.4151357917
Short name T148
Test name
Test status
Simulation time 427667528742 ps
CPU time 180.27 seconds
Started Mar 19 12:29:08 PM PDT 24
Finished Mar 19 12:32:08 PM PDT 24
Peak memory 201752 kb
Host smart-dcb908cf-6fa4-441e-9980-bde3d2d59cfd
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151357917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17
.adc_ctrl_filters_wakeup_fixed.4151357917
Directory /workspace/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_fsm_reset.1132774887
Short name T583
Test name
Test status
Simulation time 141429384960 ps
CPU time 569.15 seconds
Started Mar 19 12:29:34 PM PDT 24
Finished Mar 19 12:39:03 PM PDT 24
Peak memory 202128 kb
Host smart-ce53b903-3593-48f8-840b-374fd0f87787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132774887 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.1132774887
Directory /workspace/17.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_lowpower_counter.1908541212
Short name T428
Test name
Test status
Simulation time 41554942771 ps
CPU time 49.92 seconds
Started Mar 19 12:29:25 PM PDT 24
Finished Mar 19 12:30:15 PM PDT 24
Peak memory 201544 kb
Host smart-1c8c19f7-d975-4f33-98d0-8e01a8af792e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908541212 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.1908541212
Directory /workspace/17.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_poweron_counter.761770464
Short name T680
Test name
Test status
Simulation time 3397058583 ps
CPU time 1.6 seconds
Started Mar 19 12:29:16 PM PDT 24
Finished Mar 19 12:29:18 PM PDT 24
Peak memory 201572 kb
Host smart-4e7f4463-6f05-493c-8171-cb529bd12ae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761770464 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.761770464
Directory /workspace/17.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_smoke.826294833
Short name T517
Test name
Test status
Simulation time 5692006098 ps
CPU time 13.07 seconds
Started Mar 19 12:29:20 PM PDT 24
Finished Mar 19 12:29:34 PM PDT 24
Peak memory 201608 kb
Host smart-ecb455cb-6968-40d1-bba3-c058942947a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826294833 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.826294833
Directory /workspace/17.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.adc_ctrl_alert_test.2704585364
Short name T108
Test name
Test status
Simulation time 515264870 ps
CPU time 0.97 seconds
Started Mar 19 12:29:13 PM PDT 24
Finished Mar 19 12:29:16 PM PDT 24
Peak memory 201448 kb
Host smart-7fa32499-fb64-45dc-890c-418783f54a70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704585364 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.2704585364
Directory /workspace/18.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.adc_ctrl_clock_gating.2940212540
Short name T590
Test name
Test status
Simulation time 534864672463 ps
CPU time 518.64 seconds
Started Mar 19 12:29:13 PM PDT 24
Finished Mar 19 12:37:54 PM PDT 24
Peak memory 201584 kb
Host smart-0099ea36-4d52-4e3e-b375-9c4f6b6d6121
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940212540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gat
ing.2940212540
Directory /workspace/18.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt.3711498226
Short name T631
Test name
Test status
Simulation time 325357210307 ps
CPU time 210.73 seconds
Started Mar 19 12:29:13 PM PDT 24
Finished Mar 19 12:32:46 PM PDT 24
Peak memory 201812 kb
Host smart-b077cb72-f4ac-4844-923e-08d2edcfce15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711498226 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.3711498226
Directory /workspace/18.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled.588701816
Short name T674
Test name
Test status
Simulation time 160234509664 ps
CPU time 88.45 seconds
Started Mar 19 12:29:18 PM PDT 24
Finished Mar 19 12:30:51 PM PDT 24
Peak memory 201800 kb
Host smart-dc80e312-ce35-49c7-baee-2288616e9383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588701816 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.588701816
Directory /workspace/18.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled_fixed.3758316146
Short name T647
Test name
Test status
Simulation time 164824766643 ps
CPU time 262.12 seconds
Started Mar 19 12:29:29 PM PDT 24
Finished Mar 19 12:33:51 PM PDT 24
Peak memory 201760 kb
Host smart-3e5679ed-bc89-47e1-b77f-ef0af0d6854e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758316146 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fix
ed.3758316146
Directory /workspace/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup.2841529102
Short name T676
Test name
Test status
Simulation time 343101244982 ps
CPU time 206.61 seconds
Started Mar 19 12:29:14 PM PDT 24
Finished Mar 19 12:32:43 PM PDT 24
Peak memory 201848 kb
Host smart-705e10e9-1e8d-4413-be99-c6dae8900b1f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841529102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters
_wakeup.2841529102
Directory /workspace/18.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.1224763724
Short name T400
Test name
Test status
Simulation time 612145355988 ps
CPU time 382.77 seconds
Started Mar 19 12:29:10 PM PDT 24
Finished Mar 19 12:35:33 PM PDT 24
Peak memory 201768 kb
Host smart-4b264028-28c4-4958-8d7b-f39359564641
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224763724 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18
.adc_ctrl_filters_wakeup_fixed.1224763724
Directory /workspace/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_fsm_reset.896395294
Short name T50
Test name
Test status
Simulation time 105958007351 ps
CPU time 346.5 seconds
Started Mar 19 12:29:05 PM PDT 24
Finished Mar 19 12:34:52 PM PDT 24
Peak memory 202240 kb
Host smart-42c3f675-4a7c-41f7-b7a0-93667bddfbf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896395294 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.896395294
Directory /workspace/18.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_lowpower_counter.2529687992
Short name T789
Test name
Test status
Simulation time 33487189089 ps
CPU time 35.27 seconds
Started Mar 19 12:29:09 PM PDT 24
Finished Mar 19 12:29:45 PM PDT 24
Peak memory 201572 kb
Host smart-362bbaf8-429f-4f6e-b176-a131cee5df10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529687992 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.2529687992
Directory /workspace/18.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_poweron_counter.3317183527
Short name T741
Test name
Test status
Simulation time 3459634981 ps
CPU time 2.66 seconds
Started Mar 19 12:29:17 PM PDT 24
Finished Mar 19 12:29:21 PM PDT 24
Peak memory 201568 kb
Host smart-914c23e0-21ee-450e-beae-2ea1bfe9ef89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317183527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.3317183527
Directory /workspace/18.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_smoke.2806888183
Short name T581
Test name
Test status
Simulation time 6020205221 ps
CPU time 4.49 seconds
Started Mar 19 12:29:34 PM PDT 24
Finished Mar 19 12:29:38 PM PDT 24
Peak memory 201664 kb
Host smart-c89a618a-c11c-4c1b-876d-f0faef6a54e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806888183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.2806888183
Directory /workspace/18.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all.3957021738
Short name T201
Test name
Test status
Simulation time 186522604029 ps
CPU time 72.74 seconds
Started Mar 19 12:29:06 PM PDT 24
Finished Mar 19 12:30:20 PM PDT 24
Peak memory 201728 kb
Host smart-b07339c0-a882-4e56-8eca-b4c8605cab86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957021738 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all
.3957021738
Directory /workspace/18.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.997318080
Short name T93
Test name
Test status
Simulation time 108079413186 ps
CPU time 293.04 seconds
Started Mar 19 12:29:06 PM PDT 24
Finished Mar 19 12:34:00 PM PDT 24
Peak memory 217836 kb
Host smart-4b6588bf-77f1-46f6-bda8-3d6e4b78a970
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997318080 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all_with_rand_reset.997318080
Directory /workspace/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_alert_test.3171960610
Short name T657
Test name
Test status
Simulation time 350336774 ps
CPU time 1.39 seconds
Started Mar 19 12:29:07 PM PDT 24
Finished Mar 19 12:29:09 PM PDT 24
Peak memory 201460 kb
Host smart-2b989981-7ae9-4109-a54c-12becd6408bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171960610 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.3171960610
Directory /workspace/19.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.adc_ctrl_clock_gating.3973393212
Short name T678
Test name
Test status
Simulation time 183764129579 ps
CPU time 377.7 seconds
Started Mar 19 12:29:29 PM PDT 24
Finished Mar 19 12:35:47 PM PDT 24
Peak memory 201748 kb
Host smart-a6676afb-086b-4c01-85be-a6e0a9174e55
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973393212 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gat
ing.3973393212
Directory /workspace/19.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_both.4035838901
Short name T331
Test name
Test status
Simulation time 333707148418 ps
CPU time 724.94 seconds
Started Mar 19 12:29:34 PM PDT 24
Finished Mar 19 12:41:39 PM PDT 24
Peak memory 201732 kb
Host smart-cb63795d-ceb5-4ff3-b83b-ed064bd19682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035838901 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.4035838901
Directory /workspace/19.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt_fixed.835956501
Short name T514
Test name
Test status
Simulation time 322845195746 ps
CPU time 185.04 seconds
Started Mar 19 12:29:18 PM PDT 24
Finished Mar 19 12:32:23 PM PDT 24
Peak memory 201736 kb
Host smart-aa5ca01c-c1c4-48b1-9dab-3ebb3c42225a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=835956501 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrup
t_fixed.835956501
Directory /workspace/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled.2644209919
Short name T539
Test name
Test status
Simulation time 495356611698 ps
CPU time 497.34 seconds
Started Mar 19 12:29:29 PM PDT 24
Finished Mar 19 12:37:47 PM PDT 24
Peak memory 201856 kb
Host smart-80b19624-4844-4ce8-86d6-eedce00b7119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644209919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.2644209919
Directory /workspace/19.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled_fixed.414023681
Short name T394
Test name
Test status
Simulation time 491669644354 ps
CPU time 299.11 seconds
Started Mar 19 12:29:10 PM PDT 24
Finished Mar 19 12:34:10 PM PDT 24
Peak memory 201792 kb
Host smart-98faa236-b78e-433f-ac08-567fc02ec378
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=414023681 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fixe
d.414023681
Directory /workspace/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup.2216095257
Short name T274
Test name
Test status
Simulation time 381730258949 ps
CPU time 587.73 seconds
Started Mar 19 12:29:17 PM PDT 24
Finished Mar 19 12:39:05 PM PDT 24
Peak memory 201828 kb
Host smart-8095cf77-6f29-423b-b6b0-d16ee2beb784
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216095257 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters
_wakeup.2216095257
Directory /workspace/19.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup_fixed.4181085165
Short name T531
Test name
Test status
Simulation time 402372269335 ps
CPU time 166.11 seconds
Started Mar 19 12:29:22 PM PDT 24
Finished Mar 19 12:32:14 PM PDT 24
Peak memory 201808 kb
Host smart-818719ad-decb-4740-b89f-2c8baa4cd55d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181085165 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19
.adc_ctrl_filters_wakeup_fixed.4181085165
Directory /workspace/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_fsm_reset.1367811233
Short name T612
Test name
Test status
Simulation time 119563403662 ps
CPU time 612.33 seconds
Started Mar 19 12:29:09 PM PDT 24
Finished Mar 19 12:39:21 PM PDT 24
Peak memory 202044 kb
Host smart-f59aa247-9291-46fd-bc25-c17d76a2d4d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367811233 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.1367811233
Directory /workspace/19.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_lowpower_counter.1502073273
Short name T577
Test name
Test status
Simulation time 24485321463 ps
CPU time 8.86 seconds
Started Mar 19 12:29:27 PM PDT 24
Finished Mar 19 12:29:35 PM PDT 24
Peak memory 201568 kb
Host smart-bae0ac2a-f937-4c3c-94bb-80617562a34a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502073273 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.1502073273
Directory /workspace/19.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_poweron_counter.791587376
Short name T644
Test name
Test status
Simulation time 4198805858 ps
CPU time 10.45 seconds
Started Mar 19 12:29:15 PM PDT 24
Finished Mar 19 12:29:27 PM PDT 24
Peak memory 201560 kb
Host smart-59bfa97f-eb6b-4c04-ad58-9ce286aa2cb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791587376 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.791587376
Directory /workspace/19.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_smoke.2633732747
Short name T532
Test name
Test status
Simulation time 5838989780 ps
CPU time 7.87 seconds
Started Mar 19 12:29:23 PM PDT 24
Finished Mar 19 12:29:31 PM PDT 24
Peak memory 201576 kb
Host smart-4c93d56e-dc35-4657-8e02-a1b83c23550f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633732747 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.2633732747
Directory /workspace/19.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all.151519221
Short name T342
Test name
Test status
Simulation time 488473665139 ps
CPU time 1506.92 seconds
Started Mar 19 12:29:27 PM PDT 24
Finished Mar 19 12:54:34 PM PDT 24
Peak memory 210304 kb
Host smart-232ba1b1-aad5-4706-bf07-84f2be65c7a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151519221 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all.
151519221
Directory /workspace/19.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.1711146589
Short name T41
Test name
Test status
Simulation time 49243946123 ps
CPU time 56 seconds
Started Mar 19 12:29:10 PM PDT 24
Finished Mar 19 12:30:06 PM PDT 24
Peak memory 210380 kb
Host smart-829abe88-b921-4bac-b99d-e1fe8be9f78b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711146589 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all_with_rand_reset.1711146589
Directory /workspace/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_alert_test.4180847895
Short name T767
Test name
Test status
Simulation time 428475057 ps
CPU time 1.56 seconds
Started Mar 19 12:28:53 PM PDT 24
Finished Mar 19 12:28:55 PM PDT 24
Peak memory 201460 kb
Host smart-9357556a-5e80-4c69-bc57-0f94f8494cf3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180847895 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.4180847895
Directory /workspace/2.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.adc_ctrl_clock_gating.1660540752
Short name T677
Test name
Test status
Simulation time 573334969328 ps
CPU time 124.52 seconds
Started Mar 19 12:28:47 PM PDT 24
Finished Mar 19 12:30:52 PM PDT 24
Peak memory 201720 kb
Host smart-c522bd7c-efd1-4e85-982d-bf03809b981a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660540752 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gati
ng.1660540752
Directory /workspace/2.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt.2897276376
Short name T255
Test name
Test status
Simulation time 486211115447 ps
CPU time 1148.83 seconds
Started Mar 19 12:28:33 PM PDT 24
Finished Mar 19 12:47:43 PM PDT 24
Peak memory 201804 kb
Host smart-322c90c0-6535-4c15-8f61-85cc788a4a1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897276376 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.2897276376
Directory /workspace/2.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt_fixed.112491579
Short name T527
Test name
Test status
Simulation time 161133172464 ps
CPU time 347.37 seconds
Started Mar 19 12:28:50 PM PDT 24
Finished Mar 19 12:34:38 PM PDT 24
Peak memory 201780 kb
Host smart-d83ec009-d456-49f1-89b0-b74282135c77
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=112491579 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt
_fixed.112491579
Directory /workspace/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled.3655049494
Short name T13
Test name
Test status
Simulation time 165627816639 ps
CPU time 354.22 seconds
Started Mar 19 12:28:38 PM PDT 24
Finished Mar 19 12:34:33 PM PDT 24
Peak memory 201728 kb
Host smart-f15fef0d-fd72-4f5a-b897-7a10ea10985c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655049494 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.3655049494
Directory /workspace/2.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled_fixed.4029820879
Short name T351
Test name
Test status
Simulation time 164103535396 ps
CPU time 397.21 seconds
Started Mar 19 12:28:45 PM PDT 24
Finished Mar 19 12:35:23 PM PDT 24
Peak memory 201716 kb
Host smart-047d1e60-ac09-4c6b-aea6-71774a19bbb5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029820879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixe
d.4029820879
Directory /workspace/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup.230477137
Short name T509
Test name
Test status
Simulation time 180023207323 ps
CPU time 83.31 seconds
Started Mar 19 12:28:49 PM PDT 24
Finished Mar 19 12:30:13 PM PDT 24
Peak memory 201804 kb
Host smart-55b3296c-6ee1-4343-b20a-a097fcf6be2b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230477137 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_w
akeup.230477137
Directory /workspace/2.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup_fixed.1463073436
Short name T542
Test name
Test status
Simulation time 612360152228 ps
CPU time 391.92 seconds
Started Mar 19 12:28:46 PM PDT 24
Finished Mar 19 12:35:18 PM PDT 24
Peak memory 201844 kb
Host smart-18842fdb-2023-40bd-a88e-eb1fb8d4934a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463073436 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.
adc_ctrl_filters_wakeup_fixed.1463073436
Directory /workspace/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_fsm_reset.497485591
Short name T344
Test name
Test status
Simulation time 141668554130 ps
CPU time 749.27 seconds
Started Mar 19 12:28:34 PM PDT 24
Finished Mar 19 12:41:04 PM PDT 24
Peak memory 202076 kb
Host smart-854b1aab-1458-4042-a79d-4a9cc6dffae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497485591 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.497485591
Directory /workspace/2.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_lowpower_counter.1492830057
Short name T393
Test name
Test status
Simulation time 23108906147 ps
CPU time 13.6 seconds
Started Mar 19 12:28:45 PM PDT 24
Finished Mar 19 12:28:59 PM PDT 24
Peak memory 201556 kb
Host smart-2d6d2453-7a28-426f-9745-b291d852d942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492830057 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.1492830057
Directory /workspace/2.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_poweron_counter.2271041083
Short name T138
Test name
Test status
Simulation time 4610926798 ps
CPU time 6.22 seconds
Started Mar 19 12:28:31 PM PDT 24
Finished Mar 19 12:28:37 PM PDT 24
Peak memory 201548 kb
Host smart-f162aaa2-e8a9-4769-98d6-0afc69b42cd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271041083 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.2271041083
Directory /workspace/2.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_sec_cm.1281556805
Short name T67
Test name
Test status
Simulation time 8435694540 ps
CPU time 6.08 seconds
Started Mar 19 12:28:44 PM PDT 24
Finished Mar 19 12:28:50 PM PDT 24
Peak memory 218420 kb
Host smart-53cd5a1c-4b45-4b28-9224-ffa3bd7c382b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281556805 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.1281556805
Directory /workspace/2.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.adc_ctrl_smoke.2917122409
Short name T442
Test name
Test status
Simulation time 6089153871 ps
CPU time 4.14 seconds
Started Mar 19 12:28:42 PM PDT 24
Finished Mar 19 12:28:47 PM PDT 24
Peak memory 201568 kb
Host smart-b7a92152-5474-4b16-bb0e-dc5e3f1e5866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917122409 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.2917122409
Directory /workspace/2.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.809311498
Short name T284
Test name
Test status
Simulation time 69458028647 ps
CPU time 105.47 seconds
Started Mar 19 12:28:54 PM PDT 24
Finished Mar 19 12:30:40 PM PDT 24
Peak memory 210452 kb
Host smart-5dc5e6cb-e5a9-4c20-91c8-f108dc50c393
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809311498 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all_with_rand_reset.809311498
Directory /workspace/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_alert_test.4168847335
Short name T389
Test name
Test status
Simulation time 479165004 ps
CPU time 0.88 seconds
Started Mar 19 12:29:24 PM PDT 24
Finished Mar 19 12:29:25 PM PDT 24
Peak memory 201432 kb
Host smart-de10cbd0-de03-4843-9390-563e31dc817b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168847335 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.4168847335
Directory /workspace/20.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.adc_ctrl_clock_gating.4188988446
Short name T327
Test name
Test status
Simulation time 166620313151 ps
CPU time 103.36 seconds
Started Mar 19 12:29:24 PM PDT 24
Finished Mar 19 12:31:08 PM PDT 24
Peak memory 201764 kb
Host smart-996a3c0d-ecee-4a3c-944a-5f869bfa3e2d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188988446 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gat
ing.4188988446
Directory /workspace/20.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt.3600052331
Short name T287
Test name
Test status
Simulation time 162029448592 ps
CPU time 90.65 seconds
Started Mar 19 12:29:25 PM PDT 24
Finished Mar 19 12:30:55 PM PDT 24
Peak memory 201812 kb
Host smart-a372f811-17e5-42d3-809e-6be094174a4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600052331 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.3600052331
Directory /workspace/20.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt_fixed.1930169417
Short name T696
Test name
Test status
Simulation time 495306194876 ps
CPU time 646.87 seconds
Started Mar 19 12:29:11 PM PDT 24
Finished Mar 19 12:39:59 PM PDT 24
Peak memory 201728 kb
Host smart-c96916e0-398a-490a-a0eb-ea2a35ef9f32
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930169417 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interru
pt_fixed.1930169417
Directory /workspace/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled.3420393663
Short name T712
Test name
Test status
Simulation time 168891311022 ps
CPU time 188.39 seconds
Started Mar 19 12:29:08 PM PDT 24
Finished Mar 19 12:32:17 PM PDT 24
Peak memory 201732 kb
Host smart-64577924-5dee-4136-842b-15cd637ca4b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420393663 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.3420393663
Directory /workspace/20.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled_fixed.3424887725
Short name T406
Test name
Test status
Simulation time 331165847804 ps
CPU time 196.54 seconds
Started Mar 19 12:29:07 PM PDT 24
Finished Mar 19 12:32:24 PM PDT 24
Peak memory 201816 kb
Host smart-02e2c021-92fe-4968-9e12-959533932ef9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424887725 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fix
ed.3424887725
Directory /workspace/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup_fixed.2570561988
Short name T453
Test name
Test status
Simulation time 203811626280 ps
CPU time 503.49 seconds
Started Mar 19 12:29:18 PM PDT 24
Finished Mar 19 12:37:41 PM PDT 24
Peak memory 201744 kb
Host smart-b81c563f-5618-4659-ad59-ae01e79b44a7
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570561988 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20
.adc_ctrl_filters_wakeup_fixed.2570561988
Directory /workspace/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_fsm_reset.2547816450
Short name T723
Test name
Test status
Simulation time 115294385094 ps
CPU time 448.37 seconds
Started Mar 19 12:29:27 PM PDT 24
Finished Mar 19 12:36:55 PM PDT 24
Peak memory 202112 kb
Host smart-fdbdbd71-9cc0-4f60-8351-8ab9802d396d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547816450 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.2547816450
Directory /workspace/20.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_lowpower_counter.1091884577
Short name T507
Test name
Test status
Simulation time 23486026837 ps
CPU time 22.6 seconds
Started Mar 19 12:29:32 PM PDT 24
Finished Mar 19 12:29:54 PM PDT 24
Peak memory 201568 kb
Host smart-52d27e98-36e2-402f-a897-db676c3a472b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091884577 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.1091884577
Directory /workspace/20.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_poweron_counter.3442322077
Short name T379
Test name
Test status
Simulation time 4979639249 ps
CPU time 6.15 seconds
Started Mar 19 12:29:06 PM PDT 24
Finished Mar 19 12:29:13 PM PDT 24
Peak memory 201700 kb
Host smart-b64c177c-7b81-46ec-804b-09aef89fe083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442322077 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.3442322077
Directory /workspace/20.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_smoke.3010239967
Short name T412
Test name
Test status
Simulation time 5750194461 ps
CPU time 14.55 seconds
Started Mar 19 12:29:08 PM PDT 24
Finished Mar 19 12:29:23 PM PDT 24
Peak memory 201544 kb
Host smart-c389906f-60f9-48c8-910e-549de3910592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010239967 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.3010239967
Directory /workspace/20.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all.1606426104
Short name T775
Test name
Test status
Simulation time 284122535399 ps
CPU time 688.09 seconds
Started Mar 19 12:29:28 PM PDT 24
Finished Mar 19 12:40:56 PM PDT 24
Peak memory 202112 kb
Host smart-e9d57f24-3af5-4d67-8f16-0ce1988b5a90
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606426104 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all
.1606426104
Directory /workspace/20.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.adc_ctrl_alert_test.1455345290
Short name T592
Test name
Test status
Simulation time 501618481 ps
CPU time 1.75 seconds
Started Mar 19 12:29:16 PM PDT 24
Finished Mar 19 12:29:19 PM PDT 24
Peak memory 201448 kb
Host smart-6746e8db-b3ea-4541-8766-23da07292255
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455345290 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.1455345290
Directory /workspace/21.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_both.306801287
Short name T534
Test name
Test status
Simulation time 327495546676 ps
CPU time 718.94 seconds
Started Mar 19 12:29:27 PM PDT 24
Finished Mar 19 12:41:26 PM PDT 24
Peak memory 201736 kb
Host smart-324ed3ef-4b06-40b1-a0f3-ad3f4d488c5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306801287 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.306801287
Directory /workspace/21.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt.850307680
Short name T618
Test name
Test status
Simulation time 165316670149 ps
CPU time 393.76 seconds
Started Mar 19 12:29:36 PM PDT 24
Finished Mar 19 12:36:09 PM PDT 24
Peak memory 201828 kb
Host smart-b65a09b6-627a-4dd0-baf0-866b8c6bc0a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850307680 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.850307680
Directory /workspace/21.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt_fixed.2506804723
Short name T753
Test name
Test status
Simulation time 334219637533 ps
CPU time 381.14 seconds
Started Mar 19 12:29:35 PM PDT 24
Finished Mar 19 12:35:57 PM PDT 24
Peak memory 201732 kb
Host smart-a79fee34-621c-4f9f-ad31-4e167620a9c6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506804723 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interru
pt_fixed.2506804723
Directory /workspace/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled.661468467
Short name T659
Test name
Test status
Simulation time 159750434090 ps
CPU time 400.45 seconds
Started Mar 19 12:29:06 PM PDT 24
Finished Mar 19 12:35:46 PM PDT 24
Peak memory 201704 kb
Host smart-494ac00a-1f45-4f6b-8360-a59e42cff9b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661468467 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.661468467
Directory /workspace/21.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled_fixed.2141012847
Short name T436
Test name
Test status
Simulation time 327160732695 ps
CPU time 809.17 seconds
Started Mar 19 12:29:16 PM PDT 24
Finished Mar 19 12:42:46 PM PDT 24
Peak memory 201752 kb
Host smart-04ee4cbe-38da-41ce-a0c3-550b71613982
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141012847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fix
ed.2141012847
Directory /workspace/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup_fixed.3999496719
Short name T402
Test name
Test status
Simulation time 399467765640 ps
CPU time 462.12 seconds
Started Mar 19 12:29:08 PM PDT 24
Finished Mar 19 12:36:51 PM PDT 24
Peak memory 201740 kb
Host smart-222a3743-1604-4990-a7c7-50e9725d1338
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999496719 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21
.adc_ctrl_filters_wakeup_fixed.3999496719
Directory /workspace/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_lowpower_counter.2138622664
Short name T536
Test name
Test status
Simulation time 42900960454 ps
CPU time 102.25 seconds
Started Mar 19 12:29:23 PM PDT 24
Finished Mar 19 12:31:05 PM PDT 24
Peak memory 201556 kb
Host smart-1ee1ccb4-a611-4b54-8566-7c5c64a9e077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138622664 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.2138622664
Directory /workspace/21.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_poweron_counter.2038131518
Short name T519
Test name
Test status
Simulation time 3605423806 ps
CPU time 9.26 seconds
Started Mar 19 12:29:32 PM PDT 24
Finished Mar 19 12:29:42 PM PDT 24
Peak memory 201544 kb
Host smart-d1a049d5-6e20-4c5f-947d-1e8cf0e3dc9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038131518 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.2038131518
Directory /workspace/21.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_smoke.612379463
Short name T754
Test name
Test status
Simulation time 5714027184 ps
CPU time 14.42 seconds
Started Mar 19 12:29:21 PM PDT 24
Finished Mar 19 12:29:35 PM PDT 24
Peak memory 201548 kb
Host smart-645e859b-bb09-4a00-875e-a4fc3062d4df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612379463 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.612379463
Directory /workspace/21.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.1791421085
Short name T33
Test name
Test status
Simulation time 34784650889 ps
CPU time 71.71 seconds
Started Mar 19 12:29:34 PM PDT 24
Finished Mar 19 12:30:46 PM PDT 24
Peak memory 210088 kb
Host smart-fb59b523-4305-419c-9ceb-828f31b77b92
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791421085 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all_with_rand_reset.1791421085
Directory /workspace/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_alert_test.1316688665
Short name T620
Test name
Test status
Simulation time 435502211 ps
CPU time 1.65 seconds
Started Mar 19 12:29:06 PM PDT 24
Finished Mar 19 12:29:08 PM PDT 24
Peak memory 201576 kb
Host smart-ec6249e6-5626-4bc2-9918-2fe22fd108cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316688665 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.1316688665
Directory /workspace/22.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.adc_ctrl_clock_gating.2986559720
Short name T300
Test name
Test status
Simulation time 170087814852 ps
CPU time 107.23 seconds
Started Mar 19 12:29:07 PM PDT 24
Finished Mar 19 12:30:54 PM PDT 24
Peak memory 201732 kb
Host smart-c6ec5ee7-d55a-4321-a6d4-3b5c13481a8b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986559720 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gat
ing.2986559720
Directory /workspace/22.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt.3967620387
Short name T706
Test name
Test status
Simulation time 330555494760 ps
CPU time 313.83 seconds
Started Mar 19 12:29:22 PM PDT 24
Finished Mar 19 12:34:36 PM PDT 24
Peak memory 201756 kb
Host smart-5b604f09-35e3-4b25-adee-25ce93798307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967620387 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.3967620387
Directory /workspace/22.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt_fixed.2567575135
Short name T388
Test name
Test status
Simulation time 331171932156 ps
CPU time 190.73 seconds
Started Mar 19 12:29:22 PM PDT 24
Finished Mar 19 12:32:33 PM PDT 24
Peak memory 201740 kb
Host smart-118877eb-07ce-4485-bf52-d4950eee33cd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567575135 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interru
pt_fixed.2567575135
Directory /workspace/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled.53665427
Short name T726
Test name
Test status
Simulation time 159361142402 ps
CPU time 91.69 seconds
Started Mar 19 12:29:33 PM PDT 24
Finished Mar 19 12:31:05 PM PDT 24
Peak memory 201752 kb
Host smart-d39a9466-bb1f-4756-978e-b6bff9ed195d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53665427 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.53665427
Directory /workspace/22.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled_fixed.1630762678
Short name T490
Test name
Test status
Simulation time 496733709048 ps
CPU time 1072.8 seconds
Started Mar 19 12:29:31 PM PDT 24
Finished Mar 19 12:47:24 PM PDT 24
Peak memory 201756 kb
Host smart-d35621f2-6562-4e36-a045-085a7ba589bf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630762678 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fix
ed.1630762678
Directory /workspace/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup.4275086607
Short name T655
Test name
Test status
Simulation time 362946521363 ps
CPU time 100.16 seconds
Started Mar 19 12:29:41 PM PDT 24
Finished Mar 19 12:31:22 PM PDT 24
Peak memory 201828 kb
Host smart-be523d70-1e10-41e4-8ebf-06c402d0a3bf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275086607 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters
_wakeup.4275086607
Directory /workspace/22.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup_fixed.2839534826
Short name T376
Test name
Test status
Simulation time 407735768301 ps
CPU time 238.03 seconds
Started Mar 19 12:29:42 PM PDT 24
Finished Mar 19 12:33:40 PM PDT 24
Peak memory 201756 kb
Host smart-da625e75-007f-45b5-8a6b-d0e216d593ce
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839534826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22
.adc_ctrl_filters_wakeup_fixed.2839534826
Directory /workspace/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_fsm_reset.3808028385
Short name T512
Test name
Test status
Simulation time 99888278356 ps
CPU time 520.81 seconds
Started Mar 19 12:29:18 PM PDT 24
Finished Mar 19 12:37:59 PM PDT 24
Peak memory 202128 kb
Host smart-5998eb6f-9443-4ddc-8cdc-b8dd3c8b3f2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808028385 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.3808028385
Directory /workspace/22.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_lowpower_counter.1101593007
Short name T476
Test name
Test status
Simulation time 37892170874 ps
CPU time 84.73 seconds
Started Mar 19 12:29:17 PM PDT 24
Finished Mar 19 12:30:42 PM PDT 24
Peak memory 201572 kb
Host smart-5a9e9859-f0ef-4c55-b005-3a4f84cea173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101593007 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.1101593007
Directory /workspace/22.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_poweron_counter.3089322175
Short name T1
Test name
Test status
Simulation time 5332457215 ps
CPU time 4.11 seconds
Started Mar 19 12:29:38 PM PDT 24
Finished Mar 19 12:29:43 PM PDT 24
Peak memory 201568 kb
Host smart-bb78ae34-1b48-40cd-a64e-4d2841024602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089322175 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.3089322175
Directory /workspace/22.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_smoke.2808807443
Short name T750
Test name
Test status
Simulation time 5870128005 ps
CPU time 14.37 seconds
Started Mar 19 12:29:33 PM PDT 24
Finished Mar 19 12:29:47 PM PDT 24
Peak memory 201584 kb
Host smart-f0e2aa83-f5d4-4905-b541-b2cc742ab6a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808807443 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.2808807443
Directory /workspace/22.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.3228715463
Short name T16
Test name
Test status
Simulation time 171941012253 ps
CPU time 150.64 seconds
Started Mar 19 12:29:08 PM PDT 24
Finished Mar 19 12:31:39 PM PDT 24
Peak memory 210500 kb
Host smart-4527ac5e-b131-4d8d-8339-d8791f7d809d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228715463 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all_with_rand_reset.3228715463
Directory /workspace/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_alert_test.168606877
Short name T572
Test name
Test status
Simulation time 493157592 ps
CPU time 0.88 seconds
Started Mar 19 12:29:34 PM PDT 24
Finished Mar 19 12:29:35 PM PDT 24
Peak memory 201424 kb
Host smart-8b199373-50f7-4772-ae0c-c3edb918d520
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168606877 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.168606877
Directory /workspace/23.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.adc_ctrl_clock_gating.2640800542
Short name T179
Test name
Test status
Simulation time 352834974339 ps
CPU time 197.46 seconds
Started Mar 19 12:29:10 PM PDT 24
Finished Mar 19 12:32:28 PM PDT 24
Peak memory 201780 kb
Host smart-18346db0-1030-4bc2-acc9-3e3b73e69618
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640800542 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gat
ing.2640800542
Directory /workspace/23.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt.2650570690
Short name T489
Test name
Test status
Simulation time 330362324895 ps
CPU time 824.79 seconds
Started Mar 19 12:29:22 PM PDT 24
Finished Mar 19 12:43:07 PM PDT 24
Peak memory 201752 kb
Host smart-02632e26-be66-4a71-b53c-61c4ff1ff383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650570690 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.2650570690
Directory /workspace/23.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt_fixed.1271525246
Short name T614
Test name
Test status
Simulation time 162530376560 ps
CPU time 395.04 seconds
Started Mar 19 12:29:20 PM PDT 24
Finished Mar 19 12:35:55 PM PDT 24
Peak memory 201800 kb
Host smart-53a6e076-8ada-4fe9-905a-ebba8a98214d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271525246 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interru
pt_fixed.1271525246
Directory /workspace/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled.3322872288
Short name T141
Test name
Test status
Simulation time 336175102534 ps
CPU time 409.8 seconds
Started Mar 19 12:29:30 PM PDT 24
Finished Mar 19 12:36:20 PM PDT 24
Peak memory 201860 kb
Host smart-72c6413a-cf53-404c-ac0f-b06d830d6450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322872288 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.3322872288
Directory /workspace/23.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled_fixed.4175829348
Short name T613
Test name
Test status
Simulation time 495291892019 ps
CPU time 300.76 seconds
Started Mar 19 12:29:36 PM PDT 24
Finished Mar 19 12:34:37 PM PDT 24
Peak memory 201816 kb
Host smart-09dfc4d3-ee62-477f-8e39-10c06857d57b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175829348 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fix
ed.4175829348
Directory /workspace/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup.3905818671
Short name T504
Test name
Test status
Simulation time 165902165452 ps
CPU time 99.94 seconds
Started Mar 19 12:29:07 PM PDT 24
Finished Mar 19 12:30:48 PM PDT 24
Peak memory 201756 kb
Host smart-55ff3ee5-081e-402e-a5ab-c698121ea997
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905818671 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters
_wakeup.3905818671
Directory /workspace/23.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup_fixed.1393137049
Short name T523
Test name
Test status
Simulation time 598240143802 ps
CPU time 356.81 seconds
Started Mar 19 12:29:18 PM PDT 24
Finished Mar 19 12:35:15 PM PDT 24
Peak memory 201884 kb
Host smart-3660f347-47ed-449f-8442-060da28d41fb
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393137049 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23
.adc_ctrl_filters_wakeup_fixed.1393137049
Directory /workspace/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_fsm_reset.2513877328
Short name T589
Test name
Test status
Simulation time 148557484026 ps
CPU time 742.96 seconds
Started Mar 19 12:29:38 PM PDT 24
Finished Mar 19 12:42:01 PM PDT 24
Peak memory 202168 kb
Host smart-df37c5e3-abbd-438a-9d3c-66337fd3a3b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513877328 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.2513877328
Directory /workspace/23.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_lowpower_counter.2339741929
Short name T672
Test name
Test status
Simulation time 26618772410 ps
CPU time 50.39 seconds
Started Mar 19 12:29:38 PM PDT 24
Finished Mar 19 12:30:28 PM PDT 24
Peak memory 201588 kb
Host smart-3a7867aa-a10d-4c5d-94cb-19d079890d0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339741929 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.2339741929
Directory /workspace/23.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_poweron_counter.2957449037
Short name T385
Test name
Test status
Simulation time 5293793610 ps
CPU time 11.55 seconds
Started Mar 19 12:29:16 PM PDT 24
Finished Mar 19 12:29:28 PM PDT 24
Peak memory 201592 kb
Host smart-ff8504c1-4896-4291-a347-76aec03196a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957449037 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.2957449037
Directory /workspace/23.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_smoke.2854985221
Short name T729
Test name
Test status
Simulation time 5760573794 ps
CPU time 4.37 seconds
Started Mar 19 12:29:16 PM PDT 24
Finished Mar 19 12:29:21 PM PDT 24
Peak memory 201560 kb
Host smart-2a7e50dd-4368-4bbe-bf65-d4bf6292f2be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854985221 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.2854985221
Directory /workspace/23.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all.281728285
Short name T664
Test name
Test status
Simulation time 380732178084 ps
CPU time 272.85 seconds
Started Mar 19 12:29:38 PM PDT 24
Finished Mar 19 12:34:11 PM PDT 24
Peak memory 201756 kb
Host smart-ecf43c94-7193-4a22-8998-1b70af111720
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281728285 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all.
281728285
Directory /workspace/23.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.adc_ctrl_alert_test.1182001991
Short name T558
Test name
Test status
Simulation time 449400779 ps
CPU time 0.91 seconds
Started Mar 19 12:29:31 PM PDT 24
Finished Mar 19 12:29:32 PM PDT 24
Peak memory 201460 kb
Host smart-564f1c21-2aa9-43ca-8777-65f9e78384fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182001991 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.1182001991
Directory /workspace/24.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt.152120796
Short name T151
Test name
Test status
Simulation time 164396067653 ps
CPU time 363.91 seconds
Started Mar 19 12:29:22 PM PDT 24
Finished Mar 19 12:35:26 PM PDT 24
Peak memory 201892 kb
Host smart-0fa48476-600b-4b52-8dee-6d6c32a93b9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152120796 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.152120796
Directory /workspace/24.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt_fixed.918890183
Short name T481
Test name
Test status
Simulation time 500421674734 ps
CPU time 1128.99 seconds
Started Mar 19 12:29:34 PM PDT 24
Finished Mar 19 12:48:23 PM PDT 24
Peak memory 201804 kb
Host smart-cf6e1a49-0a81-4976-9537-c26df668d696
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=918890183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrup
t_fixed.918890183
Directory /workspace/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled.4208649761
Short name T198
Test name
Test status
Simulation time 325593922194 ps
CPU time 353.44 seconds
Started Mar 19 12:29:34 PM PDT 24
Finished Mar 19 12:35:28 PM PDT 24
Peak memory 201836 kb
Host smart-541fc5e0-0ca0-4704-a7ac-a5e3b184a60e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208649761 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.4208649761
Directory /workspace/24.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.1123705643
Short name T110
Test name
Test status
Simulation time 163688108187 ps
CPU time 361.38 seconds
Started Mar 19 12:29:39 PM PDT 24
Finished Mar 19 12:35:41 PM PDT 24
Peak memory 201724 kb
Host smart-9fb6efa0-e83c-44f8-ab0f-7dd6c486adef
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123705643 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fix
ed.1123705643
Directory /workspace/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup.2565856990
Short name T35
Test name
Test status
Simulation time 392582567916 ps
CPU time 946.53 seconds
Started Mar 19 12:29:39 PM PDT 24
Finished Mar 19 12:45:26 PM PDT 24
Peak memory 201828 kb
Host smart-b2882be4-4d64-46ff-a7af-121d13cc850c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565856990 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters
_wakeup.2565856990
Directory /workspace/24.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup_fixed.2859881876
Short name T483
Test name
Test status
Simulation time 200626780543 ps
CPU time 123.43 seconds
Started Mar 19 12:29:37 PM PDT 24
Finished Mar 19 12:31:40 PM PDT 24
Peak memory 201764 kb
Host smart-07f60d1d-2ebb-475e-be34-ac36942f0366
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859881876 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24
.adc_ctrl_filters_wakeup_fixed.2859881876
Directory /workspace/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_fsm_reset.965038977
Short name T488
Test name
Test status
Simulation time 125396739500 ps
CPU time 672.9 seconds
Started Mar 19 12:30:04 PM PDT 24
Finished Mar 19 12:41:17 PM PDT 24
Peak memory 202100 kb
Host smart-3c384d5e-5ed0-41c4-9c7c-86711943590d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965038977 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.965038977
Directory /workspace/24.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_lowpower_counter.1981524613
Short name T639
Test name
Test status
Simulation time 32569443196 ps
CPU time 77.96 seconds
Started Mar 19 12:29:16 PM PDT 24
Finished Mar 19 12:30:35 PM PDT 24
Peak memory 201568 kb
Host smart-ab31d3da-9be2-4912-80c3-5354834a623b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981524613 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.1981524613
Directory /workspace/24.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_poweron_counter.3085010985
Short name T435
Test name
Test status
Simulation time 3094180074 ps
CPU time 4.14 seconds
Started Mar 19 12:29:39 PM PDT 24
Finished Mar 19 12:29:43 PM PDT 24
Peak memory 201604 kb
Host smart-71619a30-a782-4d42-9007-0edb7e34d266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085010985 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.3085010985
Directory /workspace/24.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_smoke.809945963
Short name T484
Test name
Test status
Simulation time 5789299794 ps
CPU time 13.89 seconds
Started Mar 19 12:29:33 PM PDT 24
Finished Mar 19 12:29:47 PM PDT 24
Peak memory 201596 kb
Host smart-e2fb87e7-ab9d-44ab-956b-a07514e735ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809945963 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.809945963
Directory /workspace/24.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all.1347655819
Short name T649
Test name
Test status
Simulation time 192525308700 ps
CPU time 53 seconds
Started Mar 19 12:29:19 PM PDT 24
Finished Mar 19 12:30:12 PM PDT 24
Peak memory 201740 kb
Host smart-6b52984c-e4ba-431f-9f5a-4fa1a88d3f59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347655819 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all
.1347655819
Directory /workspace/24.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.3836167948
Short name T19
Test name
Test status
Simulation time 21932838324 ps
CPU time 47.57 seconds
Started Mar 19 12:29:42 PM PDT 24
Finished Mar 19 12:30:40 PM PDT 24
Peak memory 201964 kb
Host smart-0b0c3290-c7fa-4e2c-88a4-6912b9295f0b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836167948 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all_with_rand_reset.3836167948
Directory /workspace/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_alert_test.125433159
Short name T387
Test name
Test status
Simulation time 541144511 ps
CPU time 0.75 seconds
Started Mar 19 12:29:29 PM PDT 24
Finished Mar 19 12:29:30 PM PDT 24
Peak memory 201512 kb
Host smart-72b86290-eb1f-42a8-bd35-909f249b0bf2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125433159 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.125433159
Directory /workspace/25.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.adc_ctrl_clock_gating.2911710258
Short name T621
Test name
Test status
Simulation time 490878623186 ps
CPU time 490.29 seconds
Started Mar 19 12:29:36 PM PDT 24
Finished Mar 19 12:37:47 PM PDT 24
Peak memory 201748 kb
Host smart-bf876845-0b97-44b0-8419-76994f470400
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911710258 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gat
ing.2911710258
Directory /workspace/25.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_both.1202408537
Short name T701
Test name
Test status
Simulation time 357080864872 ps
CPU time 147.92 seconds
Started Mar 19 12:29:31 PM PDT 24
Finished Mar 19 12:31:59 PM PDT 24
Peak memory 201748 kb
Host smart-a698efee-8268-41be-acb5-82a5f16049b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202408537 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.1202408537
Directory /workspace/25.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt.2203883409
Short name T290
Test name
Test status
Simulation time 167632024865 ps
CPU time 389.9 seconds
Started Mar 19 12:29:59 PM PDT 24
Finished Mar 19 12:36:30 PM PDT 24
Peak memory 201812 kb
Host smart-45589a24-723d-497e-960a-83db6e072a7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203883409 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.2203883409
Directory /workspace/25.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt_fixed.3267258877
Short name T562
Test name
Test status
Simulation time 321050014621 ps
CPU time 698.01 seconds
Started Mar 19 12:29:23 PM PDT 24
Finished Mar 19 12:41:01 PM PDT 24
Peak memory 201788 kb
Host smart-993c6c95-fcda-455f-8221-01ad74b2160b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267258877 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interru
pt_fixed.3267258877
Directory /workspace/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled.2261787426
Short name T166
Test name
Test status
Simulation time 500268779421 ps
CPU time 329.97 seconds
Started Mar 19 12:29:25 PM PDT 24
Finished Mar 19 12:34:55 PM PDT 24
Peak memory 201776 kb
Host smart-c1b88d4c-ec40-44b1-8c36-f2087a528b81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261787426 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.2261787426
Directory /workspace/25.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled_fixed.1513020973
Short name T366
Test name
Test status
Simulation time 332237707966 ps
CPU time 804.31 seconds
Started Mar 19 12:29:31 PM PDT 24
Finished Mar 19 12:42:56 PM PDT 24
Peak memory 201836 kb
Host smart-01f19195-4122-4680-9532-280440aa96e9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513020973 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fix
ed.1513020973
Directory /workspace/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup.3447836088
Short name T285
Test name
Test status
Simulation time 552308585718 ps
CPU time 323.41 seconds
Started Mar 19 12:29:32 PM PDT 24
Finished Mar 19 12:34:55 PM PDT 24
Peak memory 201788 kb
Host smart-0e6a3a8b-21e8-4c47-bf25-73883715387f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447836088 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters
_wakeup.3447836088
Directory /workspace/25.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup_fixed.3333792195
Short name T505
Test name
Test status
Simulation time 394801176069 ps
CPU time 238.49 seconds
Started Mar 19 12:29:19 PM PDT 24
Finished Mar 19 12:33:18 PM PDT 24
Peak memory 201808 kb
Host smart-41e0e0cb-b6e9-4250-8cd3-f523f52cd6db
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333792195 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25
.adc_ctrl_filters_wakeup_fixed.3333792195
Directory /workspace/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_fsm_reset.233260206
Short name T213
Test name
Test status
Simulation time 118742476709 ps
CPU time 399.05 seconds
Started Mar 19 12:29:11 PM PDT 24
Finished Mar 19 12:35:51 PM PDT 24
Peak memory 202140 kb
Host smart-3d6f015d-0db2-4bec-b8f9-e9ce19f6d570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233260206 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.233260206
Directory /workspace/25.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_lowpower_counter.3211198836
Short name T666
Test name
Test status
Simulation time 38035151714 ps
CPU time 91.88 seconds
Started Mar 19 12:29:10 PM PDT 24
Finished Mar 19 12:30:42 PM PDT 24
Peak memory 201628 kb
Host smart-9b20378e-6f41-46c7-8aa0-833437ff51c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211198836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.3211198836
Directory /workspace/25.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_poweron_counter.1577890672
Short name T545
Test name
Test status
Simulation time 5668106113 ps
CPU time 15.09 seconds
Started Mar 19 12:29:41 PM PDT 24
Finished Mar 19 12:29:56 PM PDT 24
Peak memory 201568 kb
Host smart-048d84bf-798c-4e77-840d-b61366ca0114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577890672 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.1577890672
Directory /workspace/25.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_smoke.3149002331
Short name T479
Test name
Test status
Simulation time 5727636299 ps
CPU time 12.51 seconds
Started Mar 19 12:29:37 PM PDT 24
Finished Mar 19 12:29:49 PM PDT 24
Peak memory 201984 kb
Host smart-d7c7e965-173c-481e-a8e4-b60d4bcaec4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149002331 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.3149002331
Directory /workspace/25.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all.3831389637
Short name T785
Test name
Test status
Simulation time 75000061224 ps
CPU time 262.58 seconds
Started Mar 19 12:29:34 PM PDT 24
Finished Mar 19 12:33:57 PM PDT 24
Peak memory 202080 kb
Host smart-c5e7cde7-8333-44ac-a8aa-5d8c4c52d8a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831389637 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all
.3831389637
Directory /workspace/25.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.3285223890
Short name T555
Test name
Test status
Simulation time 22802454068 ps
CPU time 52.83 seconds
Started Mar 19 12:29:34 PM PDT 24
Finished Mar 19 12:30:27 PM PDT 24
Peak memory 218320 kb
Host smart-eb4219e6-7c79-43dd-8f7b-ecd9a28e697d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285223890 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all_with_rand_reset.3285223890
Directory /workspace/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_alert_test.1682068574
Short name T72
Test name
Test status
Simulation time 361395675 ps
CPU time 0.73 seconds
Started Mar 19 12:29:33 PM PDT 24
Finished Mar 19 12:29:34 PM PDT 24
Peak memory 201460 kb
Host smart-040c11e3-4caf-4bc9-b330-75935a65ef20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682068574 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.1682068574
Directory /workspace/26.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.adc_ctrl_clock_gating.1216213344
Short name T337
Test name
Test status
Simulation time 357738417441 ps
CPU time 762.39 seconds
Started Mar 19 12:29:36 PM PDT 24
Finished Mar 19 12:42:18 PM PDT 24
Peak memory 201776 kb
Host smart-9f88bc6a-a7af-4c39-8fb7-d6dff5bbbbd7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216213344 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gat
ing.1216213344
Directory /workspace/26.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt.3536546497
Short name T556
Test name
Test status
Simulation time 170228722758 ps
CPU time 291.71 seconds
Started Mar 19 12:29:11 PM PDT 24
Finished Mar 19 12:34:04 PM PDT 24
Peak memory 201896 kb
Host smart-8dd8d325-19da-40ee-9214-b8990eb88831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536546497 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.3536546497
Directory /workspace/26.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt_fixed.1534125107
Short name T643
Test name
Test status
Simulation time 497336665519 ps
CPU time 234.83 seconds
Started Mar 19 12:29:36 PM PDT 24
Finished Mar 19 12:33:31 PM PDT 24
Peak memory 201736 kb
Host smart-b1ae4753-d823-4445-8891-5c154fbf53dc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534125107 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interru
pt_fixed.1534125107
Directory /workspace/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled.1127088045
Short name T596
Test name
Test status
Simulation time 500356876936 ps
CPU time 292.74 seconds
Started Mar 19 12:29:52 PM PDT 24
Finished Mar 19 12:34:45 PM PDT 24
Peak memory 201804 kb
Host smart-611a58ca-293f-40bf-b950-8cb593dcb954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127088045 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.1127088045
Directory /workspace/26.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled_fixed.1885039443
Short name T169
Test name
Test status
Simulation time 494923613004 ps
CPU time 320.31 seconds
Started Mar 19 12:29:43 PM PDT 24
Finished Mar 19 12:35:03 PM PDT 24
Peak memory 201748 kb
Host smart-5f155f03-e2f9-4ed4-9968-3976491348fc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885039443 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fix
ed.1885039443
Directory /workspace/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup.1804726763
Short name T246
Test name
Test status
Simulation time 569773615307 ps
CPU time 377.81 seconds
Started Mar 19 12:29:47 PM PDT 24
Finished Mar 19 12:36:05 PM PDT 24
Peak memory 201816 kb
Host smart-fc54f1e7-afb7-49d9-875d-198d7b965748
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804726763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters
_wakeup.1804726763
Directory /workspace/26.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup_fixed.1050013600
Short name T686
Test name
Test status
Simulation time 603973808830 ps
CPU time 382.84 seconds
Started Mar 19 12:29:37 PM PDT 24
Finished Mar 19 12:36:00 PM PDT 24
Peak memory 201772 kb
Host smart-42426b64-2b4e-4348-b88d-75aea70de022
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050013600 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26
.adc_ctrl_filters_wakeup_fixed.1050013600
Directory /workspace/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_fsm_reset.3795079702
Short name T495
Test name
Test status
Simulation time 81094699469 ps
CPU time 403.91 seconds
Started Mar 19 12:29:34 PM PDT 24
Finished Mar 19 12:36:18 PM PDT 24
Peak memory 202156 kb
Host smart-ccc74baa-3cb4-4916-9240-c6d3525fa42c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795079702 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.3795079702
Directory /workspace/26.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_lowpower_counter.4007717344
Short name T760
Test name
Test status
Simulation time 32192554086 ps
CPU time 75.97 seconds
Started Mar 19 12:29:57 PM PDT 24
Finished Mar 19 12:31:14 PM PDT 24
Peak memory 201548 kb
Host smart-0d3883f8-b291-444f-9915-9a23c143e7e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007717344 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.4007717344
Directory /workspace/26.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_poweron_counter.2768371703
Short name T653
Test name
Test status
Simulation time 5495889548 ps
CPU time 3.07 seconds
Started Mar 19 12:29:40 PM PDT 24
Finished Mar 19 12:29:43 PM PDT 24
Peak memory 201576 kb
Host smart-211c0ec3-409c-45f0-9235-208395759faa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768371703 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.2768371703
Directory /workspace/26.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_smoke.3849667257
Short name T499
Test name
Test status
Simulation time 6024784016 ps
CPU time 4.09 seconds
Started Mar 19 12:30:06 PM PDT 24
Finished Mar 19 12:30:11 PM PDT 24
Peak memory 201588 kb
Host smart-931dfcc2-98df-48af-8688-504008c0ab32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849667257 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.3849667257
Directory /workspace/26.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all.424880043
Short name T83
Test name
Test status
Simulation time 332026260197 ps
CPU time 216.56 seconds
Started Mar 19 12:29:37 PM PDT 24
Finished Mar 19 12:33:14 PM PDT 24
Peak memory 201720 kb
Host smart-56264770-7d25-4dac-9b5a-187dcf1ff8f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424880043 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all.
424880043
Directory /workspace/26.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.961064635
Short name T215
Test name
Test status
Simulation time 619314501939 ps
CPU time 873.98 seconds
Started Mar 19 12:29:43 PM PDT 24
Finished Mar 19 12:44:18 PM PDT 24
Peak memory 210480 kb
Host smart-21a7e282-da4d-47d6-906e-caa205e8b8bf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961064635 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all_with_rand_reset.961064635
Directory /workspace/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_alert_test.660801186
Short name T407
Test name
Test status
Simulation time 379901932 ps
CPU time 0.74 seconds
Started Mar 19 12:29:33 PM PDT 24
Finished Mar 19 12:29:34 PM PDT 24
Peak memory 201480 kb
Host smart-87e5aeea-92a6-4f93-8826-1bc6172a7df3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660801186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.660801186
Directory /workspace/27.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt.2728547939
Short name T452
Test name
Test status
Simulation time 159205553104 ps
CPU time 91.95 seconds
Started Mar 19 12:29:38 PM PDT 24
Finished Mar 19 12:31:10 PM PDT 24
Peak memory 201816 kb
Host smart-1ff2685d-8649-496a-8a7b-59f087d9214b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728547939 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.2728547939
Directory /workspace/27.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt_fixed.3027287154
Short name T566
Test name
Test status
Simulation time 489603723601 ps
CPU time 261.57 seconds
Started Mar 19 12:29:40 PM PDT 24
Finished Mar 19 12:34:01 PM PDT 24
Peak memory 201748 kb
Host smart-3f211158-b2a4-4576-b3de-066b4e7b3432
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027287154 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interru
pt_fixed.3027287154
Directory /workspace/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled.1158676763
Short name T405
Test name
Test status
Simulation time 160171446339 ps
CPU time 108.7 seconds
Started Mar 19 12:29:23 PM PDT 24
Finished Mar 19 12:31:11 PM PDT 24
Peak memory 201812 kb
Host smart-87f7c79c-dad7-4bae-aef9-dc53214be0eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158676763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.1158676763
Directory /workspace/27.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled_fixed.1000287509
Short name T567
Test name
Test status
Simulation time 327183408442 ps
CPU time 773.04 seconds
Started Mar 19 12:29:29 PM PDT 24
Finished Mar 19 12:42:23 PM PDT 24
Peak memory 201736 kb
Host smart-899566a0-7148-4f30-8015-d91ee395533a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000287509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fix
ed.1000287509
Directory /workspace/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup.2680904087
Short name T304
Test name
Test status
Simulation time 178530470374 ps
CPU time 401.33 seconds
Started Mar 19 12:31:30 PM PDT 24
Finished Mar 19 12:38:11 PM PDT 24
Peak memory 201668 kb
Host smart-c61b5d88-04f4-408e-a103-663d397c218f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680904087 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters
_wakeup.2680904087
Directory /workspace/27.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup_fixed.80364691
Short name T420
Test name
Test status
Simulation time 593248688403 ps
CPU time 386.41 seconds
Started Mar 19 12:29:37 PM PDT 24
Finished Mar 19 12:36:03 PM PDT 24
Peak memory 201748 kb
Host smart-fb6873e9-2a90-428b-8602-66751e045a12
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80364691 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.a
dc_ctrl_filters_wakeup_fixed.80364691
Directory /workspace/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_fsm_reset.2874359069
Short name T52
Test name
Test status
Simulation time 76430562222 ps
CPU time 283.37 seconds
Started Mar 19 12:29:34 PM PDT 24
Finished Mar 19 12:34:18 PM PDT 24
Peak memory 201964 kb
Host smart-b2366b61-f3b9-410b-957d-671c7535836c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874359069 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.2874359069
Directory /workspace/27.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_lowpower_counter.440049079
Short name T595
Test name
Test status
Simulation time 42416041868 ps
CPU time 40.93 seconds
Started Mar 19 12:29:34 PM PDT 24
Finished Mar 19 12:30:15 PM PDT 24
Peak memory 201468 kb
Host smart-97da0cae-faa1-42e6-b21a-1e26e47893f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440049079 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.440049079
Directory /workspace/27.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_poweron_counter.2177629268
Short name T547
Test name
Test status
Simulation time 4932653218 ps
CPU time 3.84 seconds
Started Mar 19 12:29:40 PM PDT 24
Finished Mar 19 12:29:44 PM PDT 24
Peak memory 201568 kb
Host smart-f7402008-bc9b-4760-8452-5ac0ef76e3ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177629268 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.2177629268
Directory /workspace/27.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_smoke.170481667
Short name T430
Test name
Test status
Simulation time 5639146968 ps
CPU time 6.72 seconds
Started Mar 19 12:29:36 PM PDT 24
Finished Mar 19 12:29:43 PM PDT 24
Peak memory 201548 kb
Host smart-72b15913-d619-4ab0-9dce-ddb058b1d0b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170481667 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.170481667
Directory /workspace/27.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all.1097573626
Short name T416
Test name
Test status
Simulation time 12396692427 ps
CPU time 29.5 seconds
Started Mar 19 12:29:33 PM PDT 24
Finished Mar 19 12:30:03 PM PDT 24
Peak memory 201800 kb
Host smart-c9facea8-7c50-4b07-acf6-33a7fd1ae66f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097573626 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all
.1097573626
Directory /workspace/27.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.1129017527
Short name T780
Test name
Test status
Simulation time 57662618461 ps
CPU time 31.9 seconds
Started Mar 19 12:29:40 PM PDT 24
Finished Mar 19 12:30:12 PM PDT 24
Peak memory 210156 kb
Host smart-4b996c71-dfa0-49a6-a669-cfd54fa909e6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129017527 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all_with_rand_reset.1129017527
Directory /workspace/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_alert_test.1220778750
Short name T552
Test name
Test status
Simulation time 548377847 ps
CPU time 0.92 seconds
Started Mar 19 12:29:22 PM PDT 24
Finished Mar 19 12:29:23 PM PDT 24
Peak memory 201432 kb
Host smart-5fe50a26-e75e-4bec-89ef-cfb6c266c8ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220778750 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.1220778750
Directory /workspace/28.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.adc_ctrl_clock_gating.3191412271
Short name T557
Test name
Test status
Simulation time 163002380500 ps
CPU time 262.71 seconds
Started Mar 19 12:29:31 PM PDT 24
Finished Mar 19 12:33:54 PM PDT 24
Peak memory 201760 kb
Host smart-a2471c85-e094-446e-8e3b-445f02d84316
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191412271 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gat
ing.3191412271
Directory /workspace/28.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_both.3804455528
Short name T328
Test name
Test status
Simulation time 339571653846 ps
CPU time 819.34 seconds
Started Mar 19 12:29:32 PM PDT 24
Finished Mar 19 12:43:12 PM PDT 24
Peak memory 201804 kb
Host smart-b0960739-b2a4-4c6a-a816-91cbe2bb639c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804455528 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.3804455528
Directory /workspace/28.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt_fixed.1025612749
Short name T161
Test name
Test status
Simulation time 163589949500 ps
CPU time 89.58 seconds
Started Mar 19 12:31:30 PM PDT 24
Finished Mar 19 12:32:59 PM PDT 24
Peak memory 201652 kb
Host smart-948815a2-4fe0-45e9-a812-c4e400277b19
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025612749 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interru
pt_fixed.1025612749
Directory /workspace/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled.691863825
Short name T193
Test name
Test status
Simulation time 323847129262 ps
CPU time 193.38 seconds
Started Mar 19 12:29:42 PM PDT 24
Finished Mar 19 12:32:55 PM PDT 24
Peak memory 201808 kb
Host smart-cac1a4ea-315a-46dc-8fc6-05631f477237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691863825 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.691863825
Directory /workspace/28.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.1988888297
Short name T104
Test name
Test status
Simulation time 483923425894 ps
CPU time 270.1 seconds
Started Mar 19 12:29:36 PM PDT 24
Finished Mar 19 12:34:07 PM PDT 24
Peak memory 201772 kb
Host smart-0e87ac52-399d-452b-baf4-af7742bafc4b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988888297 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fix
ed.1988888297
Directory /workspace/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup.2624965657
Short name T46
Test name
Test status
Simulation time 171326607805 ps
CPU time 101.84 seconds
Started Mar 19 12:29:34 PM PDT 24
Finished Mar 19 12:31:16 PM PDT 24
Peak memory 201728 kb
Host smart-6679cc5d-1e06-454b-b172-a20cfa3255c2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624965657 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters
_wakeup.2624965657
Directory /workspace/28.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.562000470
Short name T403
Test name
Test status
Simulation time 405983644007 ps
CPU time 946.17 seconds
Started Mar 19 12:29:42 PM PDT 24
Finished Mar 19 12:45:29 PM PDT 24
Peak memory 201804 kb
Host smart-d4387f1c-bc74-4d8d-829f-2e2f5c222854
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562000470 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
adc_ctrl_filters_wakeup_fixed.562000470
Directory /workspace/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_lowpower_counter.1593859944
Short name T525
Test name
Test status
Simulation time 45353233336 ps
CPU time 53.58 seconds
Started Mar 19 12:29:29 PM PDT 24
Finished Mar 19 12:30:23 PM PDT 24
Peak memory 201620 kb
Host smart-796d5b04-3df6-46b8-a0ea-5d00776df0d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593859944 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.1593859944
Directory /workspace/28.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_poweron_counter.1063943810
Short name T574
Test name
Test status
Simulation time 4489192913 ps
CPU time 11.01 seconds
Started Mar 19 12:29:35 PM PDT 24
Finished Mar 19 12:29:46 PM PDT 24
Peak memory 201620 kb
Host smart-0f909e79-89a2-4010-bdb9-9a74c2662e85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063943810 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.1063943810
Directory /workspace/28.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_smoke.4016112863
Short name T433
Test name
Test status
Simulation time 5653050709 ps
CPU time 3.97 seconds
Started Mar 19 12:29:24 PM PDT 24
Finished Mar 19 12:29:28 PM PDT 24
Peak memory 201628 kb
Host smart-b6cc7bea-fba1-4ffa-a31d-ef2a2e7d42c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016112863 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.4016112863
Directory /workspace/28.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.2376113535
Short name T20
Test name
Test status
Simulation time 107506943659 ps
CPU time 258.14 seconds
Started Mar 19 12:29:44 PM PDT 24
Finished Mar 19 12:34:03 PM PDT 24
Peak memory 218280 kb
Host smart-1848d0e3-e308-41b7-9757-efada2d5d102
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376113535 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all_with_rand_reset.2376113535
Directory /workspace/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_alert_test.490036979
Short name T370
Test name
Test status
Simulation time 432772789 ps
CPU time 1.66 seconds
Started Mar 19 12:29:37 PM PDT 24
Finished Mar 19 12:29:39 PM PDT 24
Peak memory 201456 kb
Host smart-97009936-3bcf-42cb-9321-feda303e71b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490036979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.490036979
Directory /workspace/29.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.adc_ctrl_clock_gating.4150004022
Short name T303
Test name
Test status
Simulation time 169678669986 ps
CPU time 107.31 seconds
Started Mar 19 12:29:27 PM PDT 24
Finished Mar 19 12:31:15 PM PDT 24
Peak memory 201724 kb
Host smart-1e85c560-a62b-4120-9e78-d5edf7b90aea
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150004022 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gat
ing.4150004022
Directory /workspace/29.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_both.4001592246
Short name T221
Test name
Test status
Simulation time 339204419653 ps
CPU time 808.56 seconds
Started Mar 19 12:29:28 PM PDT 24
Finished Mar 19 12:42:56 PM PDT 24
Peak memory 201748 kb
Host smart-5662b6f0-7854-4f47-af68-dac108c8a821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001592246 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.4001592246
Directory /workspace/29.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt.1959103730
Short name T223
Test name
Test status
Simulation time 494762365497 ps
CPU time 1189.63 seconds
Started Mar 19 12:29:38 PM PDT 24
Finished Mar 19 12:49:28 PM PDT 24
Peak memory 201748 kb
Host smart-1e02465f-307f-4b8e-b1d5-eede8cfc82da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959103730 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.1959103730
Directory /workspace/29.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt_fixed.1952334600
Short name T597
Test name
Test status
Simulation time 329548789439 ps
CPU time 797.72 seconds
Started Mar 19 12:29:34 PM PDT 24
Finished Mar 19 12:42:52 PM PDT 24
Peak memory 201712 kb
Host smart-93b2ae2f-ccf8-4b14-bc79-960a49a9492a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952334600 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interru
pt_fixed.1952334600
Directory /workspace/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled.1173203737
Short name T404
Test name
Test status
Simulation time 162059814188 ps
CPU time 50.42 seconds
Started Mar 19 12:30:00 PM PDT 24
Finished Mar 19 12:30:51 PM PDT 24
Peak memory 201756 kb
Host smart-61478e44-5e0f-4f0c-8123-d13a63b98906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173203737 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.1173203737
Directory /workspace/29.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.269878868
Short name T714
Test name
Test status
Simulation time 485029574210 ps
CPU time 235.44 seconds
Started Mar 19 12:29:20 PM PDT 24
Finished Mar 19 12:33:16 PM PDT 24
Peak memory 201824 kb
Host smart-c35a821f-3614-4d49-8c0d-b62369f2cb2b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=269878868 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fixe
d.269878868
Directory /workspace/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup.3447057705
Short name T563
Test name
Test status
Simulation time 521551396963 ps
CPU time 1166.29 seconds
Started Mar 19 12:29:40 PM PDT 24
Finished Mar 19 12:49:06 PM PDT 24
Peak memory 201872 kb
Host smart-595e7ff5-4aa3-42e3-a289-860b4158ec77
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447057705 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters
_wakeup.3447057705
Directory /workspace/29.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup_fixed.3654655930
Short name T474
Test name
Test status
Simulation time 414488455647 ps
CPU time 914.63 seconds
Started Mar 19 12:30:03 PM PDT 24
Finished Mar 19 12:45:18 PM PDT 24
Peak memory 201796 kb
Host smart-7ff34e24-1007-4135-8227-4b0be26f9864
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654655930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29
.adc_ctrl_filters_wakeup_fixed.3654655930
Directory /workspace/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_fsm_reset.4084754479
Short name T29
Test name
Test status
Simulation time 91412838867 ps
CPU time 280.69 seconds
Started Mar 19 12:29:55 PM PDT 24
Finished Mar 19 12:34:36 PM PDT 24
Peak memory 202048 kb
Host smart-cdac89fb-7fea-411a-b9bc-1b6f9e04185e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084754479 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.4084754479
Directory /workspace/29.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_lowpower_counter.2623886300
Short name T147
Test name
Test status
Simulation time 40584535556 ps
CPU time 23.05 seconds
Started Mar 19 12:30:06 PM PDT 24
Finished Mar 19 12:30:30 PM PDT 24
Peak memory 201576 kb
Host smart-b314c56e-be99-4b86-9f03-183a25cdd7f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623886300 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.2623886300
Directory /workspace/29.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_poweron_counter.3947821997
Short name T743
Test name
Test status
Simulation time 3779556933 ps
CPU time 9.3 seconds
Started Mar 19 12:29:37 PM PDT 24
Finished Mar 19 12:29:46 PM PDT 24
Peak memory 201632 kb
Host smart-c68b2784-3224-4c12-a59e-28e0abe7f1a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947821997 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.3947821997
Directory /workspace/29.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_smoke.1742385238
Short name T585
Test name
Test status
Simulation time 5681295399 ps
CPU time 9.94 seconds
Started Mar 19 12:29:34 PM PDT 24
Finished Mar 19 12:29:44 PM PDT 24
Peak memory 201576 kb
Host smart-d04ae414-016e-46cf-8cfb-e92a84b33041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742385238 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.1742385238
Directory /workspace/29.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.2913113942
Short name T90
Test name
Test status
Simulation time 8184819420 ps
CPU time 21.46 seconds
Started Mar 19 12:29:58 PM PDT 24
Finished Mar 19 12:30:20 PM PDT 24
Peak memory 201904 kb
Host smart-5dbc0890-ba1b-45ca-9a47-4f2a53a98ead
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913113942 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all_with_rand_reset.2913113942
Directory /workspace/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_alert_test.3097610156
Short name T787
Test name
Test status
Simulation time 309119009 ps
CPU time 0.94 seconds
Started Mar 19 12:28:50 PM PDT 24
Finished Mar 19 12:28:52 PM PDT 24
Peak memory 201460 kb
Host smart-b72007ac-f4ef-44f8-9439-f6495d90386b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097610156 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.3097610156
Directory /workspace/3.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.adc_ctrl_clock_gating.621511106
Short name T231
Test name
Test status
Simulation time 177001706630 ps
CPU time 199.58 seconds
Started Mar 19 12:29:03 PM PDT 24
Finished Mar 19 12:32:22 PM PDT 24
Peak memory 201820 kb
Host smart-0b3034f8-fa5e-4848-bffc-5e8b31c3f6df
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621511106 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gatin
g.621511106
Directory /workspace/3.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_both.2190136231
Short name T292
Test name
Test status
Simulation time 175013709061 ps
CPU time 107.51 seconds
Started Mar 19 12:29:12 PM PDT 24
Finished Mar 19 12:31:00 PM PDT 24
Peak memory 201740 kb
Host smart-20bd16ee-d1ab-4175-a9b3-3caa14c705a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190136231 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.2190136231
Directory /workspace/3.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt.3351550217
Short name T768
Test name
Test status
Simulation time 162850014586 ps
CPU time 94.49 seconds
Started Mar 19 12:28:47 PM PDT 24
Finished Mar 19 12:30:22 PM PDT 24
Peak memory 201736 kb
Host smart-b2494b4e-6b98-46b5-9851-1e78639c90f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351550217 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.3351550217
Directory /workspace/3.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt_fixed.3789866909
Short name T633
Test name
Test status
Simulation time 167284812608 ps
CPU time 106.42 seconds
Started Mar 19 12:28:51 PM PDT 24
Finished Mar 19 12:30:38 PM PDT 24
Peak memory 201928 kb
Host smart-984d8204-2121-4ec3-b5cf-aa93e607591a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789866909 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrup
t_fixed.3789866909
Directory /workspace/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled.1905334054
Short name T736
Test name
Test status
Simulation time 328391845548 ps
CPU time 107.03 seconds
Started Mar 19 12:29:15 PM PDT 24
Finished Mar 19 12:31:04 PM PDT 24
Peak memory 201760 kb
Host smart-07d7a755-fe57-4579-8a67-c6fa711a6901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905334054 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.1905334054
Directory /workspace/3.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled_fixed.3418010640
Short name T355
Test name
Test status
Simulation time 320651064709 ps
CPU time 758.45 seconds
Started Mar 19 12:28:57 PM PDT 24
Finished Mar 19 12:41:36 PM PDT 24
Peak memory 201816 kb
Host smart-9b1d4b92-ee7e-4ed3-b1dd-41d278aff999
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418010640 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixe
d.3418010640
Directory /workspace/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup.905029777
Short name T262
Test name
Test status
Simulation time 557822352681 ps
CPU time 1272.35 seconds
Started Mar 19 12:28:55 PM PDT 24
Finished Mar 19 12:50:08 PM PDT 24
Peak memory 201824 kb
Host smart-abcd31a9-e8b8-4e81-8d77-ade58f11fc0a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905029777 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_w
akeup.905029777
Directory /workspace/3.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup_fixed.1807261650
Short name T571
Test name
Test status
Simulation time 607605437197 ps
CPU time 1361.13 seconds
Started Mar 19 12:29:02 PM PDT 24
Finished Mar 19 12:51:43 PM PDT 24
Peak memory 201736 kb
Host smart-b8226a6d-5d22-4c2d-92e0-e42fac27c451
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807261650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.
adc_ctrl_filters_wakeup_fixed.1807261650
Directory /workspace/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_fsm_reset.3251265920
Short name T709
Test name
Test status
Simulation time 139984465480 ps
CPU time 575.43 seconds
Started Mar 19 12:28:55 PM PDT 24
Finished Mar 19 12:38:31 PM PDT 24
Peak memory 202140 kb
Host smart-39c19226-095f-474c-9af8-a59b3c47aa25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251265920 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.3251265920
Directory /workspace/3.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_lowpower_counter.3273913864
Short name T486
Test name
Test status
Simulation time 40652692144 ps
CPU time 50.09 seconds
Started Mar 19 12:28:42 PM PDT 24
Finished Mar 19 12:29:33 PM PDT 24
Peak memory 201636 kb
Host smart-54f96b9d-b6f4-480e-8f51-ab2966ee23c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273913864 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.3273913864
Directory /workspace/3.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_poweron_counter.2118894670
Short name T443
Test name
Test status
Simulation time 3213210539 ps
CPU time 8.08 seconds
Started Mar 19 12:29:17 PM PDT 24
Finished Mar 19 12:29:25 PM PDT 24
Peak memory 201572 kb
Host smart-91afd48e-29c3-4baa-9fff-a09c2991eaf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118894670 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.2118894670
Directory /workspace/3.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_sec_cm.1418400347
Short name T81
Test name
Test status
Simulation time 3978541761 ps
CPU time 3.08 seconds
Started Mar 19 12:28:35 PM PDT 24
Finished Mar 19 12:28:39 PM PDT 24
Peak memory 217296 kb
Host smart-a81dcf62-fa05-41d0-a4c0-32d12220192c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418400347 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.1418400347
Directory /workspace/3.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.adc_ctrl_smoke.1419848771
Short name T734
Test name
Test status
Simulation time 5913287372 ps
CPU time 16.24 seconds
Started Mar 19 12:29:40 PM PDT 24
Finished Mar 19 12:29:57 PM PDT 24
Peak memory 201592 kb
Host smart-a41512b7-c024-45a3-9efb-f30bf9be810d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419848771 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.1419848771
Directory /workspace/3.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all.3579953487
Short name T336
Test name
Test status
Simulation time 444850773055 ps
CPU time 1200.78 seconds
Started Mar 19 12:29:01 PM PDT 24
Finished Mar 19 12:49:02 PM PDT 24
Peak memory 210280 kb
Host smart-c8a3bdcf-3fe1-4b67-9fa3-08c192caf8f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579953487 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all.
3579953487
Directory /workspace/3.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.2497800987
Short name T769
Test name
Test status
Simulation time 39205881126 ps
CPU time 145.09 seconds
Started Mar 19 12:29:07 PM PDT 24
Finished Mar 19 12:31:33 PM PDT 24
Peak memory 210516 kb
Host smart-f29de5b5-07b8-4d8a-8643-4def9c2f1cea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497800987 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all_with_rand_reset.2497800987
Directory /workspace/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_alert_test.2015339011
Short name T157
Test name
Test status
Simulation time 359846619 ps
CPU time 1.01 seconds
Started Mar 19 12:30:04 PM PDT 24
Finished Mar 19 12:30:05 PM PDT 24
Peak memory 201464 kb
Host smart-025a47cd-5f0e-4244-a825-9a0b265837ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015339011 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.2015339011
Directory /workspace/30.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.adc_ctrl_clock_gating.3617026393
Short name T252
Test name
Test status
Simulation time 223233115745 ps
CPU time 14.79 seconds
Started Mar 19 12:29:40 PM PDT 24
Finished Mar 19 12:29:55 PM PDT 24
Peak memory 201812 kb
Host smart-9794c60b-8337-45ce-851a-edd9884f9a4a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617026393 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gat
ing.3617026393
Directory /workspace/30.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_both.3422903312
Short name T251
Test name
Test status
Simulation time 167841554823 ps
CPU time 86.86 seconds
Started Mar 19 12:29:29 PM PDT 24
Finished Mar 19 12:30:56 PM PDT 24
Peak memory 201748 kb
Host smart-6d728d2a-dff3-4412-925e-afacda3c9dad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422903312 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.3422903312
Directory /workspace/30.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt_fixed.2277095750
Short name T521
Test name
Test status
Simulation time 489037183668 ps
CPU time 1021.69 seconds
Started Mar 19 12:30:07 PM PDT 24
Finished Mar 19 12:47:10 PM PDT 24
Peak memory 201740 kb
Host smart-8e15e1ff-e4e7-4fdd-8dbe-3cdd090be98b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277095750 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interru
pt_fixed.2277095750
Directory /workspace/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled.4142640165
Short name T220
Test name
Test status
Simulation time 485838315233 ps
CPU time 440.37 seconds
Started Mar 19 12:29:36 PM PDT 24
Finished Mar 19 12:36:57 PM PDT 24
Peak memory 201768 kb
Host smart-4803d6fa-c247-4780-95c5-d873952f7390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142640165 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.4142640165
Directory /workspace/30.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled_fixed.1795942313
Short name T704
Test name
Test status
Simulation time 329330901471 ps
CPU time 747.63 seconds
Started Mar 19 12:31:26 PM PDT 24
Finished Mar 19 12:43:53 PM PDT 24
Peak memory 201780 kb
Host smart-f5e84e01-154c-4b2c-9fa1-eef9dc707384
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795942313 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fix
ed.1795942313
Directory /workspace/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup.1703270340
Short name T437
Test name
Test status
Simulation time 213096323934 ps
CPU time 479.72 seconds
Started Mar 19 12:29:39 PM PDT 24
Finished Mar 19 12:37:39 PM PDT 24
Peak memory 201832 kb
Host smart-ea380e1e-7959-46f5-82b6-0048fc0f19e8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703270340 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters
_wakeup.1703270340
Directory /workspace/30.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup_fixed.3432361447
Short name T560
Test name
Test status
Simulation time 407164874761 ps
CPU time 162.37 seconds
Started Mar 19 12:29:35 PM PDT 24
Finished Mar 19 12:32:18 PM PDT 24
Peak memory 201728 kb
Host smart-fcbe4498-687c-4157-8e40-d2c27ac7702d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432361447 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30
.adc_ctrl_filters_wakeup_fixed.3432361447
Directory /workspace/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_fsm_reset.3545877364
Short name T208
Test name
Test status
Simulation time 103509985406 ps
CPU time 303.62 seconds
Started Mar 19 12:29:38 PM PDT 24
Finished Mar 19 12:34:41 PM PDT 24
Peak memory 202064 kb
Host smart-39443393-a260-475f-9b76-f4e340e95e8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545877364 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.3545877364
Directory /workspace/30.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_lowpower_counter.1636726216
Short name T398
Test name
Test status
Simulation time 42656699086 ps
CPU time 16.95 seconds
Started Mar 19 12:29:42 PM PDT 24
Finished Mar 19 12:29:59 PM PDT 24
Peak memory 201620 kb
Host smart-da60efeb-fd0f-4bec-894a-3d732be352d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636726216 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.1636726216
Directory /workspace/30.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_poweron_counter.544628903
Short name T434
Test name
Test status
Simulation time 3919191841 ps
CPU time 3.3 seconds
Started Mar 19 12:29:57 PM PDT 24
Finished Mar 19 12:30:01 PM PDT 24
Peak memory 201584 kb
Host smart-32196f8e-5879-4816-b964-d246c699b743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544628903 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.544628903
Directory /workspace/30.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_smoke.3555093884
Short name T515
Test name
Test status
Simulation time 5642771899 ps
CPU time 14.03 seconds
Started Mar 19 12:29:35 PM PDT 24
Finished Mar 19 12:29:49 PM PDT 24
Peak memory 201588 kb
Host smart-f0fd04a8-7e64-4786-ab01-891d5b21b034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555093884 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.3555093884
Directory /workspace/30.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all.3324146126
Short name T418
Test name
Test status
Simulation time 31784735690 ps
CPU time 37.43 seconds
Started Mar 19 12:29:25 PM PDT 24
Finished Mar 19 12:30:02 PM PDT 24
Peak memory 201624 kb
Host smart-9485fa29-08a5-4fe3-89fd-8eb4672a61c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324146126 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all
.3324146126
Directory /workspace/30.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.1507887702
Short name T295
Test name
Test status
Simulation time 60222631448 ps
CPU time 45.96 seconds
Started Mar 19 12:29:43 PM PDT 24
Finished Mar 19 12:30:29 PM PDT 24
Peak memory 218604 kb
Host smart-8fa26e6b-0b7c-4b0d-9ec8-719cb32b3d1c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507887702 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all_with_rand_reset.1507887702
Directory /workspace/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_alert_test.2187864642
Short name T158
Test name
Test status
Simulation time 544258979 ps
CPU time 0.92 seconds
Started Mar 19 12:31:13 PM PDT 24
Finished Mar 19 12:31:15 PM PDT 24
Peak memory 200616 kb
Host smart-05cf5b6b-c404-40b2-beb7-a1433df412b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187864642 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.2187864642
Directory /workspace/31.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_both.2149264876
Short name T609
Test name
Test status
Simulation time 164601513178 ps
CPU time 354.87 seconds
Started Mar 19 12:30:03 PM PDT 24
Finished Mar 19 12:35:58 PM PDT 24
Peak memory 201844 kb
Host smart-00e79666-242f-4700-9803-2505601ee0c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149264876 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.2149264876
Directory /workspace/31.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt.336549382
Short name T234
Test name
Test status
Simulation time 327495477694 ps
CPU time 781.21 seconds
Started Mar 19 12:29:26 PM PDT 24
Finished Mar 19 12:42:27 PM PDT 24
Peak memory 201712 kb
Host smart-5261fab9-53d2-4e26-9b0f-36b7909d7467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336549382 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.336549382
Directory /workspace/31.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt_fixed.289095426
Short name T232
Test name
Test status
Simulation time 163298457579 ps
CPU time 391.27 seconds
Started Mar 19 12:30:07 PM PDT 24
Finished Mar 19 12:36:39 PM PDT 24
Peak memory 201740 kb
Host smart-18068d7e-482b-4482-b7b8-a0f0506ecbcb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=289095426 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrup
t_fixed.289095426
Directory /workspace/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled.110601598
Short name T724
Test name
Test status
Simulation time 161058991729 ps
CPU time 58.76 seconds
Started Mar 19 12:29:35 PM PDT 24
Finished Mar 19 12:30:34 PM PDT 24
Peak memory 201816 kb
Host smart-f5ba651f-12f6-4a82-b67e-3a5a996d5eed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110601598 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.110601598
Directory /workspace/31.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled_fixed.272301127
Short name T469
Test name
Test status
Simulation time 493419907344 ps
CPU time 177.14 seconds
Started Mar 19 12:29:36 PM PDT 24
Finished Mar 19 12:32:33 PM PDT 24
Peak memory 201716 kb
Host smart-1ec641d7-6992-42c4-ab0b-0b61ebbbdeb6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=272301127 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fixe
d.272301127
Directory /workspace/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup.4081851063
Short name T688
Test name
Test status
Simulation time 386125411459 ps
CPU time 835.34 seconds
Started Mar 19 12:29:39 PM PDT 24
Finished Mar 19 12:43:35 PM PDT 24
Peak memory 201804 kb
Host smart-f36785a8-c781-4e37-823a-e24bb1fef6ab
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081851063 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters
_wakeup.4081851063
Directory /workspace/31.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup_fixed.1324817308
Short name T413
Test name
Test status
Simulation time 387865603212 ps
CPU time 885.85 seconds
Started Mar 19 12:29:21 PM PDT 24
Finished Mar 19 12:44:08 PM PDT 24
Peak memory 201752 kb
Host smart-a95ec378-8e50-4bb9-b84f-322dc5f905a4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324817308 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31
.adc_ctrl_filters_wakeup_fixed.1324817308
Directory /workspace/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_fsm_reset.2779177428
Short name T209
Test name
Test status
Simulation time 120271283433 ps
CPU time 402.51 seconds
Started Mar 19 12:29:25 PM PDT 24
Finished Mar 19 12:36:08 PM PDT 24
Peak memory 202100 kb
Host smart-e5b43061-0e1d-457d-8e58-47467c7f5af8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779177428 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.2779177428
Directory /workspace/31.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_lowpower_counter.165038545
Short name T500
Test name
Test status
Simulation time 40811706676 ps
CPU time 48.71 seconds
Started Mar 19 12:30:07 PM PDT 24
Finished Mar 19 12:30:57 PM PDT 24
Peak memory 201564 kb
Host smart-f33e4164-8cae-482f-906f-fd042e595353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165038545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.165038545
Directory /workspace/31.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_poweron_counter.312415053
Short name T482
Test name
Test status
Simulation time 2991318211 ps
CPU time 2.67 seconds
Started Mar 19 12:30:08 PM PDT 24
Finished Mar 19 12:30:12 PM PDT 24
Peak memory 201572 kb
Host smart-79c06212-aa37-4666-84ab-df75429afdcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312415053 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.312415053
Directory /workspace/31.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_smoke.1155247182
Short name T375
Test name
Test status
Simulation time 5864885082 ps
CPU time 5.71 seconds
Started Mar 19 12:29:35 PM PDT 24
Finished Mar 19 12:29:41 PM PDT 24
Peak memory 201632 kb
Host smart-51ad10ab-11d7-4e04-9646-fdc47cfed034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155247182 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.1155247182
Directory /workspace/31.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all.3310820288
Short name T361
Test name
Test status
Simulation time 9940431746 ps
CPU time 1.98 seconds
Started Mar 19 12:29:24 PM PDT 24
Finished Mar 19 12:29:26 PM PDT 24
Peak memory 201564 kb
Host smart-b2af9705-8199-43c6-91c7-11c77b4dff54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310820288 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all
.3310820288
Directory /workspace/31.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.319115688
Short name T718
Test name
Test status
Simulation time 273619160617 ps
CPU time 168.67 seconds
Started Mar 19 12:30:04 PM PDT 24
Finished Mar 19 12:32:53 PM PDT 24
Peak memory 210112 kb
Host smart-83019229-09a1-4dbf-817a-f72b640bd6c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319115688 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all_with_rand_reset.319115688
Directory /workspace/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_alert_test.3275345831
Short name T176
Test name
Test status
Simulation time 552887743 ps
CPU time 0.92 seconds
Started Mar 19 12:29:57 PM PDT 24
Finished Mar 19 12:29:59 PM PDT 24
Peak memory 201492 kb
Host smart-38f30d56-31d3-4561-9f20-c1ce2b0a2b79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275345831 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.3275345831
Directory /workspace/32.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.adc_ctrl_clock_gating.2607750858
Short name T233
Test name
Test status
Simulation time 522891450802 ps
CPU time 209.83 seconds
Started Mar 19 12:29:41 PM PDT 24
Finished Mar 19 12:33:10 PM PDT 24
Peak memory 201872 kb
Host smart-37c91684-f7db-41ff-ac12-36fd5262f980
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607750858 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gat
ing.2607750858
Directory /workspace/32.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_both.568144719
Short name T259
Test name
Test status
Simulation time 485174304651 ps
CPU time 904.32 seconds
Started Mar 19 12:29:39 PM PDT 24
Finished Mar 19 12:44:44 PM PDT 24
Peak memory 201848 kb
Host smart-8aa23a1f-145e-4d6c-a17d-574b19cc925a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568144719 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.568144719
Directory /workspace/32.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt.4152651720
Short name T548
Test name
Test status
Simulation time 158861491676 ps
CPU time 180.13 seconds
Started Mar 19 12:29:41 PM PDT 24
Finished Mar 19 12:32:41 PM PDT 24
Peak memory 201892 kb
Host smart-5cabc89e-f038-41c1-8991-3592d8ec3dda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152651720 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.4152651720
Directory /workspace/32.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt_fixed.1737573603
Short name T580
Test name
Test status
Simulation time 162554412133 ps
CPU time 367.78 seconds
Started Mar 19 12:29:34 PM PDT 24
Finished Mar 19 12:35:41 PM PDT 24
Peak memory 201780 kb
Host smart-449f83bf-10a7-4686-b29a-5649286417b5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737573603 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interru
pt_fixed.1737573603
Directory /workspace/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled.1782705075
Short name T561
Test name
Test status
Simulation time 488320398192 ps
CPU time 73.06 seconds
Started Mar 19 12:29:47 PM PDT 24
Finished Mar 19 12:31:01 PM PDT 24
Peak memory 201760 kb
Host smart-662cd533-f049-4868-8255-97f0206c5406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782705075 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.1782705075
Directory /workspace/32.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled_fixed.983913793
Short name T637
Test name
Test status
Simulation time 327239090028 ps
CPU time 381.56 seconds
Started Mar 19 12:29:36 PM PDT 24
Finished Mar 19 12:35:58 PM PDT 24
Peak memory 201764 kb
Host smart-722bd484-5f23-482c-90e8-d30fd9217cf5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=983913793 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fixe
d.983913793
Directory /workspace/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup.3871280227
Short name T606
Test name
Test status
Simulation time 598054376772 ps
CPU time 371.15 seconds
Started Mar 19 12:30:05 PM PDT 24
Finished Mar 19 12:36:17 PM PDT 24
Peak memory 201756 kb
Host smart-f69fdb25-0b9b-450b-b86f-cc0366843ca1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871280227 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters
_wakeup.3871280227
Directory /workspace/32.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup_fixed.3953201305
Short name T740
Test name
Test status
Simulation time 586997990116 ps
CPU time 307.94 seconds
Started Mar 19 12:30:08 PM PDT 24
Finished Mar 19 12:35:16 PM PDT 24
Peak memory 201868 kb
Host smart-965016e7-296c-4fb2-83ab-840588116546
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953201305 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32
.adc_ctrl_filters_wakeup_fixed.3953201305
Directory /workspace/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_fsm_reset.972847558
Short name T707
Test name
Test status
Simulation time 109545033056 ps
CPU time 438.71 seconds
Started Mar 19 12:29:41 PM PDT 24
Finished Mar 19 12:37:00 PM PDT 24
Peak memory 202040 kb
Host smart-e79f388c-32ee-42b6-8c37-77dc2707e787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972847558 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.972847558
Directory /workspace/32.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_lowpower_counter.424735041
Short name T3
Test name
Test status
Simulation time 24047797533 ps
CPU time 53.46 seconds
Started Mar 19 12:29:34 PM PDT 24
Finished Mar 19 12:30:27 PM PDT 24
Peak memory 201640 kb
Host smart-5eb9f823-22af-4933-ac17-131d20d1269a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424735041 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.424735041
Directory /workspace/32.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_poweron_counter.523196442
Short name T491
Test name
Test status
Simulation time 3412066195 ps
CPU time 8.14 seconds
Started Mar 19 12:29:34 PM PDT 24
Finished Mar 19 12:29:42 PM PDT 24
Peak memory 201548 kb
Host smart-3f466873-f610-4ba5-9f11-5d5c90bbd454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523196442 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.523196442
Directory /workspace/32.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_smoke.3034879308
Short name T744
Test name
Test status
Simulation time 5864482888 ps
CPU time 8.76 seconds
Started Mar 19 12:29:37 PM PDT 24
Finished Mar 19 12:29:46 PM PDT 24
Peak memory 201592 kb
Host smart-6be69d5a-1bc7-4b21-bd09-a3049bbe7a98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034879308 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.3034879308
Directory /workspace/32.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all.3052212018
Short name T299
Test name
Test status
Simulation time 193684267736 ps
CPU time 58.75 seconds
Started Mar 19 12:29:42 PM PDT 24
Finished Mar 19 12:30:41 PM PDT 24
Peak memory 201776 kb
Host smart-00736040-b1c1-426d-a73e-3c8e6b0b870d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052212018 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all
.3052212018
Directory /workspace/32.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.401525038
Short name T36
Test name
Test status
Simulation time 14151875391 ps
CPU time 46.59 seconds
Started Mar 19 12:29:43 PM PDT 24
Finished Mar 19 12:30:30 PM PDT 24
Peak memory 210524 kb
Host smart-1dcd7ef6-0b41-44c4-876a-ae028236a37a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401525038 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all_with_rand_reset.401525038
Directory /workspace/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_alert_test.2051563313
Short name T622
Test name
Test status
Simulation time 381532225 ps
CPU time 1.41 seconds
Started Mar 19 12:29:58 PM PDT 24
Finished Mar 19 12:29:59 PM PDT 24
Peak memory 201448 kb
Host smart-67618130-a204-456a-ab4a-a85abfe448c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051563313 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.2051563313
Directory /workspace/33.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_both.2757962761
Short name T615
Test name
Test status
Simulation time 162935005712 ps
CPU time 357.51 seconds
Started Mar 19 12:29:41 PM PDT 24
Finished Mar 19 12:35:39 PM PDT 24
Peak memory 201768 kb
Host smart-4e3800d1-d0d2-4639-a551-db57f6cb2320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757962761 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.2757962761
Directory /workspace/33.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt.3318935667
Short name T178
Test name
Test status
Simulation time 485098166943 ps
CPU time 1062.14 seconds
Started Mar 19 12:29:46 PM PDT 24
Finished Mar 19 12:47:29 PM PDT 24
Peak memory 201740 kb
Host smart-63b83e5e-07c8-4447-b972-2731515d9fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318935667 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.3318935667
Directory /workspace/33.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt_fixed.1543764079
Short name T399
Test name
Test status
Simulation time 162882690380 ps
CPU time 195.06 seconds
Started Mar 19 12:31:29 PM PDT 24
Finished Mar 19 12:34:44 PM PDT 24
Peak memory 201600 kb
Host smart-2cea4a47-5eab-4d19-954b-50f1501c71da
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543764079 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interru
pt_fixed.1543764079
Directory /workspace/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled.1634831416
Short name T324
Test name
Test status
Simulation time 331393598510 ps
CPU time 244.43 seconds
Started Mar 19 12:31:28 PM PDT 24
Finished Mar 19 12:35:33 PM PDT 24
Peak memory 201676 kb
Host smart-6417b7ef-ccee-415f-ac20-35f0ada4a825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634831416 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.1634831416
Directory /workspace/33.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled_fixed.2931518742
Short name T170
Test name
Test status
Simulation time 497656419745 ps
CPU time 309.91 seconds
Started Mar 19 12:29:35 PM PDT 24
Finished Mar 19 12:34:45 PM PDT 24
Peak memory 201888 kb
Host smart-1c0d8ae2-3d96-4b1d-b558-900c735d731a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931518742 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fix
ed.2931518742
Directory /workspace/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup.2530522583
Short name T100
Test name
Test status
Simulation time 178710214755 ps
CPU time 53.33 seconds
Started Mar 19 12:29:46 PM PDT 24
Finished Mar 19 12:30:39 PM PDT 24
Peak memory 201808 kb
Host smart-c8296b08-905c-49a5-86c2-2acd50d13320
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530522583 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters
_wakeup.2530522583
Directory /workspace/33.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/33.adc_ctrl_fsm_reset.2538891265
Short name T526
Test name
Test status
Simulation time 66953770306 ps
CPU time 240.46 seconds
Started Mar 19 12:29:37 PM PDT 24
Finished Mar 19 12:33:37 PM PDT 24
Peak memory 202104 kb
Host smart-02a2fd0d-3cd7-4735-9df8-16e8e7f544f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538891265 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.2538891265
Directory /workspace/33.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_lowpower_counter.1929025293
Short name T358
Test name
Test status
Simulation time 29945510101 ps
CPU time 16.62 seconds
Started Mar 19 12:29:38 PM PDT 24
Finished Mar 19 12:29:55 PM PDT 24
Peak memory 201564 kb
Host smart-700722d9-50ae-4b06-9a49-14880b7b5c71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929025293 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.1929025293
Directory /workspace/33.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_poweron_counter.498260807
Short name T350
Test name
Test status
Simulation time 4263420925 ps
CPU time 11.21 seconds
Started Mar 19 12:29:46 PM PDT 24
Finished Mar 19 12:29:57 PM PDT 24
Peak memory 201568 kb
Host smart-e08e95ac-d505-4bf6-a93f-c9967065beb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498260807 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.498260807
Directory /workspace/33.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_smoke.3234255508
Short name T720
Test name
Test status
Simulation time 5800351226 ps
CPU time 4.59 seconds
Started Mar 19 12:29:35 PM PDT 24
Finished Mar 19 12:29:39 PM PDT 24
Peak memory 201548 kb
Host smart-9988b788-0777-48fd-bc1b-0ad4b1341025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234255508 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.3234255508
Directory /workspace/33.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all.3078741410
Short name T687
Test name
Test status
Simulation time 70098747192 ps
CPU time 26.45 seconds
Started Mar 19 12:29:42 PM PDT 24
Finished Mar 19 12:30:09 PM PDT 24
Peak memory 201728 kb
Host smart-3ad99c2d-b3c2-48ab-b688-0bd7b65ae2de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078741410 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all
.3078741410
Directory /workspace/33.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.4107140878
Short name T538
Test name
Test status
Simulation time 46162344927 ps
CPU time 51.02 seconds
Started Mar 19 12:29:46 PM PDT 24
Finished Mar 19 12:30:37 PM PDT 24
Peak memory 210408 kb
Host smart-3ca8c5af-57bf-4361-875b-32ff038a248b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107140878 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all_with_rand_reset.4107140878
Directory /workspace/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_alert_test.4119650077
Short name T588
Test name
Test status
Simulation time 422202862 ps
CPU time 0.86 seconds
Started Mar 19 12:29:33 PM PDT 24
Finished Mar 19 12:29:34 PM PDT 24
Peak memory 201544 kb
Host smart-ad652239-f149-4796-8981-44d37df59628
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119650077 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.4119650077
Directory /workspace/34.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.adc_ctrl_clock_gating.3813154068
Short name T634
Test name
Test status
Simulation time 233545846821 ps
CPU time 513.64 seconds
Started Mar 19 12:29:37 PM PDT 24
Finished Mar 19 12:38:11 PM PDT 24
Peak memory 201776 kb
Host smart-0770797a-81df-4bce-b9f3-847f0b030413
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813154068 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gat
ing.3813154068
Directory /workspace/34.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_both.2203665816
Short name T604
Test name
Test status
Simulation time 174863364448 ps
CPU time 199.87 seconds
Started Mar 19 12:29:48 PM PDT 24
Finished Mar 19 12:33:08 PM PDT 24
Peak memory 201748 kb
Host smart-83c2f8a5-f133-4690-94eb-8db04c5beff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203665816 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.2203665816
Directory /workspace/34.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt.1204852868
Short name T470
Test name
Test status
Simulation time 167054070117 ps
CPU time 416.78 seconds
Started Mar 19 12:31:29 PM PDT 24
Finished Mar 19 12:38:26 PM PDT 24
Peak memory 201760 kb
Host smart-986d239c-be13-4bae-a58d-832c378f1e9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204852868 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.1204852868
Directory /workspace/34.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt_fixed.2375466265
Short name T763
Test name
Test status
Simulation time 498343024936 ps
CPU time 328.3 seconds
Started Mar 19 12:29:44 PM PDT 24
Finished Mar 19 12:35:12 PM PDT 24
Peak memory 201728 kb
Host smart-1e346a43-93e7-4cc5-9d47-8de448d43dcc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375466265 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interru
pt_fixed.2375466265
Directory /workspace/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled.2420208064
Short name T751
Test name
Test status
Simulation time 328623001614 ps
CPU time 790.18 seconds
Started Mar 19 12:29:40 PM PDT 24
Finished Mar 19 12:42:51 PM PDT 24
Peak memory 201804 kb
Host smart-172588e8-edec-4e8b-a492-e646a29fba4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420208064 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.2420208064
Directory /workspace/34.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled_fixed.729811405
Short name T550
Test name
Test status
Simulation time 325990408201 ps
CPU time 815.22 seconds
Started Mar 19 12:29:36 PM PDT 24
Finished Mar 19 12:43:11 PM PDT 24
Peak memory 201756 kb
Host smart-34e76978-7333-4dd0-960d-2b60887410d1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=729811405 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fixe
d.729811405
Directory /workspace/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup.3785245552
Short name T782
Test name
Test status
Simulation time 554741560488 ps
CPU time 676.74 seconds
Started Mar 19 12:31:13 PM PDT 24
Finished Mar 19 12:42:30 PM PDT 24
Peak memory 200116 kb
Host smart-e86d756a-1b32-43d5-9620-cad316b813cb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785245552 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters
_wakeup.3785245552
Directory /workspace/34.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.2807256285
Short name T203
Test name
Test status
Simulation time 589693317947 ps
CPU time 401 seconds
Started Mar 19 12:29:45 PM PDT 24
Finished Mar 19 12:36:26 PM PDT 24
Peak memory 201752 kb
Host smart-bb5ca4d4-c456-4ba9-bea7-66b8006436f5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807256285 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34
.adc_ctrl_filters_wakeup_fixed.2807256285
Directory /workspace/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_fsm_reset.415404999
Short name T347
Test name
Test status
Simulation time 111395292279 ps
CPU time 339.28 seconds
Started Mar 19 12:29:58 PM PDT 24
Finished Mar 19 12:35:38 PM PDT 24
Peak memory 202052 kb
Host smart-0e58a144-ba5d-4f99-8880-cd8a7a0fc415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415404999 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.415404999
Directory /workspace/34.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_lowpower_counter.3123816827
Short name T494
Test name
Test status
Simulation time 33860264129 ps
CPU time 16.18 seconds
Started Mar 19 12:29:49 PM PDT 24
Finished Mar 19 12:30:05 PM PDT 24
Peak memory 201600 kb
Host smart-17099aa0-e664-4fcb-94e4-44c67a2dbf46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123816827 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.3123816827
Directory /workspace/34.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_poweron_counter.1420516785
Short name T670
Test name
Test status
Simulation time 3170103856 ps
CPU time 1.52 seconds
Started Mar 19 12:29:43 PM PDT 24
Finished Mar 19 12:29:45 PM PDT 24
Peak memory 201544 kb
Host smart-dd904734-697d-4602-8005-a23648d62362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420516785 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.1420516785
Directory /workspace/34.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_smoke.3346291448
Short name T391
Test name
Test status
Simulation time 5648757826 ps
CPU time 4.1 seconds
Started Mar 19 12:30:10 PM PDT 24
Finished Mar 19 12:30:15 PM PDT 24
Peak memory 201532 kb
Host smart-0b3235d3-e981-4e65-ba2e-20cbdeb73d41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346291448 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.3346291448
Directory /workspace/34.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all.2278867547
Short name T266
Test name
Test status
Simulation time 163157526364 ps
CPU time 91.02 seconds
Started Mar 19 12:29:36 PM PDT 24
Finished Mar 19 12:31:07 PM PDT 24
Peak memory 202228 kb
Host smart-2fe1fe6d-71f1-45b2-838c-011ade3ab88f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278867547 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all
.2278867547
Directory /workspace/34.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.1124460151
Short name T635
Test name
Test status
Simulation time 84300545017 ps
CPU time 173.59 seconds
Started Mar 19 12:31:29 PM PDT 24
Finished Mar 19 12:34:23 PM PDT 24
Peak memory 210320 kb
Host smart-8875f600-f830-4db5-846c-78209b51b927
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124460151 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all_with_rand_reset.1124460151
Directory /workspace/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_alert_test.2342602903
Short name T371
Test name
Test status
Simulation time 449614303 ps
CPU time 1.79 seconds
Started Mar 19 12:29:40 PM PDT 24
Finished Mar 19 12:29:41 PM PDT 24
Peak memory 201472 kb
Host smart-e0a42906-67a9-4cd5-abbe-7d7075263123
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342602903 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.2342602903
Directory /workspace/35.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.adc_ctrl_clock_gating.3794879947
Short name T645
Test name
Test status
Simulation time 350341599464 ps
CPU time 244.16 seconds
Started Mar 19 12:29:49 PM PDT 24
Finished Mar 19 12:33:53 PM PDT 24
Peak memory 201860 kb
Host smart-691ebc3b-0b0e-41f0-b492-a99b10417c9f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794879947 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gat
ing.3794879947
Directory /workspace/35.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt_fixed.1395116208
Short name T524
Test name
Test status
Simulation time 505672973730 ps
CPU time 1240.33 seconds
Started Mar 19 12:29:39 PM PDT 24
Finished Mar 19 12:50:20 PM PDT 24
Peak memory 201820 kb
Host smart-aabc83c3-05e3-4b02-ae7b-61ce49a941b2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395116208 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interru
pt_fixed.1395116208
Directory /workspace/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled.3791492283
Short name T600
Test name
Test status
Simulation time 161314836879 ps
CPU time 206.04 seconds
Started Mar 19 12:29:41 PM PDT 24
Finished Mar 19 12:33:07 PM PDT 24
Peak memory 201876 kb
Host smart-3ab14134-e9af-45fa-8e00-cf4037c7bd3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791492283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.3791492283
Directory /workspace/35.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled_fixed.1693455586
Short name T354
Test name
Test status
Simulation time 333366065245 ps
CPU time 331.47 seconds
Started Mar 19 12:29:40 PM PDT 24
Finished Mar 19 12:35:12 PM PDT 24
Peak memory 201768 kb
Host smart-700db5fd-7549-4cd8-b077-15fae048ea23
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693455586 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fix
ed.1693455586
Directory /workspace/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup.1101686612
Short name T107
Test name
Test status
Simulation time 406680491882 ps
CPU time 871.53 seconds
Started Mar 19 12:31:13 PM PDT 24
Finished Mar 19 12:45:45 PM PDT 24
Peak memory 199984 kb
Host smart-42290df2-6f20-4daf-aa55-6527069db4a7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101686612 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters
_wakeup.1101686612
Directory /workspace/35.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup_fixed.3417751714
Short name T648
Test name
Test status
Simulation time 609793666366 ps
CPU time 364.4 seconds
Started Mar 19 12:31:13 PM PDT 24
Finished Mar 19 12:37:18 PM PDT 24
Peak memory 200288 kb
Host smart-64100ec8-3d5a-4860-be89-9b04cccc22d3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417751714 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35
.adc_ctrl_filters_wakeup_fixed.3417751714
Directory /workspace/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_fsm_reset.4156702060
Short name T506
Test name
Test status
Simulation time 87024270220 ps
CPU time 307.13 seconds
Started Mar 19 12:29:50 PM PDT 24
Finished Mar 19 12:34:57 PM PDT 24
Peak memory 202196 kb
Host smart-85ad3f94-cabc-40fd-8a4d-162952086368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156702060 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.4156702060
Directory /workspace/35.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_lowpower_counter.1690813602
Short name T457
Test name
Test status
Simulation time 24363401091 ps
CPU time 15.21 seconds
Started Mar 19 12:29:36 PM PDT 24
Finished Mar 19 12:29:52 PM PDT 24
Peak memory 201608 kb
Host smart-38b17b69-3748-4d91-8103-101b5d81d805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690813602 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.1690813602
Directory /workspace/35.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_poweron_counter.503304550
Short name T88
Test name
Test status
Simulation time 3722534239 ps
CPU time 2.99 seconds
Started Mar 19 12:31:13 PM PDT 24
Finished Mar 19 12:31:16 PM PDT 24
Peak memory 199680 kb
Host smart-dc1529d1-5947-44c6-87ab-ddeda60e9398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503304550 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.503304550
Directory /workspace/35.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_smoke.2177074550
Short name T369
Test name
Test status
Simulation time 5803391011 ps
CPU time 14.67 seconds
Started Mar 19 12:29:50 PM PDT 24
Finished Mar 19 12:30:04 PM PDT 24
Peak memory 201644 kb
Host smart-e40c08af-5074-4481-842f-ca2ebda2dcc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177074550 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.2177074550
Directory /workspace/35.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.adc_ctrl_alert_test.1490051425
Short name T447
Test name
Test status
Simulation time 568231313 ps
CPU time 0.85 seconds
Started Mar 19 12:29:46 PM PDT 24
Finished Mar 19 12:29:47 PM PDT 24
Peak memory 201432 kb
Host smart-eb6c3fcd-73af-4302-b21c-4d11f2f28197
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490051425 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.1490051425
Directory /workspace/36.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.adc_ctrl_clock_gating.4154159147
Short name T679
Test name
Test status
Simulation time 330418276536 ps
CPU time 194 seconds
Started Mar 19 12:29:47 PM PDT 24
Finished Mar 19 12:33:01 PM PDT 24
Peak memory 201724 kb
Host smart-d376f5c8-7e3f-4aa9-ba5b-9fc60ea69eaa
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154159147 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gat
ing.4154159147
Directory /workspace/36.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt.3636007623
Short name T186
Test name
Test status
Simulation time 496274771150 ps
CPU time 325 seconds
Started Mar 19 12:29:36 PM PDT 24
Finished Mar 19 12:35:01 PM PDT 24
Peak memory 201840 kb
Host smart-b82712ce-464d-4644-9cf3-c4b12f673d2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636007623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.3636007623
Directory /workspace/36.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.3875627728
Short name T174
Test name
Test status
Simulation time 338430454718 ps
CPU time 851.08 seconds
Started Mar 19 12:29:53 PM PDT 24
Finished Mar 19 12:44:04 PM PDT 24
Peak memory 201752 kb
Host smart-0d835d85-6db3-4779-9263-17f7baf3d4a9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875627728 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interru
pt_fixed.3875627728
Directory /workspace/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled.1653366621
Short name T182
Test name
Test status
Simulation time 507176056977 ps
CPU time 1074.36 seconds
Started Mar 19 12:29:40 PM PDT 24
Finished Mar 19 12:47:35 PM PDT 24
Peak memory 201740 kb
Host smart-4488cdef-1259-40cc-a07a-a9b944615561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653366621 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.1653366621
Directory /workspace/36.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled_fixed.3735365988
Short name T779
Test name
Test status
Simulation time 166308577568 ps
CPU time 203.99 seconds
Started Mar 19 12:29:39 PM PDT 24
Finished Mar 19 12:33:03 PM PDT 24
Peak memory 201784 kb
Host smart-fd2d321a-52f6-48dd-853d-b7a273a73964
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735365988 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fix
ed.3735365988
Directory /workspace/36.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup.382540137
Short name T265
Test name
Test status
Simulation time 186458961357 ps
CPU time 377.57 seconds
Started Mar 19 12:29:41 PM PDT 24
Finished Mar 19 12:35:59 PM PDT 24
Peak memory 201832 kb
Host smart-38c643f0-cc6c-453c-88f6-649e485e0767
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382540137 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_
wakeup.382540137
Directory /workspace/36.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup_fixed.3788997129
Short name T386
Test name
Test status
Simulation time 612096803356 ps
CPU time 392.83 seconds
Started Mar 19 12:29:36 PM PDT 24
Finished Mar 19 12:36:09 PM PDT 24
Peak memory 201864 kb
Host smart-74c6e340-1d00-458d-9b29-8e7064f32eab
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788997129 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36
.adc_ctrl_filters_wakeup_fixed.3788997129
Directory /workspace/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_fsm_reset.3874295260
Short name T211
Test name
Test status
Simulation time 86922615175 ps
CPU time 514.89 seconds
Started Mar 19 12:29:47 PM PDT 24
Finished Mar 19 12:38:22 PM PDT 24
Peak memory 202120 kb
Host smart-99903551-e7db-4561-99da-b85e5fe328d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874295260 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.3874295260
Directory /workspace/36.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_lowpower_counter.2377623634
Short name T32
Test name
Test status
Simulation time 29081942928 ps
CPU time 11.29 seconds
Started Mar 19 12:29:46 PM PDT 24
Finished Mar 19 12:29:57 PM PDT 24
Peak memory 201576 kb
Host smart-048b1eef-0029-44be-bf3d-23ba0df479b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377623634 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.2377623634
Directory /workspace/36.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_poweron_counter.3374147053
Short name T377
Test name
Test status
Simulation time 5201369747 ps
CPU time 4.15 seconds
Started Mar 19 12:29:43 PM PDT 24
Finished Mar 19 12:29:47 PM PDT 24
Peak memory 201584 kb
Host smart-6dd21a9e-c513-4b16-90af-12c2409e543c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374147053 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.3374147053
Directory /workspace/36.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_smoke.3594271602
Short name T762
Test name
Test status
Simulation time 5760069765 ps
CPU time 4.76 seconds
Started Mar 19 12:29:42 PM PDT 24
Finished Mar 19 12:29:47 PM PDT 24
Peak memory 201552 kb
Host smart-4239dd3f-5831-4b8a-b018-ef7c3e3fadf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594271602 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.3594271602
Directory /workspace/36.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all.2259910003
Short name T459
Test name
Test status
Simulation time 368229261114 ps
CPU time 854.93 seconds
Started Mar 19 12:29:39 PM PDT 24
Finished Mar 19 12:43:54 PM PDT 24
Peak memory 201732 kb
Host smart-6e615061-ccef-4fc8-96d5-968d4674558a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259910003 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all
.2259910003
Directory /workspace/36.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.519000236
Short name T24
Test name
Test status
Simulation time 50541998645 ps
CPU time 31.22 seconds
Started Mar 19 12:29:40 PM PDT 24
Finished Mar 19 12:30:16 PM PDT 24
Peak memory 210108 kb
Host smart-ffe95017-24fe-45dd-9d97-f45b469943f5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519000236 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all_with_rand_reset.519000236
Directory /workspace/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_alert_test.3753242781
Short name T454
Test name
Test status
Simulation time 312997021 ps
CPU time 1.33 seconds
Started Mar 19 12:29:53 PM PDT 24
Finished Mar 19 12:29:55 PM PDT 24
Peak memory 201472 kb
Host smart-7c606290-a6a7-41c7-9da0-5f35532d11c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753242781 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.3753242781
Directory /workspace/37.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt_fixed.3092505569
Short name T533
Test name
Test status
Simulation time 490221275833 ps
CPU time 146.23 seconds
Started Mar 19 12:29:44 PM PDT 24
Finished Mar 19 12:32:10 PM PDT 24
Peak memory 201752 kb
Host smart-6f934fab-bc99-4d32-a7ad-35d412df0be0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092505569 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interru
pt_fixed.3092505569
Directory /workspace/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled.1870853521
Short name T111
Test name
Test status
Simulation time 328810915590 ps
CPU time 194.68 seconds
Started Mar 19 12:29:40 PM PDT 24
Finished Mar 19 12:32:55 PM PDT 24
Peak memory 201756 kb
Host smart-448d4ac4-4212-47df-bf46-3a0769f0dea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870853521 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.1870853521
Directory /workspace/37.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.1872353263
Short name T97
Test name
Test status
Simulation time 158110746161 ps
CPU time 96.76 seconds
Started Mar 19 12:29:45 PM PDT 24
Finished Mar 19 12:31:22 PM PDT 24
Peak memory 201796 kb
Host smart-e1dc9b29-954a-44b8-97dd-9bfcdeed754a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872353263 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fix
ed.1872353263
Directory /workspace/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup.3900715513
Short name T257
Test name
Test status
Simulation time 545136587770 ps
CPU time 693.85 seconds
Started Mar 19 12:29:42 PM PDT 24
Finished Mar 19 12:41:16 PM PDT 24
Peak memory 201776 kb
Host smart-328065f2-cce8-47c8-a2dc-208272edd929
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900715513 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters
_wakeup.3900715513
Directory /workspace/37.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup_fixed.2096033114
Short name T86
Test name
Test status
Simulation time 411508034800 ps
CPU time 999.94 seconds
Started Mar 19 12:29:45 PM PDT 24
Finished Mar 19 12:46:26 PM PDT 24
Peak memory 201724 kb
Host smart-1aa533c3-8ccb-4433-9e68-af9a6063e71b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096033114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37
.adc_ctrl_filters_wakeup_fixed.2096033114
Directory /workspace/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_fsm_reset.2762441437
Short name T346
Test name
Test status
Simulation time 108477998791 ps
CPU time 547.56 seconds
Started Mar 19 12:29:53 PM PDT 24
Finished Mar 19 12:39:01 PM PDT 24
Peak memory 202056 kb
Host smart-c3ab0b77-14f2-4493-bc2e-e90c8d42630a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762441437 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.2762441437
Directory /workspace/37.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_lowpower_counter.2281790754
Short name T565
Test name
Test status
Simulation time 22319380823 ps
CPU time 6.94 seconds
Started Mar 19 12:29:45 PM PDT 24
Finished Mar 19 12:29:52 PM PDT 24
Peak memory 201568 kb
Host smart-0e573cbc-8a82-48d9-8443-9f90ff9d067f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281790754 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.2281790754
Directory /workspace/37.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_poweron_counter.2780939446
Short name T173
Test name
Test status
Simulation time 3906788106 ps
CPU time 2.93 seconds
Started Mar 19 12:29:42 PM PDT 24
Finished Mar 19 12:29:45 PM PDT 24
Peak memory 201576 kb
Host smart-a4d0f6f9-a755-4c47-bdc4-b73fa9665550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780939446 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.2780939446
Directory /workspace/37.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_smoke.109507085
Short name T456
Test name
Test status
Simulation time 5857258271 ps
CPU time 13.67 seconds
Started Mar 19 12:29:49 PM PDT 24
Finished Mar 19 12:30:03 PM PDT 24
Peak memory 201696 kb
Host smart-c4f5c0ba-5c6f-47cb-a0cf-9246343f8264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109507085 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.109507085
Directory /workspace/37.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all.606113905
Short name T745
Test name
Test status
Simulation time 240933514405 ps
CPU time 382.32 seconds
Started Mar 19 12:29:42 PM PDT 24
Finished Mar 19 12:36:09 PM PDT 24
Peak memory 211992 kb
Host smart-aa3a490b-9029-465d-a419-f172fa0095da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606113905 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all.
606113905
Directory /workspace/37.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.1267706395
Short name T43
Test name
Test status
Simulation time 285610660302 ps
CPU time 272.46 seconds
Started Mar 19 12:29:45 PM PDT 24
Finished Mar 19 12:34:17 PM PDT 24
Peak memory 210400 kb
Host smart-7dbaec14-5114-4fe4-b107-4ee1944d4140
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267706395 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.1267706395
Directory /workspace/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_alert_test.658932977
Short name T553
Test name
Test status
Simulation time 418132399 ps
CPU time 0.81 seconds
Started Mar 19 12:29:42 PM PDT 24
Finished Mar 19 12:29:43 PM PDT 24
Peak memory 201444 kb
Host smart-e8bf6426-25e3-47ca-a2d8-8478b50fd00c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658932977 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.658932977
Directory /workspace/38.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.adc_ctrl_clock_gating.2953575539
Short name T535
Test name
Test status
Simulation time 194149895519 ps
CPU time 480.17 seconds
Started Mar 19 12:29:46 PM PDT 24
Finished Mar 19 12:37:46 PM PDT 24
Peak memory 201832 kb
Host smart-bf3ba1a4-924a-40f3-b960-0a50ff5cb771
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953575539 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gat
ing.2953575539
Directory /workspace/38.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_both.3333408489
Short name T225
Test name
Test status
Simulation time 367798034574 ps
CPU time 866.97 seconds
Started Mar 19 12:29:40 PM PDT 24
Finished Mar 19 12:44:07 PM PDT 24
Peak memory 201832 kb
Host smart-2e63889c-cf2f-4e5a-a128-ba53a57d27a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333408489 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.3333408489
Directory /workspace/38.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt.1422238228
Short name T227
Test name
Test status
Simulation time 486959654764 ps
CPU time 1156.93 seconds
Started Mar 19 12:29:45 PM PDT 24
Finished Mar 19 12:49:02 PM PDT 24
Peak memory 201776 kb
Host smart-2b07ccc1-169b-4788-ad6d-8dc9e881572d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422238228 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.1422238228
Directory /workspace/38.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt_fixed.1759002546
Short name T101
Test name
Test status
Simulation time 159971114421 ps
CPU time 353.81 seconds
Started Mar 19 12:29:46 PM PDT 24
Finished Mar 19 12:35:40 PM PDT 24
Peak memory 201792 kb
Host smart-c2cb9fe7-dc64-4bf6-86c6-74b5d71ac39d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759002546 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interru
pt_fixed.1759002546
Directory /workspace/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled_fixed.653800879
Short name T197
Test name
Test status
Simulation time 332042738095 ps
CPU time 197.88 seconds
Started Mar 19 12:29:37 PM PDT 24
Finished Mar 19 12:32:55 PM PDT 24
Peak memory 201788 kb
Host smart-efebc58f-39e6-421c-8ea6-313c9068b144
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=653800879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fixe
d.653800879
Directory /workspace/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup_fixed.4085857837
Short name T582
Test name
Test status
Simulation time 611064448660 ps
CPU time 1061.64 seconds
Started Mar 19 12:29:43 PM PDT 24
Finished Mar 19 12:47:25 PM PDT 24
Peak memory 201808 kb
Host smart-73b85b85-ac29-42f8-91b6-b540d32150c6
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085857837 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38
.adc_ctrl_filters_wakeup_fixed.4085857837
Directory /workspace/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_fsm_reset.3059497431
Short name T410
Test name
Test status
Simulation time 83273913027 ps
CPU time 285.2 seconds
Started Mar 19 12:29:43 PM PDT 24
Finished Mar 19 12:34:28 PM PDT 24
Peak memory 202048 kb
Host smart-6e8491cb-ab38-41ab-8ae8-f6449e6a4acb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059497431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.3059497431
Directory /workspace/38.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_lowpower_counter.102273517
Short name T415
Test name
Test status
Simulation time 37138723591 ps
CPU time 87.51 seconds
Started Mar 19 12:29:47 PM PDT 24
Finished Mar 19 12:31:15 PM PDT 24
Peak memory 201580 kb
Host smart-4a759243-e9d6-4054-aa1a-6a465e99defb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102273517 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.102273517
Directory /workspace/38.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_poweron_counter.2870800392
Short name T498
Test name
Test status
Simulation time 4032716091 ps
CPU time 1.93 seconds
Started Mar 19 12:29:39 PM PDT 24
Finished Mar 19 12:29:41 PM PDT 24
Peak memory 201568 kb
Host smart-107609ee-c66c-482a-8268-79ebe427d422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870800392 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.2870800392
Directory /workspace/38.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_smoke.641796289
Short name T511
Test name
Test status
Simulation time 6064001284 ps
CPU time 6.91 seconds
Started Mar 19 12:29:50 PM PDT 24
Finished Mar 19 12:29:57 PM PDT 24
Peak memory 201572 kb
Host smart-c3c4add8-7dba-41ee-a90c-48b5c92198fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641796289 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.641796289
Directory /workspace/38.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all.192499394
Short name T529
Test name
Test status
Simulation time 699974044715 ps
CPU time 406.57 seconds
Started Mar 19 12:29:45 PM PDT 24
Finished Mar 19 12:36:32 PM PDT 24
Peak memory 201792 kb
Host smart-36a530d7-2b03-408b-a1ad-87e3b1e7168e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192499394 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all.
192499394
Directory /workspace/38.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.1707592719
Short name T243
Test name
Test status
Simulation time 95374078559 ps
CPU time 54.76 seconds
Started Mar 19 12:29:50 PM PDT 24
Finished Mar 19 12:30:45 PM PDT 24
Peak memory 202020 kb
Host smart-87ab3058-6f19-4642-ae74-8610c7ddb869
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707592719 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all_with_rand_reset.1707592719
Directory /workspace/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_alert_test.2907842446
Short name T587
Test name
Test status
Simulation time 579324476 ps
CPU time 0.67 seconds
Started Mar 19 12:29:52 PM PDT 24
Finished Mar 19 12:29:53 PM PDT 24
Peak memory 201472 kb
Host smart-614d3b0e-cf47-4721-96e0-3971063a32db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907842446 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.2907842446
Directory /workspace/39.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.adc_ctrl_clock_gating.501154204
Short name T334
Test name
Test status
Simulation time 327655627769 ps
CPU time 684.06 seconds
Started Mar 19 12:29:50 PM PDT 24
Finished Mar 19 12:41:14 PM PDT 24
Peak memory 201800 kb
Host smart-795e00f8-30c8-4f3c-9ab9-2532c5451bb4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501154204 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gati
ng.501154204
Directory /workspace/39.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_both.790263526
Short name T278
Test name
Test status
Simulation time 333149437355 ps
CPU time 111.81 seconds
Started Mar 19 12:30:03 PM PDT 24
Finished Mar 19 12:31:55 PM PDT 24
Peak memory 201768 kb
Host smart-4c19cede-290d-471b-b4d3-7fdfe304c89f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790263526 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.790263526
Directory /workspace/39.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt.3479820788
Short name T153
Test name
Test status
Simulation time 496285098412 ps
CPU time 1073.85 seconds
Started Mar 19 12:29:52 PM PDT 24
Finished Mar 19 12:47:46 PM PDT 24
Peak memory 201892 kb
Host smart-c0149eed-7415-4e26-a429-0fff98d65029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479820788 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.3479820788
Directory /workspace/39.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt_fixed.3203071368
Short name T462
Test name
Test status
Simulation time 164595253335 ps
CPU time 53.26 seconds
Started Mar 19 12:31:29 PM PDT 24
Finished Mar 19 12:32:23 PM PDT 24
Peak memory 201480 kb
Host smart-bc8c21d3-c469-45fe-894c-564d21d52a73
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203071368 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interru
pt_fixed.3203071368
Directory /workspace/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled.2420481099
Short name T196
Test name
Test status
Simulation time 334377517228 ps
CPU time 161.38 seconds
Started Mar 19 12:30:05 PM PDT 24
Finished Mar 19 12:32:47 PM PDT 24
Peak memory 201752 kb
Host smart-fde58601-8293-4fbb-ab28-34d1f36327df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420481099 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.2420481099
Directory /workspace/39.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled_fixed.3332583180
Short name T764
Test name
Test status
Simulation time 327070670138 ps
CPU time 161.82 seconds
Started Mar 19 12:29:38 PM PDT 24
Finished Mar 19 12:32:20 PM PDT 24
Peak memory 202132 kb
Host smart-53fe794b-59dc-49da-88ce-8ace81859458
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332583180 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fix
ed.3332583180
Directory /workspace/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup.2898984042
Short name T727
Test name
Test status
Simulation time 353213567057 ps
CPU time 433.75 seconds
Started Mar 19 12:29:50 PM PDT 24
Finished Mar 19 12:37:04 PM PDT 24
Peak memory 201788 kb
Host smart-180df010-ccdc-4f68-a8ce-e76a991164ff
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898984042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters
_wakeup.2898984042
Directory /workspace/39.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.268731014
Short name T576
Test name
Test status
Simulation time 623329956681 ps
CPU time 1611.94 seconds
Started Mar 19 12:29:48 PM PDT 24
Finished Mar 19 12:56:40 PM PDT 24
Peak memory 201740 kb
Host smart-eb4f06c3-26ed-453e-a3e4-f70d141f78f0
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268731014 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
adc_ctrl_filters_wakeup_fixed.268731014
Directory /workspace/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_fsm_reset.3170894096
Short name T784
Test name
Test status
Simulation time 89157280462 ps
CPU time 276.98 seconds
Started Mar 19 12:29:50 PM PDT 24
Finished Mar 19 12:34:27 PM PDT 24
Peak memory 202056 kb
Host smart-693b90cf-e140-4219-8b41-85aa48a4055b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170894096 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.3170894096
Directory /workspace/39.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_lowpower_counter.1905481476
Short name T608
Test name
Test status
Simulation time 32103033557 ps
CPU time 73.11 seconds
Started Mar 19 12:29:49 PM PDT 24
Finished Mar 19 12:31:02 PM PDT 24
Peak memory 201564 kb
Host smart-d519c480-a616-4576-9d29-63946f3ed36e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905481476 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.1905481476
Directory /workspace/39.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_poweron_counter.1983032321
Short name T638
Test name
Test status
Simulation time 4650869732 ps
CPU time 10.53 seconds
Started Mar 19 12:29:47 PM PDT 24
Finished Mar 19 12:29:58 PM PDT 24
Peak memory 201624 kb
Host smart-14cd0ebb-c927-4eff-98cf-18e749889dfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983032321 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.1983032321
Directory /workspace/39.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_smoke.3829805289
Short name T777
Test name
Test status
Simulation time 5652819804 ps
CPU time 2.9 seconds
Started Mar 19 12:29:49 PM PDT 24
Finished Mar 19 12:29:52 PM PDT 24
Peak memory 201588 kb
Host smart-bc338e3f-28c4-4f85-91ef-8c80d97c2714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829805289 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.3829805289
Directory /workspace/39.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all.2264903468
Short name T85
Test name
Test status
Simulation time 161006442823 ps
CPU time 174.77 seconds
Started Mar 19 12:29:50 PM PDT 24
Finished Mar 19 12:32:45 PM PDT 24
Peak memory 201876 kb
Host smart-05f7d8b1-7677-4832-b5a7-b6b85cc71dbf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264903468 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all
.2264903468
Directory /workspace/39.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.adc_ctrl_alert_test.2558436983
Short name T541
Test name
Test status
Simulation time 444564227 ps
CPU time 1.11 seconds
Started Mar 19 12:28:49 PM PDT 24
Finished Mar 19 12:28:51 PM PDT 24
Peak memory 201516 kb
Host smart-dbfe8d03-a792-4687-8f23-663b28168aa3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558436983 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.2558436983
Directory /workspace/4.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.adc_ctrl_clock_gating.3229450385
Short name T159
Test name
Test status
Simulation time 354888838262 ps
CPU time 828.35 seconds
Started Mar 19 12:28:48 PM PDT 24
Finished Mar 19 12:42:36 PM PDT 24
Peak memory 201720 kb
Host smart-b1fe42f4-8b5f-40d1-95d5-888a1f1b8f80
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229450385 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gati
ng.3229450385
Directory /workspace/4.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_both.3528513343
Short name T455
Test name
Test status
Simulation time 162160030386 ps
CPU time 188.98 seconds
Started Mar 19 12:28:55 PM PDT 24
Finished Mar 19 12:32:04 PM PDT 24
Peak memory 201748 kb
Host smart-4e5703cf-2e95-449e-9017-993db10df875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528513343 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.3528513343
Directory /workspace/4.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt.4270513903
Short name T241
Test name
Test status
Simulation time 336168194007 ps
CPU time 216.38 seconds
Started Mar 19 12:28:43 PM PDT 24
Finished Mar 19 12:32:20 PM PDT 24
Peak memory 201720 kb
Host smart-2942ff35-d6ff-4ad5-9d3a-fd54d38f050c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270513903 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.4270513903
Directory /workspace/4.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt_fixed.3265911940
Short name T703
Test name
Test status
Simulation time 163184380355 ps
CPU time 41.32 seconds
Started Mar 19 12:28:42 PM PDT 24
Finished Mar 19 12:29:24 PM PDT 24
Peak memory 201716 kb
Host smart-9c252b35-c396-4448-9462-8563807a8797
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265911940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrup
t_fixed.3265911940
Directory /workspace/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled_fixed.1135694326
Short name T417
Test name
Test status
Simulation time 325348115171 ps
CPU time 67.6 seconds
Started Mar 19 12:28:49 PM PDT 24
Finished Mar 19 12:29:57 PM PDT 24
Peak memory 201716 kb
Host smart-ce6da059-0273-4071-9ff5-9d52c7367a96
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135694326 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixe
d.1135694326
Directory /workspace/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup.2982064927
Short name T326
Test name
Test status
Simulation time 365715477033 ps
CPU time 437.09 seconds
Started Mar 19 12:29:06 PM PDT 24
Finished Mar 19 12:36:23 PM PDT 24
Peak memory 201816 kb
Host smart-423ad6c8-0855-49d6-93e5-4bfb0639c3ab
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982064927 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_
wakeup.2982064927
Directory /workspace/4.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup_fixed.161465454
Short name T363
Test name
Test status
Simulation time 187600321033 ps
CPU time 417.08 seconds
Started Mar 19 12:28:57 PM PDT 24
Finished Mar 19 12:35:55 PM PDT 24
Peak memory 201728 kb
Host smart-bd802df7-497c-4ac3-bd2e-58e75dbd6e65
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161465454 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.a
dc_ctrl_filters_wakeup_fixed.161465454
Directory /workspace/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_fsm_reset.3334880755
Short name T480
Test name
Test status
Simulation time 115179102013 ps
CPU time 414.25 seconds
Started Mar 19 12:28:53 PM PDT 24
Finished Mar 19 12:35:48 PM PDT 24
Peak memory 202036 kb
Host smart-19a5c76e-52e1-4044-a02d-0ba0825cada0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334880755 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.3334880755
Directory /workspace/4.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_lowpower_counter.663557484
Short name T492
Test name
Test status
Simulation time 37891101121 ps
CPU time 35.21 seconds
Started Mar 19 12:28:45 PM PDT 24
Finished Mar 19 12:29:20 PM PDT 24
Peak memory 201452 kb
Host smart-3f8a0408-84a1-4606-8efd-eb2c89ecb525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663557484 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.663557484
Directory /workspace/4.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_poweron_counter.3422841780
Short name T364
Test name
Test status
Simulation time 2952666946 ps
CPU time 7.88 seconds
Started Mar 19 12:29:02 PM PDT 24
Finished Mar 19 12:29:10 PM PDT 24
Peak memory 201556 kb
Host smart-d489179f-585a-413a-98bb-9ac1a622eb69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422841780 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.3422841780
Directory /workspace/4.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_sec_cm.297033861
Short name T68
Test name
Test status
Simulation time 4093925986 ps
CPU time 2.35 seconds
Started Mar 19 12:28:53 PM PDT 24
Finished Mar 19 12:28:56 PM PDT 24
Peak memory 217232 kb
Host smart-bd1f6234-2c68-42fd-87d3-f2912c7c8171
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297033861 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.297033861
Directory /workspace/4.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.adc_ctrl_smoke.2043064508
Short name T439
Test name
Test status
Simulation time 5750767864 ps
CPU time 14.68 seconds
Started Mar 19 12:29:30 PM PDT 24
Finished Mar 19 12:29:45 PM PDT 24
Peak memory 201588 kb
Host smart-ba943695-e3c3-48c6-a293-cbbfd0abbc32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043064508 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.2043064508
Directory /workspace/4.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all.233888926
Short name T654
Test name
Test status
Simulation time 229202460511 ps
CPU time 131.08 seconds
Started Mar 19 12:28:43 PM PDT 24
Finished Mar 19 12:30:54 PM PDT 24
Peak memory 201704 kb
Host smart-75d880f3-877d-4528-829a-1cc4f2482071
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233888926 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.233888926
Directory /workspace/4.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.adc_ctrl_alert_test.338621504
Short name T82
Test name
Test status
Simulation time 407049805 ps
CPU time 1.62 seconds
Started Mar 19 12:29:50 PM PDT 24
Finished Mar 19 12:29:52 PM PDT 24
Peak memory 201460 kb
Host smart-6128da2d-9479-46e6-95f5-2ac4914c6905
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338621504 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.338621504
Directory /workspace/40.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.adc_ctrl_clock_gating.359365463
Short name T261
Test name
Test status
Simulation time 517788064541 ps
CPU time 628.61 seconds
Started Mar 19 12:30:06 PM PDT 24
Finished Mar 19 12:40:35 PM PDT 24
Peak memory 201824 kb
Host smart-039df37a-56c0-4294-bac9-2d60d9cace89
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359365463 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gati
ng.359365463
Directory /workspace/40.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_both.4029460450
Short name T728
Test name
Test status
Simulation time 501873222866 ps
CPU time 82.63 seconds
Started Mar 19 12:29:47 PM PDT 24
Finished Mar 19 12:31:10 PM PDT 24
Peak memory 201800 kb
Host smart-998483a7-aba7-4cb4-9831-38df2ad664a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029460450 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.4029460450
Directory /workspace/40.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt.67648591
Short name T739
Test name
Test status
Simulation time 328269826642 ps
CPU time 109.84 seconds
Started Mar 19 12:29:54 PM PDT 24
Finished Mar 19 12:31:44 PM PDT 24
Peak memory 201808 kb
Host smart-ec444a3c-9d56-44de-b513-660c5e728dc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67648591 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.67648591
Directory /workspace/40.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt_fixed.4149580707
Short name T367
Test name
Test status
Simulation time 327233939666 ps
CPU time 198.14 seconds
Started Mar 19 12:29:51 PM PDT 24
Finished Mar 19 12:33:10 PM PDT 24
Peak memory 201792 kb
Host smart-583e7b1b-1b24-4f65-9ee1-067fb16dc6fb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149580707 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interru
pt_fixed.4149580707
Directory /workspace/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled.2342893017
Short name T611
Test name
Test status
Simulation time 502811415915 ps
CPU time 729.45 seconds
Started Mar 19 12:30:05 PM PDT 24
Finished Mar 19 12:42:14 PM PDT 24
Peak memory 201820 kb
Host smart-fe497c73-c22d-4b66-a160-2f41d5be03c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342893017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.2342893017
Directory /workspace/40.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled_fixed.2773732243
Short name T501
Test name
Test status
Simulation time 161038606036 ps
CPU time 362.62 seconds
Started Mar 19 12:29:49 PM PDT 24
Finished Mar 19 12:35:52 PM PDT 24
Peak memory 201880 kb
Host smart-f9b96f34-bd9b-4e04-a240-e755d8b2a805
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773732243 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fix
ed.2773732243
Directory /workspace/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup.1409033677
Short name T154
Test name
Test status
Simulation time 361840959358 ps
CPU time 921.29 seconds
Started Mar 19 12:30:05 PM PDT 24
Finished Mar 19 12:45:27 PM PDT 24
Peak memory 201764 kb
Host smart-196f64d5-fca2-499b-880e-8a6b197ea9d3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409033677 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters
_wakeup.1409033677
Directory /workspace/40.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup_fixed.3721381351
Short name T766
Test name
Test status
Simulation time 187151448778 ps
CPU time 455.44 seconds
Started Mar 19 12:29:55 PM PDT 24
Finished Mar 19 12:37:31 PM PDT 24
Peak memory 201732 kb
Host smart-a9d0b3ba-73fb-4574-b491-2ac685b8dbbb
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721381351 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40
.adc_ctrl_filters_wakeup_fixed.3721381351
Directory /workspace/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_fsm_reset.3723635484
Short name T212
Test name
Test status
Simulation time 75791027652 ps
CPU time 191.16 seconds
Started Mar 19 12:29:52 PM PDT 24
Finished Mar 19 12:33:03 PM PDT 24
Peak memory 202028 kb
Host smart-33bca603-fdb7-46d8-9d49-da73db50b3a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723635484 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.3723635484
Directory /workspace/40.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_lowpower_counter.2578698814
Short name T497
Test name
Test status
Simulation time 33882354582 ps
CPU time 44.28 seconds
Started Mar 19 12:30:02 PM PDT 24
Finished Mar 19 12:30:47 PM PDT 24
Peak memory 201568 kb
Host smart-ef72d2cc-18ab-431c-81f7-c6ecd81b07e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578698814 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.2578698814
Directory /workspace/40.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_poweron_counter.2070255560
Short name T540
Test name
Test status
Simulation time 4277578554 ps
CPU time 4.26 seconds
Started Mar 19 12:29:54 PM PDT 24
Finished Mar 19 12:29:58 PM PDT 24
Peak memory 201568 kb
Host smart-ef282707-0f32-46e8-af60-315cf1fc417b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070255560 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.2070255560
Directory /workspace/40.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_smoke.3008870009
Short name T378
Test name
Test status
Simulation time 6133169329 ps
CPU time 4.44 seconds
Started Mar 19 12:30:05 PM PDT 24
Finished Mar 19 12:30:09 PM PDT 24
Peak memory 201588 kb
Host smart-71fec201-f21b-4c19-b483-5af172148972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008870009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.3008870009
Directory /workspace/40.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.1480050785
Short name T625
Test name
Test status
Simulation time 112509818223 ps
CPU time 192.43 seconds
Started Mar 19 12:29:54 PM PDT 24
Finished Mar 19 12:33:07 PM PDT 24
Peak memory 211448 kb
Host smart-31111314-a04f-4088-b6b8-a288724cdc78
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480050785 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all_with_rand_reset.1480050785
Directory /workspace/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_alert_test.3855037288
Short name T103
Test name
Test status
Simulation time 504410987 ps
CPU time 1.7 seconds
Started Mar 19 12:29:56 PM PDT 24
Finished Mar 19 12:29:58 PM PDT 24
Peak memory 201456 kb
Host smart-72ff39a7-2e2e-4a46-9580-f4898f6c532c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855037288 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.3855037288
Directory /workspace/41.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.adc_ctrl_clock_gating.3919698503
Short name T269
Test name
Test status
Simulation time 167971439479 ps
CPU time 392.58 seconds
Started Mar 19 12:30:05 PM PDT 24
Finished Mar 19 12:36:38 PM PDT 24
Peak memory 201736 kb
Host smart-9c1c70b5-1b32-4ca1-88dd-1397359fd44b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919698503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gat
ing.3919698503
Directory /workspace/41.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_both.4127568005
Short name T619
Test name
Test status
Simulation time 512456891374 ps
CPU time 1197.66 seconds
Started Mar 19 12:30:10 PM PDT 24
Finished Mar 19 12:50:08 PM PDT 24
Peak memory 201760 kb
Host smart-86e9adae-3582-4bd8-9c56-4feee0cc3b0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127568005 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.4127568005
Directory /workspace/41.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt.663545522
Short name T282
Test name
Test status
Simulation time 164630101568 ps
CPU time 218.3 seconds
Started Mar 19 12:30:01 PM PDT 24
Finished Mar 19 12:33:40 PM PDT 24
Peak memory 201824 kb
Host smart-24715d73-7f09-45ad-bbe9-6afd49f7bf17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663545522 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.663545522
Directory /workspace/41.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt_fixed.1723811651
Short name T737
Test name
Test status
Simulation time 164096739053 ps
CPU time 375.43 seconds
Started Mar 19 12:30:06 PM PDT 24
Finished Mar 19 12:36:22 PM PDT 24
Peak memory 201732 kb
Host smart-bd348e3b-38c1-4f0e-afdb-5814e741b3e0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723811651 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interru
pt_fixed.1723811651
Directory /workspace/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled.2505061842
Short name T308
Test name
Test status
Simulation time 327257566238 ps
CPU time 352.99 seconds
Started Mar 19 12:30:01 PM PDT 24
Finished Mar 19 12:35:54 PM PDT 24
Peak memory 201800 kb
Host smart-9103d11f-09c9-4608-91c0-7f2d3cce6b54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505061842 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.2505061842
Directory /workspace/41.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled_fixed.3872928738
Short name T2
Test name
Test status
Simulation time 163524431858 ps
CPU time 94.95 seconds
Started Mar 19 12:29:57 PM PDT 24
Finished Mar 19 12:31:33 PM PDT 24
Peak memory 201848 kb
Host smart-2bf12093-19bc-4ee1-9153-4439f5ed3c50
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872928738 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fix
ed.3872928738
Directory /workspace/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup.2889360518
Short name T544
Test name
Test status
Simulation time 177883254031 ps
CPU time 237.83 seconds
Started Mar 19 12:29:53 PM PDT 24
Finished Mar 19 12:33:51 PM PDT 24
Peak memory 201804 kb
Host smart-dbcc2a67-2412-41f2-b285-a581165f5246
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889360518 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters
_wakeup.2889360518
Directory /workspace/41.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.3629493826
Short name T362
Test name
Test status
Simulation time 621966103872 ps
CPU time 1384.76 seconds
Started Mar 19 12:29:54 PM PDT 24
Finished Mar 19 12:52:59 PM PDT 24
Peak memory 201808 kb
Host smart-a9bfa824-b27b-4715-b5be-4e6ee513243e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629493826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41
.adc_ctrl_filters_wakeup_fixed.3629493826
Directory /workspace/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_fsm_reset.3359913430
Short name T343
Test name
Test status
Simulation time 116201240364 ps
CPU time 434.59 seconds
Started Mar 19 12:30:08 PM PDT 24
Finished Mar 19 12:37:24 PM PDT 24
Peak memory 202052 kb
Host smart-617d35c3-4153-4c46-83d5-066757396cfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359913430 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.3359913430
Directory /workspace/41.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_lowpower_counter.445551844
Short name T10
Test name
Test status
Simulation time 32871642400 ps
CPU time 20.76 seconds
Started Mar 19 12:29:57 PM PDT 24
Finished Mar 19 12:30:18 PM PDT 24
Peak memory 201568 kb
Host smart-70479a37-b423-4d1d-9a54-05384a803770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445551844 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.445551844
Directory /workspace/41.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_poweron_counter.2096817103
Short name T598
Test name
Test status
Simulation time 3252795283 ps
CPU time 2.74 seconds
Started Mar 19 12:29:59 PM PDT 24
Finished Mar 19 12:30:02 PM PDT 24
Peak memory 201560 kb
Host smart-894d48f0-ce59-4e50-b6ec-bf84b62741a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096817103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.2096817103
Directory /workspace/41.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_smoke.323470060
Short name T508
Test name
Test status
Simulation time 5961837044 ps
CPU time 13.46 seconds
Started Mar 19 12:30:00 PM PDT 24
Finished Mar 19 12:30:15 PM PDT 24
Peak memory 201588 kb
Host smart-3e7dd829-8efd-4ef3-8ad6-f97b7aa84bb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323470060 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.323470060
Directory /workspace/41.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.adc_ctrl_alert_test.2315690399
Short name T446
Test name
Test status
Simulation time 540577024 ps
CPU time 1.2 seconds
Started Mar 19 12:30:07 PM PDT 24
Finished Mar 19 12:30:08 PM PDT 24
Peak memory 201508 kb
Host smart-198bed65-e0e7-42c3-9340-f4a38629d539
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315690399 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.2315690399
Directory /workspace/42.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.adc_ctrl_clock_gating.2803427698
Short name T187
Test name
Test status
Simulation time 344711340310 ps
CPU time 169.5 seconds
Started Mar 19 12:29:59 PM PDT 24
Finished Mar 19 12:32:49 PM PDT 24
Peak memory 201836 kb
Host smart-ad112739-aed1-475b-bf89-b3ff03b59081
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803427698 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gat
ing.2803427698
Directory /workspace/42.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt.3077874374
Short name T711
Test name
Test status
Simulation time 334398007743 ps
CPU time 729.86 seconds
Started Mar 19 12:30:06 PM PDT 24
Finished Mar 19 12:42:16 PM PDT 24
Peak memory 201784 kb
Host smart-068b7ddb-151e-457b-87cf-0cad5c6db660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077874374 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.3077874374
Directory /workspace/42.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt_fixed.1141566849
Short name T472
Test name
Test status
Simulation time 495628966379 ps
CPU time 1212.52 seconds
Started Mar 19 12:30:14 PM PDT 24
Finished Mar 19 12:50:27 PM PDT 24
Peak memory 201752 kb
Host smart-75cf7b11-17ff-4e06-b08e-93a20e593289
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141566849 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interru
pt_fixed.1141566849
Directory /workspace/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled.1264216246
Short name T629
Test name
Test status
Simulation time 166142027659 ps
CPU time 375.62 seconds
Started Mar 19 12:30:07 PM PDT 24
Finished Mar 19 12:36:23 PM PDT 24
Peak memory 201800 kb
Host smart-05c9fe9e-5b1e-48e1-904a-b6862fc1e0de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264216246 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.1264216246
Directory /workspace/42.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.4273122582
Short name T632
Test name
Test status
Simulation time 487187286457 ps
CPU time 323.44 seconds
Started Mar 19 12:30:08 PM PDT 24
Finished Mar 19 12:35:32 PM PDT 24
Peak memory 201764 kb
Host smart-a05e8fc5-c03b-4dab-9993-6e165a525500
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273122582 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fix
ed.4273122582
Directory /workspace/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup.1668059064
Short name T260
Test name
Test status
Simulation time 173895688408 ps
CPU time 237.71 seconds
Started Mar 19 12:31:24 PM PDT 24
Finished Mar 19 12:35:22 PM PDT 24
Peak memory 201780 kb
Host smart-b819b8e5-6763-4bcb-8605-e38cefb0d1fb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668059064 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters
_wakeup.1668059064
Directory /workspace/42.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup_fixed.2380351667
Short name T365
Test name
Test status
Simulation time 393108037762 ps
CPU time 211.67 seconds
Started Mar 19 12:29:57 PM PDT 24
Finished Mar 19 12:33:29 PM PDT 24
Peak memory 201820 kb
Host smart-2d64f8fa-6516-4020-81fd-9886b6a6b53f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380351667 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42
.adc_ctrl_filters_wakeup_fixed.2380351667
Directory /workspace/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_fsm_reset.261545609
Short name T586
Test name
Test status
Simulation time 73972736404 ps
CPU time 403.19 seconds
Started Mar 19 12:30:10 PM PDT 24
Finished Mar 19 12:36:54 PM PDT 24
Peak memory 202036 kb
Host smart-afde311f-9077-4085-a12f-35759ad478b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261545609 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.261545609
Directory /workspace/42.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_lowpower_counter.750326576
Short name T395
Test name
Test status
Simulation time 43249787785 ps
CPU time 101.19 seconds
Started Mar 19 12:29:57 PM PDT 24
Finished Mar 19 12:31:39 PM PDT 24
Peak memory 201568 kb
Host smart-9ee95115-799c-48df-a398-6e2b772fcdbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750326576 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.750326576
Directory /workspace/42.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_poweron_counter.2101060274
Short name T759
Test name
Test status
Simulation time 3462036021 ps
CPU time 2.68 seconds
Started Mar 19 12:30:12 PM PDT 24
Finished Mar 19 12:30:15 PM PDT 24
Peak memory 201568 kb
Host smart-13f78e82-c901-43b5-937c-956ba8199547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101060274 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.2101060274
Directory /workspace/42.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_smoke.275844437
Short name T564
Test name
Test status
Simulation time 5930967584 ps
CPU time 4.4 seconds
Started Mar 19 12:29:57 PM PDT 24
Finished Mar 19 12:30:02 PM PDT 24
Peak memory 201692 kb
Host smart-de89ee4c-81c9-4c89-816c-cb8bfa565fd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275844437 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.275844437
Directory /workspace/42.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all.2764693096
Short name T136
Test name
Test status
Simulation time 339837086909 ps
CPU time 216.74 seconds
Started Mar 19 12:29:59 PM PDT 24
Finished Mar 19 12:33:36 PM PDT 24
Peak memory 201876 kb
Host smart-c7c310b3-9695-4ebb-82a8-0be017425c5c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764693096 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all
.2764693096
Directory /workspace/42.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.adc_ctrl_alert_test.789008251
Short name T448
Test name
Test status
Simulation time 423323023 ps
CPU time 1.1 seconds
Started Mar 19 12:30:14 PM PDT 24
Finished Mar 19 12:30:15 PM PDT 24
Peak memory 201440 kb
Host smart-f65d3b15-3fca-4f21-9dd5-dfebad678103
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789008251 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.789008251
Directory /workspace/43.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.adc_ctrl_clock_gating.1878781951
Short name T752
Test name
Test status
Simulation time 509672624825 ps
CPU time 553.12 seconds
Started Mar 19 12:30:09 PM PDT 24
Finished Mar 19 12:39:22 PM PDT 24
Peak memory 201748 kb
Host smart-6a23dcc0-fef8-47cc-847c-4c371593f8d7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878781951 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gat
ing.1878781951
Directory /workspace/43.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_both.867324909
Short name T291
Test name
Test status
Simulation time 583723736021 ps
CPU time 1472.23 seconds
Started Mar 19 12:30:04 PM PDT 24
Finished Mar 19 12:54:37 PM PDT 24
Peak memory 201728 kb
Host smart-aa4226b1-902d-4f18-ad32-9df90e1b4e21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867324909 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.867324909
Directory /workspace/43.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt.651430057
Short name T445
Test name
Test status
Simulation time 165836248018 ps
CPU time 383.8 seconds
Started Mar 19 12:29:59 PM PDT 24
Finished Mar 19 12:36:24 PM PDT 24
Peak memory 201800 kb
Host smart-ef794fff-3e9b-4bb8-a887-8b027a93cca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651430057 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.651430057
Directory /workspace/43.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.546635276
Short name T204
Test name
Test status
Simulation time 165156596941 ps
CPU time 104.01 seconds
Started Mar 19 12:30:08 PM PDT 24
Finished Mar 19 12:31:52 PM PDT 24
Peak memory 201736 kb
Host smart-1be88593-7bdf-4267-89b1-00f5ac9ccbb6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=546635276 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrup
t_fixed.546635276
Directory /workspace/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled.4154553690
Short name T219
Test name
Test status
Simulation time 162198941449 ps
CPU time 192.42 seconds
Started Mar 19 12:30:16 PM PDT 24
Finished Mar 19 12:33:29 PM PDT 24
Peak memory 201880 kb
Host smart-894716a6-97ca-4a2f-8edd-c98f3004edc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154553690 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.4154553690
Directory /workspace/43.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled_fixed.919248855
Short name T599
Test name
Test status
Simulation time 492343962117 ps
CPU time 559.06 seconds
Started Mar 19 12:30:09 PM PDT 24
Finished Mar 19 12:39:29 PM PDT 24
Peak memory 201752 kb
Host smart-eb62e60b-540d-411a-a7e1-8db8a0eb3ac7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=919248855 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fixe
d.919248855
Directory /workspace/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup.451496576
Short name T249
Test name
Test status
Simulation time 586146969192 ps
CPU time 1334.82 seconds
Started Mar 19 12:30:00 PM PDT 24
Finished Mar 19 12:52:16 PM PDT 24
Peak memory 201900 kb
Host smart-c397da97-7fca-41e0-bd31-37cfa1a3e51c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451496576 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_
wakeup.451496576
Directory /workspace/43.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.3094623061
Short name T26
Test name
Test status
Simulation time 404926420175 ps
CPU time 234.45 seconds
Started Mar 19 12:30:09 PM PDT 24
Finished Mar 19 12:34:04 PM PDT 24
Peak memory 201756 kb
Host smart-43d2179d-67b9-490a-8233-343b23b020cf
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094623061 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43
.adc_ctrl_filters_wakeup_fixed.3094623061
Directory /workspace/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_fsm_reset.698159919
Short name T694
Test name
Test status
Simulation time 82128254146 ps
CPU time 436.54 seconds
Started Mar 19 12:30:10 PM PDT 24
Finished Mar 19 12:37:27 PM PDT 24
Peak memory 202104 kb
Host smart-9a4b2530-4689-4e8d-b313-76100dad03d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698159919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.698159919
Directory /workspace/43.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_lowpower_counter.848898063
Short name T396
Test name
Test status
Simulation time 45845856222 ps
CPU time 112.99 seconds
Started Mar 19 12:30:10 PM PDT 24
Finished Mar 19 12:32:04 PM PDT 24
Peak memory 201572 kb
Host smart-bc9403b1-b852-42cc-a78e-83b1149b822f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848898063 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.848898063
Directory /workspace/43.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_poweron_counter.945936734
Short name T137
Test name
Test status
Simulation time 3354354218 ps
CPU time 2.72 seconds
Started Mar 19 12:30:03 PM PDT 24
Finished Mar 19 12:30:06 PM PDT 24
Peak memory 201556 kb
Host smart-248b6630-a3f1-41be-a172-c409ac7d8473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945936734 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.945936734
Directory /workspace/43.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_smoke.1698857590
Short name T693
Test name
Test status
Simulation time 5743078886 ps
CPU time 14.7 seconds
Started Mar 19 12:29:59 PM PDT 24
Finished Mar 19 12:30:14 PM PDT 24
Peak memory 201576 kb
Host smart-5860e478-d290-40ab-8a5e-cf8faef62a4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698857590 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.1698857590
Directory /workspace/43.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all.2493446242
Short name T229
Test name
Test status
Simulation time 370862776140 ps
CPU time 429.55 seconds
Started Mar 19 12:30:06 PM PDT 24
Finished Mar 19 12:37:16 PM PDT 24
Peak memory 201780 kb
Host smart-60dfd8b3-dac6-42dd-8d40-168402eec6ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493446242 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all
.2493446242
Directory /workspace/43.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.1499716857
Short name T748
Test name
Test status
Simulation time 24245122399 ps
CPU time 57.13 seconds
Started Mar 19 12:30:09 PM PDT 24
Finished Mar 19 12:31:06 PM PDT 24
Peak memory 210088 kb
Host smart-07f580ab-8b45-4475-be6b-842fb92f0034
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499716857 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.1499716857
Directory /workspace/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_alert_test.3539539426
Short name T673
Test name
Test status
Simulation time 450296930 ps
CPU time 0.74 seconds
Started Mar 19 12:30:10 PM PDT 24
Finished Mar 19 12:30:11 PM PDT 24
Peak memory 201448 kb
Host smart-c8412be1-a019-4f8d-8a9e-6cad9afcefd8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539539426 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.3539539426
Directory /workspace/44.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.adc_ctrl_clock_gating.2452584809
Short name T15
Test name
Test status
Simulation time 329849120881 ps
CPU time 809.5 seconds
Started Mar 19 12:30:08 PM PDT 24
Finished Mar 19 12:43:39 PM PDT 24
Peak memory 201792 kb
Host smart-a90a132c-50f9-48ae-b178-bc05b273bcdc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452584809 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gat
ing.2452584809
Directory /workspace/44.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt_fixed.1559437636
Short name T493
Test name
Test status
Simulation time 326226317827 ps
CPU time 795.2 seconds
Started Mar 19 12:30:06 PM PDT 24
Finished Mar 19 12:43:22 PM PDT 24
Peak memory 201792 kb
Host smart-a5be7a7e-5649-4cd6-b10d-c7ca48590f72
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559437636 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interru
pt_fixed.1559437636
Directory /workspace/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled.1293215680
Short name T698
Test name
Test status
Simulation time 161956239770 ps
CPU time 104.1 seconds
Started Mar 19 12:30:15 PM PDT 24
Finished Mar 19 12:31:59 PM PDT 24
Peak memory 201764 kb
Host smart-03a9b5b0-a094-48f4-be28-69c4c8ff8c5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293215680 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.1293215680
Directory /workspace/44.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled_fixed.524453130
Short name T426
Test name
Test status
Simulation time 319171324691 ps
CPU time 190.08 seconds
Started Mar 19 12:30:09 PM PDT 24
Finished Mar 19 12:33:19 PM PDT 24
Peak memory 201752 kb
Host smart-038978d5-5e78-4447-8007-7f4e7315cc74
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=524453130 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fixe
d.524453130
Directory /workspace/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup.3312522696
Short name T316
Test name
Test status
Simulation time 560891344056 ps
CPU time 1383.72 seconds
Started Mar 19 12:30:05 PM PDT 24
Finished Mar 19 12:53:10 PM PDT 24
Peak memory 201752 kb
Host smart-5a565f84-c925-4004-b73d-13871b68c897
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312522696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters
_wakeup.3312522696
Directory /workspace/44.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup_fixed.3015200585
Short name T530
Test name
Test status
Simulation time 384209828276 ps
CPU time 109.04 seconds
Started Mar 19 12:30:14 PM PDT 24
Finished Mar 19 12:32:03 PM PDT 24
Peak memory 201764 kb
Host smart-5d28423c-b7e5-4521-acd4-61f27df449ed
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015200585 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44
.adc_ctrl_filters_wakeup_fixed.3015200585
Directory /workspace/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_fsm_reset.178743869
Short name T522
Test name
Test status
Simulation time 129622792465 ps
CPU time 480.71 seconds
Started Mar 19 12:30:07 PM PDT 24
Finished Mar 19 12:38:08 PM PDT 24
Peak memory 202128 kb
Host smart-d18a411e-6bd5-4850-b101-e994e0db1f70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178743869 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.178743869
Directory /workspace/44.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_lowpower_counter.181399349
Short name T554
Test name
Test status
Simulation time 24917457251 ps
CPU time 35.14 seconds
Started Mar 19 12:30:09 PM PDT 24
Finished Mar 19 12:30:44 PM PDT 24
Peak memory 201568 kb
Host smart-0c52b4a1-923e-4ee7-ba48-50eef99c322a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181399349 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.181399349
Directory /workspace/44.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_poweron_counter.3115792266
Short name T423
Test name
Test status
Simulation time 5058810136 ps
CPU time 12.38 seconds
Started Mar 19 12:30:07 PM PDT 24
Finished Mar 19 12:30:19 PM PDT 24
Peak memory 201580 kb
Host smart-05eb3fce-382a-4eaa-8e7b-abb1737cabaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115792266 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.3115792266
Directory /workspace/44.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_smoke.1503950326
Short name T770
Test name
Test status
Simulation time 6091977610 ps
CPU time 7.66 seconds
Started Mar 19 12:30:14 PM PDT 24
Finished Mar 19 12:30:22 PM PDT 24
Peak memory 201608 kb
Host smart-4cedbc67-8664-4dd9-bf52-f98086125eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503950326 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.1503950326
Directory /workspace/44.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all.3644281509
Short name T39
Test name
Test status
Simulation time 34239806017 ps
CPU time 19.04 seconds
Started Mar 19 12:30:13 PM PDT 24
Finished Mar 19 12:30:33 PM PDT 24
Peak memory 201576 kb
Host smart-609dd015-5755-4dad-9a5b-bb736b86c7a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644281509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all
.3644281509
Directory /workspace/44.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.1246815534
Short name T18
Test name
Test status
Simulation time 87906851843 ps
CPU time 72.79 seconds
Started Mar 19 12:30:04 PM PDT 24
Finished Mar 19 12:31:17 PM PDT 24
Peak memory 215932 kb
Host smart-0c20c4cc-b263-409b-a386-b6e1fb0fdac8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246815534 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all_with_rand_reset.1246815534
Directory /workspace/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_alert_test.1999689902
Short name T383
Test name
Test status
Simulation time 411367927 ps
CPU time 1.5 seconds
Started Mar 19 12:30:12 PM PDT 24
Finished Mar 19 12:30:13 PM PDT 24
Peak memory 201432 kb
Host smart-55d7f0ff-305d-465e-9b13-3cb23855947f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999689902 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.1999689902
Directory /workspace/45.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.adc_ctrl_clock_gating.1311661391
Short name T200
Test name
Test status
Simulation time 345749789477 ps
CPU time 219.75 seconds
Started Mar 19 12:30:11 PM PDT 24
Finished Mar 19 12:33:51 PM PDT 24
Peak memory 201768 kb
Host smart-813f3501-29ae-482c-bba0-09aa97d613d5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311661391 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gat
ing.1311661391
Directory /workspace/45.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_both.768979016
Short name T194
Test name
Test status
Simulation time 362358539386 ps
CPU time 808.63 seconds
Started Mar 19 12:30:15 PM PDT 24
Finished Mar 19 12:43:44 PM PDT 24
Peak memory 201888 kb
Host smart-e0f8e3f2-7beb-44ab-bd2a-f88f1b79bb92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768979016 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.768979016
Directory /workspace/45.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt.2322462095
Short name T224
Test name
Test status
Simulation time 323868255916 ps
CPU time 404.83 seconds
Started Mar 19 12:30:13 PM PDT 24
Finished Mar 19 12:36:59 PM PDT 24
Peak memory 201732 kb
Host smart-0e9e16c0-1aa2-43f2-a8e8-280697eca01c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322462095 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.2322462095
Directory /workspace/45.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt_fixed.3184407327
Short name T475
Test name
Test status
Simulation time 166651711109 ps
CPU time 187.36 seconds
Started Mar 19 12:30:09 PM PDT 24
Finished Mar 19 12:33:17 PM PDT 24
Peak memory 201732 kb
Host smart-20e77cdc-7e70-4cf8-a68a-cbe12e51f8bd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184407327 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interru
pt_fixed.3184407327
Directory /workspace/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled.2221111163
Short name T146
Test name
Test status
Simulation time 334026376872 ps
CPU time 785.19 seconds
Started Mar 19 12:30:14 PM PDT 24
Finished Mar 19 12:43:20 PM PDT 24
Peak memory 201828 kb
Host smart-57192ebe-fef2-4132-bf25-464e0d8a4036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221111163 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.2221111163
Directory /workspace/45.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled_fixed.3098278671
Short name T397
Test name
Test status
Simulation time 331689643326 ps
CPU time 717.25 seconds
Started Mar 19 12:30:05 PM PDT 24
Finished Mar 19 12:42:02 PM PDT 24
Peak memory 201752 kb
Host smart-6942580c-6f91-418a-9de5-ccada540679f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098278671 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fix
ed.3098278671
Directory /workspace/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup.3778278453
Short name T774
Test name
Test status
Simulation time 364491740250 ps
CPU time 907.68 seconds
Started Mar 19 12:30:17 PM PDT 24
Finished Mar 19 12:45:25 PM PDT 24
Peak memory 201840 kb
Host smart-04f6ae57-09f0-44f8-a849-398c4666638e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778278453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters
_wakeup.3778278453
Directory /workspace/45.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup_fixed.897130864
Short name T373
Test name
Test status
Simulation time 611195550006 ps
CPU time 1365.74 seconds
Started Mar 19 12:30:17 PM PDT 24
Finished Mar 19 12:53:03 PM PDT 24
Peak memory 201772 kb
Host smart-2a3b325e-d110-47cd-a4bd-df76a66485ad
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897130864 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
adc_ctrl_filters_wakeup_fixed.897130864
Directory /workspace/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_fsm_reset.3944728593
Short name T30
Test name
Test status
Simulation time 94511841639 ps
CPU time 355.84 seconds
Started Mar 19 12:30:11 PM PDT 24
Finished Mar 19 12:36:07 PM PDT 24
Peak memory 202076 kb
Host smart-58e6a481-b33c-4eb9-b60f-989265b2e60c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944728593 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.3944728593
Directory /workspace/45.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_lowpower_counter.2854179521
Short name T449
Test name
Test status
Simulation time 41016864000 ps
CPU time 95.98 seconds
Started Mar 19 12:30:11 PM PDT 24
Finished Mar 19 12:31:47 PM PDT 24
Peak memory 201580 kb
Host smart-6a57de91-1e3d-4b24-bb3b-70d5014e199e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854179521 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.2854179521
Directory /workspace/45.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_poweron_counter.924824188
Short name T380
Test name
Test status
Simulation time 3052446937 ps
CPU time 7.63 seconds
Started Mar 19 12:30:21 PM PDT 24
Finished Mar 19 12:30:29 PM PDT 24
Peak memory 201568 kb
Host smart-ced449fb-c163-48dd-8994-818f303992a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924824188 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.924824188
Directory /workspace/45.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_smoke.725900581
Short name T381
Test name
Test status
Simulation time 5849442855 ps
CPU time 14.71 seconds
Started Mar 19 12:30:12 PM PDT 24
Finished Mar 19 12:30:27 PM PDT 24
Peak memory 201576 kb
Host smart-d80668f5-7455-425d-bd55-5e3609290f66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725900581 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.725900581
Directory /workspace/45.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all.2523693181
Short name T584
Test name
Test status
Simulation time 180247548522 ps
CPU time 223.33 seconds
Started Mar 19 12:30:12 PM PDT 24
Finished Mar 19 12:33:55 PM PDT 24
Peak memory 201832 kb
Host smart-3862c3a4-0075-4b1a-8eef-78e85acd1409
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523693181 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all
.2523693181
Directory /workspace/45.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.adc_ctrl_alert_test.3878153032
Short name T731
Test name
Test status
Simulation time 290894046 ps
CPU time 1.26 seconds
Started Mar 19 12:30:17 PM PDT 24
Finished Mar 19 12:30:19 PM PDT 24
Peak memory 201512 kb
Host smart-9104d2ae-b22b-4a5c-8507-bb054e6703ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878153032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.3878153032
Directory /workspace/46.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.adc_ctrl_clock_gating.183339266
Short name T610
Test name
Test status
Simulation time 525110145168 ps
CPU time 931.6 seconds
Started Mar 19 12:30:21 PM PDT 24
Finished Mar 19 12:45:53 PM PDT 24
Peak memory 201800 kb
Host smart-d4faad16-b853-48c4-b426-d63c0ba1b3e5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183339266 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gati
ng.183339266
Directory /workspace/46.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_both.1599505944
Short name T160
Test name
Test status
Simulation time 334664549173 ps
CPU time 88.16 seconds
Started Mar 19 12:30:19 PM PDT 24
Finished Mar 19 12:31:47 PM PDT 24
Peak memory 201720 kb
Host smart-0e8f0ff1-9113-4e6a-9374-5c45200683c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599505944 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.1599505944
Directory /workspace/46.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt.3360556650
Short name T177
Test name
Test status
Simulation time 159611932891 ps
CPU time 80.8 seconds
Started Mar 19 12:30:15 PM PDT 24
Finished Mar 19 12:31:36 PM PDT 24
Peak memory 201840 kb
Host smart-eb4697a0-1475-4740-827b-7d2415b4a8f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360556650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.3360556650
Directory /workspace/46.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.673808378
Short name T771
Test name
Test status
Simulation time 326965143786 ps
CPU time 753.04 seconds
Started Mar 19 12:30:23 PM PDT 24
Finished Mar 19 12:42:57 PM PDT 24
Peak memory 201728 kb
Host smart-e979f9bb-1f60-4ecb-826a-4ebc68f204e1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=673808378 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrup
t_fixed.673808378
Directory /workspace/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled.3349912730
Short name T667
Test name
Test status
Simulation time 318498559272 ps
CPU time 585.53 seconds
Started Mar 19 12:30:12 PM PDT 24
Finished Mar 19 12:39:57 PM PDT 24
Peak memory 201852 kb
Host smart-9f4a2a72-e93a-44be-a16e-bdafa222491b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349912730 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.3349912730
Directory /workspace/46.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled_fixed.705925439
Short name T425
Test name
Test status
Simulation time 163745969951 ps
CPU time 212.36 seconds
Started Mar 19 12:30:19 PM PDT 24
Finished Mar 19 12:33:52 PM PDT 24
Peak memory 201828 kb
Host smart-14cf3615-80d7-4518-8f5b-0b24966c439f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=705925439 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fixe
d.705925439
Directory /workspace/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup.171094805
Short name T546
Test name
Test status
Simulation time 173284510560 ps
CPU time 357.34 seconds
Started Mar 19 12:30:24 PM PDT 24
Finished Mar 19 12:36:22 PM PDT 24
Peak memory 201764 kb
Host smart-267ac98b-1b56-46c8-8f01-846fe4ac86ce
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171094805 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_
wakeup.171094805
Directory /workspace/46.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup_fixed.3527452305
Short name T468
Test name
Test status
Simulation time 200108486309 ps
CPU time 470.03 seconds
Started Mar 19 12:30:17 PM PDT 24
Finished Mar 19 12:38:07 PM PDT 24
Peak memory 201768 kb
Host smart-24b944e1-d7df-4889-8726-50473626b4c4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527452305 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46
.adc_ctrl_filters_wakeup_fixed.3527452305
Directory /workspace/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_fsm_reset.4198197356
Short name T210
Test name
Test status
Simulation time 137788648309 ps
CPU time 552.34 seconds
Started Mar 19 12:30:15 PM PDT 24
Finished Mar 19 12:39:27 PM PDT 24
Peak memory 202048 kb
Host smart-6e5e8d43-4fba-463e-a826-f315d54cefc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198197356 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.4198197356
Directory /workspace/46.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_lowpower_counter.2016936981
Short name T510
Test name
Test status
Simulation time 35131576569 ps
CPU time 77.86 seconds
Started Mar 19 12:30:19 PM PDT 24
Finished Mar 19 12:31:37 PM PDT 24
Peak memory 201568 kb
Host smart-fecf3cf5-4c5c-477e-9d89-afec555059f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016936981 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.2016936981
Directory /workspace/46.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_poweron_counter.4184331381
Short name T675
Test name
Test status
Simulation time 5148283396 ps
CPU time 12.22 seconds
Started Mar 19 12:30:24 PM PDT 24
Finished Mar 19 12:30:37 PM PDT 24
Peak memory 201572 kb
Host smart-1bbda948-8a1d-4580-b3f0-b5d40c42db1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184331381 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.4184331381
Directory /workspace/46.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_smoke.3680164709
Short name T353
Test name
Test status
Simulation time 5820347726 ps
CPU time 15.14 seconds
Started Mar 19 12:30:09 PM PDT 24
Finished Mar 19 12:30:25 PM PDT 24
Peak memory 201580 kb
Host smart-0613cbae-4686-4630-9870-fc83294e9fee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680164709 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.3680164709
Directory /workspace/46.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all.3306130531
Short name T9
Test name
Test status
Simulation time 243513825220 ps
CPU time 845.32 seconds
Started Mar 19 12:30:23 PM PDT 24
Finished Mar 19 12:44:29 PM PDT 24
Peak memory 212356 kb
Host smart-731488f2-224b-461e-bdec-b31cb91eab5c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306130531 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all
.3306130531
Directory /workspace/46.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.378725845
Short name T549
Test name
Test status
Simulation time 113047291032 ps
CPU time 33.43 seconds
Started Mar 19 12:30:18 PM PDT 24
Finished Mar 19 12:30:51 PM PDT 24
Peak memory 201912 kb
Host smart-de746d69-4fcf-4651-9f2f-09771ea6155b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378725845 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all_with_rand_reset.378725845
Directory /workspace/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_alert_test.623266831
Short name T411
Test name
Test status
Simulation time 351670800 ps
CPU time 0.83 seconds
Started Mar 19 12:30:23 PM PDT 24
Finished Mar 19 12:30:25 PM PDT 24
Peak memory 201440 kb
Host smart-b4d67129-f4b4-4313-b7ee-897d126119a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623266831 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.623266831
Directory /workspace/47.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_both.3742314288
Short name T228
Test name
Test status
Simulation time 352314985462 ps
CPU time 799.96 seconds
Started Mar 19 12:30:23 PM PDT 24
Finished Mar 19 12:43:43 PM PDT 24
Peak memory 201760 kb
Host smart-47477422-04d1-420f-9992-409b68fa6d26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742314288 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.3742314288
Directory /workspace/47.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt.413147048
Short name T791
Test name
Test status
Simulation time 174768975907 ps
CPU time 60.51 seconds
Started Mar 19 12:30:17 PM PDT 24
Finished Mar 19 12:31:17 PM PDT 24
Peak memory 201836 kb
Host smart-230b7aad-ad7e-41e5-bb32-6b0be194ec69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413147048 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.413147048
Directory /workspace/47.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt_fixed.2024360023
Short name T356
Test name
Test status
Simulation time 161983762282 ps
CPU time 344.67 seconds
Started Mar 19 12:30:15 PM PDT 24
Finished Mar 19 12:36:00 PM PDT 24
Peak memory 201712 kb
Host smart-2f27a2c5-65fa-463b-8b70-eb9033868b2f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024360023 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interru
pt_fixed.2024360023
Directory /workspace/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled.207820381
Short name T199
Test name
Test status
Simulation time 335367771388 ps
CPU time 189.58 seconds
Started Mar 19 12:30:22 PM PDT 24
Finished Mar 19 12:33:32 PM PDT 24
Peak memory 201816 kb
Host smart-45e2c18b-493e-4769-983b-f7425634ad30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207820381 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.207820381
Directory /workspace/47.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled_fixed.196661832
Short name T699
Test name
Test status
Simulation time 507592338466 ps
CPU time 299.27 seconds
Started Mar 19 12:30:24 PM PDT 24
Finished Mar 19 12:35:24 PM PDT 24
Peak memory 201740 kb
Host smart-34adb206-40fd-4f88-82e8-ef87fa89eae6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=196661832 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fixe
d.196661832
Directory /workspace/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup.1748418457
Short name T333
Test name
Test status
Simulation time 362786937875 ps
CPU time 417.21 seconds
Started Mar 19 12:30:19 PM PDT 24
Finished Mar 19 12:37:16 PM PDT 24
Peak memory 201724 kb
Host smart-ee45f7e4-5c0d-4cbe-a341-31093aa6150e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748418457 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters
_wakeup.1748418457
Directory /workspace/47.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.3299222886
Short name T627
Test name
Test status
Simulation time 395203158459 ps
CPU time 61.99 seconds
Started Mar 19 12:30:20 PM PDT 24
Finished Mar 19 12:31:22 PM PDT 24
Peak memory 201760 kb
Host smart-2fa086d8-f8e7-43ce-b9ed-5ab9ddf6d648
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299222886 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47
.adc_ctrl_filters_wakeup_fixed.3299222886
Directory /workspace/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_fsm_reset.1020130581
Short name T348
Test name
Test status
Simulation time 123430001125 ps
CPU time 429.49 seconds
Started Mar 19 12:30:24 PM PDT 24
Finished Mar 19 12:37:34 PM PDT 24
Peak memory 202044 kb
Host smart-a41e774f-73cb-46e0-9cf5-0c77921d34c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020130581 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.1020130581
Directory /workspace/47.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_lowpower_counter.1473661756
Short name T478
Test name
Test status
Simulation time 44872563784 ps
CPU time 56.2 seconds
Started Mar 19 12:30:23 PM PDT 24
Finished Mar 19 12:31:19 PM PDT 24
Peak memory 201572 kb
Host smart-a2cda4c8-65bf-4517-a2e3-bc5d05393b1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473661756 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.1473661756
Directory /workspace/47.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_poweron_counter.3440175901
Short name T682
Test name
Test status
Simulation time 4929223339 ps
CPU time 3.97 seconds
Started Mar 19 12:30:21 PM PDT 24
Finished Mar 19 12:30:25 PM PDT 24
Peak memory 201616 kb
Host smart-8745d7ab-f212-484e-8e36-65f8d9efe08d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440175901 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.3440175901
Directory /workspace/47.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_smoke.2165360143
Short name T401
Test name
Test status
Simulation time 5718637648 ps
CPU time 13.11 seconds
Started Mar 19 12:30:17 PM PDT 24
Finished Mar 19 12:30:31 PM PDT 24
Peak memory 201584 kb
Host smart-5681dbd9-c8c7-4658-a7dc-50896a692627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165360143 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.2165360143
Directory /workspace/47.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all.2732121660
Short name T37
Test name
Test status
Simulation time 56456123773 ps
CPU time 36.31 seconds
Started Mar 19 12:30:24 PM PDT 24
Finished Mar 19 12:31:01 PM PDT 24
Peak memory 201832 kb
Host smart-3f0e4eef-9527-4d30-b87f-9698c3d1f91b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732121660 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all
.2732121660
Directory /workspace/47.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.550759185
Short name T279
Test name
Test status
Simulation time 1043975751271 ps
CPU time 249.14 seconds
Started Mar 19 12:30:31 PM PDT 24
Finished Mar 19 12:34:41 PM PDT 24
Peak memory 210428 kb
Host smart-ce5b7251-41c8-4391-bbc3-1e09464eca5f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550759185 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all_with_rand_reset.550759185
Directory /workspace/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_alert_test.637469830
Short name T630
Test name
Test status
Simulation time 536604388 ps
CPU time 1.24 seconds
Started Mar 19 12:30:21 PM PDT 24
Finished Mar 19 12:30:22 PM PDT 24
Peak memory 201456 kb
Host smart-f6c994a2-da1b-400f-a008-0a3a71f94719
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637469830 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.637469830
Directory /workspace/48.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.adc_ctrl_clock_gating.2751741298
Short name T272
Test name
Test status
Simulation time 165403869950 ps
CPU time 400.2 seconds
Started Mar 19 12:30:31 PM PDT 24
Finished Mar 19 12:37:11 PM PDT 24
Peak memory 201736 kb
Host smart-58aaea68-f02f-492d-9663-90400ff2ee30
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751741298 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gat
ing.2751741298
Directory /workspace/48.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_both.1322160874
Short name T155
Test name
Test status
Simulation time 444458131790 ps
CPU time 338.88 seconds
Started Mar 19 12:30:25 PM PDT 24
Finished Mar 19 12:36:04 PM PDT 24
Peak memory 201724 kb
Host smart-3b9f1ba6-63b4-4899-9ace-5fd2217d1dac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322160874 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.1322160874
Directory /workspace/48.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt.3429438033
Short name T289
Test name
Test status
Simulation time 163572491223 ps
CPU time 92.21 seconds
Started Mar 19 12:30:23 PM PDT 24
Finished Mar 19 12:31:56 PM PDT 24
Peak memory 201748 kb
Host smart-f39eed3c-5a6d-4bc5-816f-4f22374293c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429438033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.3429438033
Directory /workspace/48.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt_fixed.3325155141
Short name T708
Test name
Test status
Simulation time 498411752645 ps
CPU time 583.32 seconds
Started Mar 19 12:30:21 PM PDT 24
Finished Mar 19 12:40:04 PM PDT 24
Peak memory 201816 kb
Host smart-c39806f6-c1b6-406f-b78f-423eb49676ee
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325155141 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interru
pt_fixed.3325155141
Directory /workspace/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled_fixed.2632367153
Short name T573
Test name
Test status
Simulation time 167449313480 ps
CPU time 209.02 seconds
Started Mar 19 12:30:21 PM PDT 24
Finished Mar 19 12:33:50 PM PDT 24
Peak memory 201788 kb
Host smart-fca99fb1-48f5-4056-87a6-2f1668d4a836
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632367153 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fix
ed.2632367153
Directory /workspace/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup.1874970083
Short name T663
Test name
Test status
Simulation time 347547747902 ps
CPU time 379.92 seconds
Started Mar 19 12:30:21 PM PDT 24
Finished Mar 19 12:36:42 PM PDT 24
Peak memory 201868 kb
Host smart-9777a5dd-8c8f-40ca-9801-5f0e0b51f020
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874970083 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters
_wakeup.1874970083
Directory /workspace/48.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.2829918704
Short name T477
Test name
Test status
Simulation time 197372838408 ps
CPU time 435.2 seconds
Started Mar 19 12:30:23 PM PDT 24
Finished Mar 19 12:37:38 PM PDT 24
Peak memory 201764 kb
Host smart-7a874880-4a04-49e4-9a98-09286b647aa5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829918704 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48
.adc_ctrl_filters_wakeup_fixed.2829918704
Directory /workspace/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_fsm_reset.64792030
Short name T603
Test name
Test status
Simulation time 58814350199 ps
CPU time 280.37 seconds
Started Mar 19 12:30:21 PM PDT 24
Finished Mar 19 12:35:02 PM PDT 24
Peak memory 202072 kb
Host smart-8b1882e0-108e-45ab-96c4-babed0ba0fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64792030 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.64792030
Directory /workspace/48.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_lowpower_counter.9730025
Short name T460
Test name
Test status
Simulation time 34330463417 ps
CPU time 9.17 seconds
Started Mar 19 12:30:23 PM PDT 24
Finished Mar 19 12:30:33 PM PDT 24
Peak memory 201540 kb
Host smart-686ba5e0-5609-4aae-a388-94602abaa260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9730025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.9730025
Directory /workspace/48.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_poweron_counter.994051228
Short name T451
Test name
Test status
Simulation time 4697686355 ps
CPU time 12.62 seconds
Started Mar 19 12:30:23 PM PDT 24
Finished Mar 19 12:30:36 PM PDT 24
Peak memory 201668 kb
Host smart-0d4a964a-9154-48e8-bece-fc0a0917d85a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994051228 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.994051228
Directory /workspace/48.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_smoke.2313650323
Short name T749
Test name
Test status
Simulation time 6118143039 ps
CPU time 4.13 seconds
Started Mar 19 12:30:23 PM PDT 24
Finished Mar 19 12:30:27 PM PDT 24
Peak memory 201588 kb
Host smart-3ff9348d-765f-44d1-8596-727f8a2f0570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313650323 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.2313650323
Directory /workspace/48.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all.1162307644
Short name T189
Test name
Test status
Simulation time 360055936444 ps
CPU time 840.85 seconds
Started Mar 19 12:30:21 PM PDT 24
Finished Mar 19 12:44:22 PM PDT 24
Peak memory 201792 kb
Host smart-6a11a748-07e7-453a-a317-e984128994c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162307644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all
.1162307644
Directory /workspace/48.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.adc_ctrl_alert_test.2933420691
Short name T684
Test name
Test status
Simulation time 529928839 ps
CPU time 1.8 seconds
Started Mar 19 12:30:33 PM PDT 24
Finished Mar 19 12:30:35 PM PDT 24
Peak memory 201512 kb
Host smart-4ca8c35e-3b85-492b-8ddb-cea5d8daccd1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933420691 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.2933420691
Directory /workspace/49.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.adc_ctrl_clock_gating.1774628920
Short name T297
Test name
Test status
Simulation time 191957003314 ps
CPU time 451.78 seconds
Started Mar 19 12:30:33 PM PDT 24
Finished Mar 19 12:38:05 PM PDT 24
Peak memory 201756 kb
Host smart-ef0c6324-a72a-428c-aed5-5f87df9902e7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774628920 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gat
ing.1774628920
Directory /workspace/49.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_both.2143625166
Short name T190
Test name
Test status
Simulation time 374450938628 ps
CPU time 242.41 seconds
Started Mar 19 12:30:32 PM PDT 24
Finished Mar 19 12:34:35 PM PDT 24
Peak memory 201884 kb
Host smart-49cd0bdd-a331-4b03-ac04-4b3901d165da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143625166 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.2143625166
Directory /workspace/49.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt_fixed.3507512471
Short name T735
Test name
Test status
Simulation time 493683792347 ps
CPU time 1140.29 seconds
Started Mar 19 12:30:34 PM PDT 24
Finished Mar 19 12:49:35 PM PDT 24
Peak memory 201804 kb
Host smart-0514f7dc-4882-49af-9bbc-8829e756fe71
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507512471 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interru
pt_fixed.3507512471
Directory /workspace/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled.2801671037
Short name T7
Test name
Test status
Simulation time 339961168829 ps
CPU time 708.79 seconds
Started Mar 19 12:30:31 PM PDT 24
Finished Mar 19 12:42:21 PM PDT 24
Peak memory 201796 kb
Host smart-54f3fa39-eac5-4eec-883e-382a7f5124af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801671037 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.2801671037
Directory /workspace/49.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled_fixed.655494608
Short name T432
Test name
Test status
Simulation time 167740282499 ps
CPU time 67.87 seconds
Started Mar 19 12:30:23 PM PDT 24
Finished Mar 19 12:31:32 PM PDT 24
Peak memory 201844 kb
Host smart-045a3a87-e438-4049-afdf-c7decddb79fa
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=655494608 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fixe
d.655494608
Directory /workspace/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup.4064037011
Short name T640
Test name
Test status
Simulation time 371535053116 ps
CPU time 350.34 seconds
Started Mar 19 12:30:35 PM PDT 24
Finished Mar 19 12:36:25 PM PDT 24
Peak memory 201712 kb
Host smart-ec86d13c-45a1-4871-a454-e273b378ca29
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064037011 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters
_wakeup.4064037011
Directory /workspace/49.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup_fixed.3918643958
Short name T467
Test name
Test status
Simulation time 608974251624 ps
CPU time 190.38 seconds
Started Mar 19 12:30:33 PM PDT 24
Finished Mar 19 12:33:44 PM PDT 24
Peak memory 201796 kb
Host smart-d3741692-c48d-425f-8630-20c55265697c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918643958 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49
.adc_ctrl_filters_wakeup_fixed.3918643958
Directory /workspace/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_fsm_reset.3756715612
Short name T51
Test name
Test status
Simulation time 98236344471 ps
CPU time 328.5 seconds
Started Mar 19 12:30:33 PM PDT 24
Finished Mar 19 12:36:02 PM PDT 24
Peak memory 202064 kb
Host smart-aee806c6-0cf9-488d-ba44-e64b2ae0b095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756715612 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.3756715612
Directory /workspace/49.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_lowpower_counter.2110642526
Short name T790
Test name
Test status
Simulation time 26303094297 ps
CPU time 65.77 seconds
Started Mar 19 12:30:34 PM PDT 24
Finished Mar 19 12:31:40 PM PDT 24
Peak memory 201572 kb
Host smart-39122180-1546-47a8-a92a-e33fde8cfe25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110642526 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.2110642526
Directory /workspace/49.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_poweron_counter.3878213014
Short name T662
Test name
Test status
Simulation time 5400440946 ps
CPU time 9.56 seconds
Started Mar 19 12:30:33 PM PDT 24
Finished Mar 19 12:30:43 PM PDT 24
Peak memory 201560 kb
Host smart-587efd5d-704a-434d-8b2a-aa952fb2707b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878213014 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.3878213014
Directory /workspace/49.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_smoke.2223076346
Short name T721
Test name
Test status
Simulation time 5897620108 ps
CPU time 14.73 seconds
Started Mar 19 12:30:31 PM PDT 24
Finished Mar 19 12:30:45 PM PDT 24
Peak memory 201560 kb
Host smart-58b95cee-7092-4210-bce5-24477e5cec97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223076346 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.2223076346
Directory /workspace/49.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.1929626355
Short name T92
Test name
Test status
Simulation time 80587438211 ps
CPU time 240.83 seconds
Started Mar 19 12:30:38 PM PDT 24
Finished Mar 19 12:34:41 PM PDT 24
Peak memory 210700 kb
Host smart-34e0342d-99d1-412d-b00e-56d39ee554c4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929626355 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all_with_rand_reset.1929626355
Directory /workspace/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_alert_test.2613292331
Short name T773
Test name
Test status
Simulation time 302645163 ps
CPU time 0.79 seconds
Started Mar 19 12:28:48 PM PDT 24
Finished Mar 19 12:28:49 PM PDT 24
Peak memory 201460 kb
Host smart-22cbeca4-3c04-47e2-beb5-81a01c54d5ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613292331 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.2613292331
Directory /workspace/5.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.adc_ctrl_clock_gating.2057999381
Short name T191
Test name
Test status
Simulation time 530204267880 ps
CPU time 143.59 seconds
Started Mar 19 12:29:39 PM PDT 24
Finished Mar 19 12:32:02 PM PDT 24
Peak memory 201796 kb
Host smart-33aff291-9a41-4d6c-9248-afc4b76d7641
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057999381 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gati
ng.2057999381
Directory /workspace/5.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_both.835317158
Short name T277
Test name
Test status
Simulation time 368533572944 ps
CPU time 94.58 seconds
Started Mar 19 12:28:52 PM PDT 24
Finished Mar 19 12:30:26 PM PDT 24
Peak memory 201804 kb
Host smart-3afbbac6-2db0-4280-adec-f0a9530605d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835317158 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.835317158
Directory /workspace/5.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt.1334123328
Short name T314
Test name
Test status
Simulation time 166984143161 ps
CPU time 117.32 seconds
Started Mar 19 12:29:04 PM PDT 24
Finished Mar 19 12:31:01 PM PDT 24
Peak memory 201740 kb
Host smart-70112c3c-3654-4903-9680-6d7f6912dae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334123328 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.1334123328
Directory /workspace/5.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt_fixed.1715899299
Short name T464
Test name
Test status
Simulation time 501551351162 ps
CPU time 1192.93 seconds
Started Mar 19 12:28:43 PM PDT 24
Finished Mar 19 12:48:36 PM PDT 24
Peak memory 201740 kb
Host smart-a45d39c5-a935-40f6-b9da-a7ed6bff33df
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715899299 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrup
t_fixed.1715899299
Directory /workspace/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled.618310001
Short name T335
Test name
Test status
Simulation time 326730624258 ps
CPU time 175.4 seconds
Started Mar 19 12:29:30 PM PDT 24
Finished Mar 19 12:32:26 PM PDT 24
Peak memory 201800 kb
Host smart-705daea6-aee2-4986-9398-684ad82f01bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618310001 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.618310001
Directory /workspace/5.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled_fixed.3410574468
Short name T669
Test name
Test status
Simulation time 160367767058 ps
CPU time 204.98 seconds
Started Mar 19 12:28:43 PM PDT 24
Finished Mar 19 12:32:09 PM PDT 24
Peak memory 201804 kb
Host smart-0381d60f-d1e1-4219-86e1-59e5b440c6f0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410574468 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixe
d.3410574468
Directory /workspace/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup.3236631334
Short name T594
Test name
Test status
Simulation time 171221940244 ps
CPU time 404.46 seconds
Started Mar 19 12:28:49 PM PDT 24
Finished Mar 19 12:35:34 PM PDT 24
Peak memory 201752 kb
Host smart-3f603a27-fb41-4a61-b622-5b79677112b6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236631334 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_
wakeup.3236631334
Directory /workspace/5.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup_fixed.1505542478
Short name T772
Test name
Test status
Simulation time 206490530269 ps
CPU time 487.2 seconds
Started Mar 19 12:28:54 PM PDT 24
Finished Mar 19 12:37:01 PM PDT 24
Peak memory 201792 kb
Host smart-b8da303e-6adc-4b74-b4c2-584bf9e01e48
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505542478 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.
adc_ctrl_filters_wakeup_fixed.1505542478
Directory /workspace/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_fsm_reset.3519475599
Short name T473
Test name
Test status
Simulation time 106953259091 ps
CPU time 542.65 seconds
Started Mar 19 12:29:27 PM PDT 24
Finished Mar 19 12:38:30 PM PDT 24
Peak memory 202220 kb
Host smart-47690e24-9052-4fee-946e-9e0671805696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519475599 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.3519475599
Directory /workspace/5.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_lowpower_counter.1238330006
Short name T485
Test name
Test status
Simulation time 25004677361 ps
CPU time 14.98 seconds
Started Mar 19 12:29:07 PM PDT 24
Finished Mar 19 12:29:22 PM PDT 24
Peak memory 201556 kb
Host smart-4c0a39e7-0bf3-4f7b-94f0-2f032e108085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238330006 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.1238330006
Directory /workspace/5.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_poweron_counter.1858704141
Short name T537
Test name
Test status
Simulation time 4542803500 ps
CPU time 3.38 seconds
Started Mar 19 12:28:53 PM PDT 24
Finished Mar 19 12:28:57 PM PDT 24
Peak memory 201568 kb
Host smart-a5e5f3c5-ed6c-4c78-85eb-8dad492e6ef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858704141 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.1858704141
Directory /workspace/5.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_smoke.1543613457
Short name T738
Test name
Test status
Simulation time 6017018536 ps
CPU time 7.81 seconds
Started Mar 19 12:28:59 PM PDT 24
Finished Mar 19 12:29:08 PM PDT 24
Peak memory 201564 kb
Host smart-0097ed1f-eb08-49b5-8133-e8d90efc9536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543613457 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.1543613457
Directory /workspace/5.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.3546325177
Short name T722
Test name
Test status
Simulation time 22795977370 ps
CPU time 46.74 seconds
Started Mar 19 12:28:41 PM PDT 24
Finished Mar 19 12:29:29 PM PDT 24
Peak memory 201928 kb
Host smart-d5b93ee9-b8e9-474f-bdc6-eba89e612e1a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546325177 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all_with_rand_reset.3546325177
Directory /workspace/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_alert_test.1886370134
Short name T569
Test name
Test status
Simulation time 338601500 ps
CPU time 0.75 seconds
Started Mar 19 12:29:30 PM PDT 24
Finished Mar 19 12:29:31 PM PDT 24
Peak memory 201496 kb
Host smart-73faab34-dc6f-4a33-bfd0-ee57082ff196
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886370134 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.1886370134
Directory /workspace/6.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.adc_ctrl_clock_gating.630978397
Short name T237
Test name
Test status
Simulation time 170059233184 ps
CPU time 113.99 seconds
Started Mar 19 12:29:04 PM PDT 24
Finished Mar 19 12:30:58 PM PDT 24
Peak memory 201720 kb
Host smart-4c321d85-4fbe-43e0-8d6e-717a64b5d894
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630978397 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gatin
g.630978397
Directory /workspace/6.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_both.424435516
Short name T168
Test name
Test status
Simulation time 360393207692 ps
CPU time 126.6 seconds
Started Mar 19 12:29:33 PM PDT 24
Finished Mar 19 12:31:39 PM PDT 24
Peak memory 201764 kb
Host smart-ee47c184-3169-40cd-a45d-86466c79a615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424435516 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.424435516
Directory /workspace/6.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt.1402960816
Short name T142
Test name
Test status
Simulation time 337697479627 ps
CPU time 229.48 seconds
Started Mar 19 12:29:02 PM PDT 24
Finished Mar 19 12:32:51 PM PDT 24
Peak memory 201008 kb
Host smart-f704c93a-12c3-4be7-9ae6-0c5ca39ee354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402960816 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.1402960816
Directory /workspace/6.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt_fixed.219830470
Short name T715
Test name
Test status
Simulation time 167635217936 ps
CPU time 176.09 seconds
Started Mar 19 12:28:45 PM PDT 24
Finished Mar 19 12:31:41 PM PDT 24
Peak memory 201716 kb
Host smart-98a6a41e-e5a3-4964-859d-d89c0a36b459
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=219830470 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt
_fixed.219830470
Directory /workspace/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled.308927690
Short name T424
Test name
Test status
Simulation time 488798516489 ps
CPU time 1219.54 seconds
Started Mar 19 12:28:45 PM PDT 24
Finished Mar 19 12:49:05 PM PDT 24
Peak memory 201748 kb
Host smart-d22f8831-e9e4-483b-849d-1b0ffa0f8585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308927690 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.308927690
Directory /workspace/6.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.540169450
Short name T87
Test name
Test status
Simulation time 168144658293 ps
CPU time 93.09 seconds
Started Mar 19 12:28:39 PM PDT 24
Finished Mar 19 12:30:13 PM PDT 24
Peak memory 201724 kb
Host smart-529b4747-317d-4f47-abc4-95f329f7a179
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=540169450 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixed
.540169450
Directory /workspace/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup.4031037751
Short name T747
Test name
Test status
Simulation time 403526686651 ps
CPU time 275.33 seconds
Started Mar 19 12:29:02 PM PDT 24
Finished Mar 19 12:33:38 PM PDT 24
Peak memory 201836 kb
Host smart-77d8d438-5716-48b3-a888-b6d8dc89a13f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031037751 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_
wakeup.4031037751
Directory /workspace/6.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup_fixed.1418984081
Short name T47
Test name
Test status
Simulation time 592273173901 ps
CPU time 1177.66 seconds
Started Mar 19 12:28:43 PM PDT 24
Finished Mar 19 12:48:21 PM PDT 24
Peak memory 201740 kb
Host smart-f24f5627-dbf3-4efb-b783-16ae733310c1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418984081 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.
adc_ctrl_filters_wakeup_fixed.1418984081
Directory /workspace/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_fsm_reset.3540055714
Short name T216
Test name
Test status
Simulation time 146357108366 ps
CPU time 397.4 seconds
Started Mar 19 12:28:58 PM PDT 24
Finished Mar 19 12:35:37 PM PDT 24
Peak memory 202116 kb
Host smart-36c162b1-337e-4354-8bfc-57ddfc02ea3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540055714 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.3540055714
Directory /workspace/6.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_lowpower_counter.3293923647
Short name T156
Test name
Test status
Simulation time 26193112144 ps
CPU time 61.99 seconds
Started Mar 19 12:28:45 PM PDT 24
Finished Mar 19 12:29:53 PM PDT 24
Peak memory 201568 kb
Host smart-dcaa2448-ef7a-4f66-ac41-31a74e79a79b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293923647 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.3293923647
Directory /workspace/6.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_poweron_counter.1999800345
Short name T171
Test name
Test status
Simulation time 3425197476 ps
CPU time 8.41 seconds
Started Mar 19 12:28:53 PM PDT 24
Finished Mar 19 12:29:02 PM PDT 24
Peak memory 201580 kb
Host smart-6f5d05a3-4b8c-4075-85dc-658d8b1e6c8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999800345 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.1999800345
Directory /workspace/6.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_smoke.2554501818
Short name T438
Test name
Test status
Simulation time 5991683841 ps
CPU time 14.53 seconds
Started Mar 19 12:28:42 PM PDT 24
Finished Mar 19 12:28:57 PM PDT 24
Peak memory 201556 kb
Host smart-a61b0b04-6ebf-4e3a-ac8d-f74a9e2fdf64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554501818 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.2554501818
Directory /workspace/6.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all.4023468958
Short name T280
Test name
Test status
Simulation time 167048053808 ps
CPU time 176.58 seconds
Started Mar 19 12:29:36 PM PDT 24
Finished Mar 19 12:32:33 PM PDT 24
Peak memory 201760 kb
Host smart-431de924-bf8d-475d-a593-e68a9ffb6517
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023468958 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.
4023468958
Directory /workspace/6.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.595527979
Short name T91
Test name
Test status
Simulation time 78601390929 ps
CPU time 168.78 seconds
Started Mar 19 12:29:40 PM PDT 24
Finished Mar 19 12:32:29 PM PDT 24
Peak memory 217844 kb
Host smart-c751c2ac-b84a-4f5d-8254-47e7acc2a87b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595527979 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all_with_rand_reset.595527979
Directory /workspace/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_alert_test.524918367
Short name T94
Test name
Test status
Simulation time 346579086 ps
CPU time 1.05 seconds
Started Mar 19 12:29:02 PM PDT 24
Finished Mar 19 12:29:03 PM PDT 24
Peak memory 201440 kb
Host smart-f8f31eb7-fb51-4562-8048-5de3f1932201
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524918367 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.524918367
Directory /workspace/7.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.adc_ctrl_clock_gating.1385302021
Short name T700
Test name
Test status
Simulation time 190005434883 ps
CPU time 431.02 seconds
Started Mar 19 12:28:43 PM PDT 24
Finished Mar 19 12:35:54 PM PDT 24
Peak memory 201860 kb
Host smart-1533337b-6f86-4dfa-a521-b544a3deae5b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385302021 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gati
ng.1385302021
Directory /workspace/7.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt_fixed.2236645658
Short name T778
Test name
Test status
Simulation time 168930418354 ps
CPU time 404.18 seconds
Started Mar 19 12:29:36 PM PDT 24
Finished Mar 19 12:36:21 PM PDT 24
Peak memory 201788 kb
Host smart-dc7552c6-d13b-4b5f-9105-4794946f1d86
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236645658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrup
t_fixed.2236645658
Directory /workspace/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled.1469370254
Short name T145
Test name
Test status
Simulation time 491525341453 ps
CPU time 1280.34 seconds
Started Mar 19 12:28:28 PM PDT 24
Finished Mar 19 12:49:49 PM PDT 24
Peak memory 201780 kb
Host smart-6eb503f4-5c86-420d-824c-bcc452bf9cf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469370254 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.1469370254
Directory /workspace/7.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled_fixed.2517328817
Short name T719
Test name
Test status
Simulation time 492608698235 ps
CPU time 1248.05 seconds
Started Mar 19 12:28:53 PM PDT 24
Finished Mar 19 12:49:42 PM PDT 24
Peak memory 201804 kb
Host smart-28de2c78-10d0-4394-b1d0-cdce7cf3b374
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517328817 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixe
d.2517328817
Directory /workspace/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup.3456622168
Short name T218
Test name
Test status
Simulation time 182072872565 ps
CPU time 426.72 seconds
Started Mar 19 12:29:36 PM PDT 24
Finished Mar 19 12:36:43 PM PDT 24
Peak memory 201764 kb
Host smart-099123b7-f75d-4598-bc13-8fe8696c7924
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456622168 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_
wakeup.3456622168
Directory /workspace/7.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup_fixed.1380370040
Short name T570
Test name
Test status
Simulation time 397618336031 ps
CPU time 262.66 seconds
Started Mar 19 12:28:40 PM PDT 24
Finished Mar 19 12:33:03 PM PDT 24
Peak memory 201836 kb
Host smart-74ab242b-57f8-46de-9f9a-459eb1a1fb8f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380370040 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.
adc_ctrl_filters_wakeup_fixed.1380370040
Directory /workspace/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_fsm_reset.2853393389
Short name T56
Test name
Test status
Simulation time 81522936278 ps
CPU time 471.55 seconds
Started Mar 19 12:29:02 PM PDT 24
Finished Mar 19 12:36:53 PM PDT 24
Peak memory 202124 kb
Host smart-900c96f1-dc7f-4fc8-8d7f-a3a89ef6c1e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853393389 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.2853393389
Directory /workspace/7.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_lowpower_counter.2754571153
Short name T756
Test name
Test status
Simulation time 39882289593 ps
CPU time 23.76 seconds
Started Mar 19 12:29:02 PM PDT 24
Finished Mar 19 12:29:26 PM PDT 24
Peak memory 200936 kb
Host smart-e69fa56f-f75d-40f7-abc9-3acac9e787ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754571153 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.2754571153
Directory /workspace/7.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_poweron_counter.2434169134
Short name T105
Test name
Test status
Simulation time 5061894137 ps
CPU time 12.78 seconds
Started Mar 19 12:29:00 PM PDT 24
Finished Mar 19 12:29:13 PM PDT 24
Peak memory 201216 kb
Host smart-9cdcc4b5-c918-4e93-8fff-7df6c4cce742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434169134 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.2434169134
Directory /workspace/7.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_smoke.706693753
Short name T765
Test name
Test status
Simulation time 5679049046 ps
CPU time 5.43 seconds
Started Mar 19 12:29:25 PM PDT 24
Finished Mar 19 12:29:30 PM PDT 24
Peak memory 201564 kb
Host smart-e25dc827-a4af-423f-a6eb-04015cb7c406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706693753 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.706693753
Directory /workspace/7.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.2032512133
Short name T22
Test name
Test status
Simulation time 56829496142 ps
CPU time 158.17 seconds
Started Mar 19 12:29:40 PM PDT 24
Finished Mar 19 12:32:18 PM PDT 24
Peak memory 210488 kb
Host smart-659d66c7-e42c-450d-b441-54aa226cda8d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032512133 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all_with_rand_reset.2032512133
Directory /workspace/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_alert_test.4258586702
Short name T429
Test name
Test status
Simulation time 322380768 ps
CPU time 0.85 seconds
Started Mar 19 12:29:00 PM PDT 24
Finished Mar 19 12:29:01 PM PDT 24
Peak memory 201512 kb
Host smart-747f28e2-767a-4518-8670-bf4174fc2e4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258586702 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.4258586702
Directory /workspace/8.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_both.4051022198
Short name T283
Test name
Test status
Simulation time 171410484591 ps
CPU time 378.12 seconds
Started Mar 19 12:28:47 PM PDT 24
Finished Mar 19 12:35:06 PM PDT 24
Peak memory 201732 kb
Host smart-68788480-fdac-46d8-b38c-bb49a89505ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051022198 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.4051022198
Directory /workspace/8.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt.3824867222
Short name T150
Test name
Test status
Simulation time 166114929135 ps
CPU time 88.01 seconds
Started Mar 19 12:28:57 PM PDT 24
Finished Mar 19 12:30:26 PM PDT 24
Peak memory 201744 kb
Host smart-e3cf8870-1208-4343-a027-9262245f8783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824867222 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.3824867222
Directory /workspace/8.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt_fixed.204012711
Short name T390
Test name
Test status
Simulation time 491432325051 ps
CPU time 613.56 seconds
Started Mar 19 12:29:00 PM PDT 24
Finished Mar 19 12:39:14 PM PDT 24
Peak memory 201432 kb
Host smart-70c72582-cc25-4b9a-b6e9-1b89683e049b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=204012711 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt
_fixed.204012711
Directory /workspace/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled.491475826
Short name T776
Test name
Test status
Simulation time 320168457671 ps
CPU time 384.8 seconds
Started Mar 19 12:28:47 PM PDT 24
Finished Mar 19 12:35:12 PM PDT 24
Peak memory 201804 kb
Host smart-1f713fe1-6361-43b0-9bdf-8c5e98a54a03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491475826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.491475826
Directory /workspace/8.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.41227836
Short name T651
Test name
Test status
Simulation time 330079414815 ps
CPU time 217.28 seconds
Started Mar 19 12:28:50 PM PDT 24
Finished Mar 19 12:32:28 PM PDT 24
Peak memory 201788 kb
Host smart-6635bb13-033b-4275-955b-71d0ae74e5ff
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=41227836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixed.41227836
Directory /workspace/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup.2630242634
Short name T309
Test name
Test status
Simulation time 438636252874 ps
CPU time 1000.33 seconds
Started Mar 19 12:28:46 PM PDT 24
Finished Mar 19 12:45:27 PM PDT 24
Peak memory 201716 kb
Host smart-a0757c9f-2fd6-47f1-8fee-9b9865b07826
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630242634 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_
wakeup.2630242634
Directory /workspace/8.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup_fixed.3969330335
Short name T441
Test name
Test status
Simulation time 204003161786 ps
CPU time 117.89 seconds
Started Mar 19 12:29:02 PM PDT 24
Finished Mar 19 12:31:00 PM PDT 24
Peak memory 201804 kb
Host smart-8c572fb5-fc6d-4617-898f-01ec2a035515
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969330335 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.
adc_ctrl_filters_wakeup_fixed.3969330335
Directory /workspace/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_fsm_reset.2341051185
Short name T206
Test name
Test status
Simulation time 129792958373 ps
CPU time 628.93 seconds
Started Mar 19 12:28:57 PM PDT 24
Finished Mar 19 12:39:27 PM PDT 24
Peak memory 202132 kb
Host smart-ca9a3110-5a9b-47fb-8784-25141d006674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341051185 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.2341051185
Directory /workspace/8.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_lowpower_counter.1597902110
Short name T84
Test name
Test status
Simulation time 44533637278 ps
CPU time 28.51 seconds
Started Mar 19 12:29:02 PM PDT 24
Finished Mar 19 12:29:30 PM PDT 24
Peak memory 201552 kb
Host smart-3a2a8304-7394-406f-b9c2-7af43e380487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597902110 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.1597902110
Directory /workspace/8.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_poweron_counter.2919360817
Short name T788
Test name
Test status
Simulation time 3372654148 ps
CPU time 7.91 seconds
Started Mar 19 12:28:54 PM PDT 24
Finished Mar 19 12:29:03 PM PDT 24
Peak memory 201524 kb
Host smart-f42b1a56-c3c5-41f3-abd3-63545849c298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919360817 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.2919360817
Directory /workspace/8.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_smoke.1425420914
Short name T359
Test name
Test status
Simulation time 5608382550 ps
CPU time 4.04 seconds
Started Mar 19 12:28:47 PM PDT 24
Finished Mar 19 12:28:51 PM PDT 24
Peak memory 201564 kb
Host smart-ee0d1b45-554b-44d8-8a26-3bf525dcd62e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425420914 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.1425420914
Directory /workspace/8.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all.2107425600
Short name T487
Test name
Test status
Simulation time 122475886137 ps
CPU time 394.6 seconds
Started Mar 19 12:28:56 PM PDT 24
Finished Mar 19 12:35:32 PM PDT 24
Peak memory 202036 kb
Host smart-804bf4e2-7b3d-49e5-a249-10508a0574fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107425600 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.
2107425600
Directory /workspace/8.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.adc_ctrl_alert_test.4175111617
Short name T357
Test name
Test status
Simulation time 364245535 ps
CPU time 1.02 seconds
Started Mar 19 12:29:22 PM PDT 24
Finished Mar 19 12:29:24 PM PDT 24
Peak memory 201448 kb
Host smart-77fe6b1c-f736-4f33-bd01-c8afae261827
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175111617 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.4175111617
Directory /workspace/9.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.adc_ctrl_clock_gating.3594740630
Short name T45
Test name
Test status
Simulation time 173284692261 ps
CPU time 398.79 seconds
Started Mar 19 12:28:48 PM PDT 24
Finished Mar 19 12:35:28 PM PDT 24
Peak memory 201832 kb
Host smart-069aff76-3a19-4941-baf5-54cb85177928
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594740630 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gati
ng.3594740630
Directory /workspace/9.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt.675886241
Short name T298
Test name
Test status
Simulation time 168272662361 ps
CPU time 400.09 seconds
Started Mar 19 12:29:06 PM PDT 24
Finished Mar 19 12:35:47 PM PDT 24
Peak memory 201744 kb
Host smart-cdf707c7-b8f3-4ffe-8839-5b9b7e49e513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675886241 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.675886241
Directory /workspace/9.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt_fixed.3026647265
Short name T205
Test name
Test status
Simulation time 331031540517 ps
CPU time 431.12 seconds
Started Mar 19 12:28:51 PM PDT 24
Finished Mar 19 12:36:03 PM PDT 24
Peak memory 201752 kb
Host smart-38cbe7ec-ca1f-4444-a3ad-c0e39313f11d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026647265 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrup
t_fixed.3026647265
Directory /workspace/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled.220055563
Short name T28
Test name
Test status
Simulation time 170344336944 ps
CPU time 75.33 seconds
Started Mar 19 12:29:02 PM PDT 24
Finished Mar 19 12:30:17 PM PDT 24
Peak memory 201740 kb
Host smart-d41f5f8c-09cb-4c64-88a7-4b01864a5578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220055563 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.220055563
Directory /workspace/9.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled_fixed.1757564982
Short name T685
Test name
Test status
Simulation time 490969421181 ps
CPU time 304.91 seconds
Started Mar 19 12:28:46 PM PDT 24
Finished Mar 19 12:33:51 PM PDT 24
Peak memory 201804 kb
Host smart-0be526bf-06b3-484f-acf8-bedf4b42a489
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757564982 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixe
d.1757564982
Directory /workspace/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup.4072366639
Short name T624
Test name
Test status
Simulation time 170588597439 ps
CPU time 399.56 seconds
Started Mar 19 12:28:53 PM PDT 24
Finished Mar 19 12:35:33 PM PDT 24
Peak memory 201796 kb
Host smart-bc40b67e-8fbc-476a-aecb-6b97f858a096
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072366639 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_
wakeup.4072366639
Directory /workspace/9.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup_fixed.1001477839
Short name T163
Test name
Test status
Simulation time 194902126254 ps
CPU time 52.67 seconds
Started Mar 19 12:28:50 PM PDT 24
Finished Mar 19 12:29:44 PM PDT 24
Peak memory 201836 kb
Host smart-fc20c72e-dc0a-408c-9b26-33d115810fef
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001477839 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.
adc_ctrl_filters_wakeup_fixed.1001477839
Directory /workspace/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_lowpower_counter.2908877394
Short name T352
Test name
Test status
Simulation time 26849692873 ps
CPU time 54.54 seconds
Started Mar 19 12:29:08 PM PDT 24
Finished Mar 19 12:30:03 PM PDT 24
Peak memory 201572 kb
Host smart-0aee8952-05c4-4868-87ba-c71ead770f61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908877394 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.2908877394
Directory /workspace/9.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_poweron_counter.1170575367
Short name T458
Test name
Test status
Simulation time 3350217868 ps
CPU time 2.62 seconds
Started Mar 19 12:29:05 PM PDT 24
Finished Mar 19 12:29:08 PM PDT 24
Peak memory 201572 kb
Host smart-716b40fe-1e67-4d97-846f-179d90b42501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170575367 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.1170575367
Directory /workspace/9.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_smoke.1625018139
Short name T384
Test name
Test status
Simulation time 5687055639 ps
CPU time 4.86 seconds
Started Mar 19 12:29:10 PM PDT 24
Finished Mar 19 12:29:15 PM PDT 24
Peak memory 201624 kb
Host smart-10d6427a-04a3-4c24-b347-24209446917b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625018139 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.1625018139
Directory /workspace/9.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all.2211188966
Short name T551
Test name
Test status
Simulation time 11309325702 ps
CPU time 26.26 seconds
Started Mar 19 12:28:48 PM PDT 24
Finished Mar 19 12:29:16 PM PDT 24
Peak memory 201744 kb
Host smart-d32c2383-e315-41b2-a18d-ff17b31e7610
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211188966 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.
2211188966
Directory /workspace/9.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.4226828280
Short name T502
Test name
Test status
Simulation time 63279077202 ps
CPU time 149.79 seconds
Started Mar 19 12:28:59 PM PDT 24
Finished Mar 19 12:31:29 PM PDT 24
Peak memory 201924 kb
Host smart-31260279-5bf4-47bb-ab3f-a4b3bfdebb05
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226828280 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.4226828280
Directory /workspace/9.adc_ctrl_stress_all_with_rand_reset/latest
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