Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

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Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	7434	1			T1	46		T3	20		T7	9
testmodes[AdcCtrlTestmodeNormal]	5852	1			T1	47		T5	1		T7	5
testmodes[AdcCtrlTestmodeLowpower]	6111	1			T1	60		T2	2		T5	1
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	4104	1			T1	15		T3	19		T7	5
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1798	1			T1	11		T7	3		T36	18
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1423	1			T1	20		T36	19		T13	3
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1831	1			T1	14		T7	3		T36	24
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	2184	1			T1	14		T7	2		T36	22
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1491	1			T1	18		T5	1		T36	19
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1383	1			T1	17		T36	12		T13	4
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1532	1			T1	22		T9	1		T36	25
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2954	1			T1	21		T2	1		T6	2