Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27970

1

T1

156

T2

19

T3

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

24443

1

T1

156

T2

8

T3

20

auto[ADC_CTRL_FILTER_COND_OUT]

3527

1

T2

11

T5

17

T6

19

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21798

1

T1

156

T2

11

T3

20

auto[1]

6172

1

T2

8

T5

17

T6

26

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23680

1

T1

153

T2

19

T3

20

auto[1]

4290

1

T1

3

T5

19

T9

14

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	22	1			T15	4		T223	18		-	-
values[0]	44	1			T224	12		T225	21		T226	1
values[1]	634	1			T2	8		T11	15		T13	13
values[2]	760	1			T131	17		T125	13		T141	1
values[3]	910	1			T6	7		T11	5		T48	1
values[4]	905	1			T5	26		T48	1		T125	18
values[5]	832	1			T6	19		T9	16		T44	44
values[6]	554	1			T2	11		T10	15		T12	14
values[7]	703	1			T5	17		T9	19		T14	39
values[8]	543	1			T14	9		T128	14		T130	17
values[9]	3619	1			T41	50		T43	19		T132	16
minimum	18444	1			T1	156		T3	20		T7	14

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	978	1			T2	8		T11	15		T13	13
values[1]	772	1			T11	5		T131	17		T125	13
values[2]	851	1			T5	26		T6	7		T48	2
values[3]	936	1			T6	7		T48	1		T16	32
values[4]	680	1			T6	12		T9	16		T12	14
values[5]	618	1			T2	11		T5	17		T9	19
values[6]	2951	1			T41	50		T43	19		T105	23
values[7]	660	1			T14	9		T132	12		T33	1
values[8]	944	1			T15	4		T132	4		T106	60
values[9]	135	1			T134	2		T140	13		T227	14
minimum	18445	1			T1	156		T3	20		T7	14

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23687

1

T1

156

T2

2

T3

20

auto[1]

4283

1

T2

17

T5

22

T6

23

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	297	1			T2	8		T11	8		T13	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T15	13		T44	10		T106	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T131	1		T127	1		T130	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T11	3		T131	1		T125	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T5	15		T6	7		T125	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T48	2		T30	12		T141	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T48	1		T16	16		T37	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T6	7		T33	1		T135	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T12	14		T44	23		T26	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T6	12		T9	10		T37	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T9	11		T10	5		T228	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T2	11		T5	9		T14	19
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1702	1			T41	50		T43	2		T105	23
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T30	11		T229	3		T227	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T14	5		T132	1		T127	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T33	1		T128	12		T138	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T15	1		T182	1		T126	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	359	1			T132	1		T106	29		T182	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T47	6		T230	9		T223	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T134	1		T140	4		T227	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18289	1			T1	153		T3	20		T7	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T11	7		T13	3		T131	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T15	11		T44	7		T181	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	303	1			T131	15		T130	9		T144	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T11	2		T160	7		T79	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T5	11		T134	11		T34	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T159	4		T231	2		T232	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T16	16		T37	1		T233	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T33	1		T135	14		T129	19
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T44	21		T26	6		T138	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T9	6		T37	1		T129	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T9	8		T10	10		T234	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T5	8		T14	20		T129	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	950	1			T43	17		T183	13		T136	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T229	9		T227	2		T235	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T14	4		T132	11		T130	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T128	2		T138	7		T147	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T15	3		T37	2		T135	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T132	3		T106	31		T126	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T47	6		T230	3		T223	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T134	1		T140	9		T227	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T1	3		T13	4		T33	4

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T15	1		T223	9		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T224	1		T225	21		T226	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T2	8		T11	8		T13	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T15	13		T44	10		T106	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T131	1		T141	1		T130	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T131	1		T125	13		T236	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T6	7		T30	7		T34	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T11	3		T48	1		T141	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T5	15		T125	18		T134	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T48	1		T30	12		T33	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T44	23		T48	1		T26	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T6	19		T9	10		T37	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T10	5		T12	14		T228	26
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T2	11		T129	3		T206	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T9	11		T127	1		T145	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T5	9		T14	19		T30	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T14	5		T130	9		T237	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T128	12		T38	7		T229	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1821	1			T41	50		T43	2		T132	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	434	1			T132	1		T106	29		T182	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18288	1			T1	153		T3	20		T7	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T15	3		T223	9		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T224	11		T207	1		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T11	7		T13	3		T131	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T15	11		T44	7		T181	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T131	15		T130	9		T144	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T160	7		T149	10		T204	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T34	11		T159	10		T229	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T11	2		T232	7		T149	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T5	11		T134	11		T16	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T33	1		T135	14		T159	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T44	21		T26	6		T138	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T9	6		T37	1		T129	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T10	10		T139	11		T234	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T129	13		T143	12		T204	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T9	8		T145	14		T152	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T5	8		T14	20		T235	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T14	4		T130	8		T237	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T128	2		T38	4		T229	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1068	1			T43	17		T132	11		T183	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	296	1			T132	3		T106	31		T126	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T1	3		T13	4		T33	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	302	1			T2	1		T11	8		T13	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T15	12		T44	8		T106	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	346	1			T131	16		T127	1		T130	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T11	3		T131	1		T125	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T5	12		T6	1		T125	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T48	2		T30	1		T141	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T48	1		T16	22		T37	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T6	1		T33	2		T135	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T12	1		T44	23		T26	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T6	1		T9	7		T37	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T9	9		T10	11		T228	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T2	1		T5	9		T14	21
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1294	1			T41	3		T43	19		T105	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T30	1		T229	10		T227	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T14	6		T132	12		T127	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T33	1		T128	3		T138	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T15	4		T182	1		T126	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T132	4		T106	33		T182	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T47	8		T230	8		T223	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T134	2		T140	10		T227	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18445	1			T1	156		T3	20		T7	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T2	7		T11	7		T13	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T15	12		T44	9		T106	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T130	2		T229	8		T238	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T11	2		T125	12		T160	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T5	14		T6	6		T125	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T30	11		T231	14		T232	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T16	10		T239	14		T240	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T6	6		T135	17		T129	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T12	13		T44	21		T26	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T6	11		T9	9		T37	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T9	10		T10	4		T228	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T2	10		T5	8		T14	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1358	1			T41	47		T105	21		T241	40
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T30	10		T229	2		T227	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T14	3		T130	8		T140	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T128	11		T147	14		T162	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T126	2		T37	1		T135	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	308	1			T106	27		T126	13		T236	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T47	4		T230	4		T223	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T140	3		T227	4		T242	9

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T15	4		T223	10		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T224	12		T225	1		T226	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T2	1		T11	8		T13	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T15	12		T44	8		T106	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	328	1			T131	16		T141	1		T130	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T131	1		T125	1		T236	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	296	1			T6	1		T30	1		T34	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T11	3		T48	1		T141	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T5	12		T125	1		T134	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T48	1		T30	1		T33	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T44	23		T48	1		T26	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T6	2		T9	7		T37	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T10	11		T12	1		T228	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T2	1		T129	14		T206	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T9	9		T127	1		T145	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T5	9		T14	21		T30	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T14	6		T130	9		T237	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T128	3		T38	8		T229	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1440	1			T41	3		T43	19		T132	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	359	1			T132	4		T106	33		T182	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18444	1			T1	156		T3	20		T7	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T223	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T225	20		T188	5		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T2	7		T11	7		T13	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T15	12		T44	9		T106	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T130	2		T238	11		T243	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T125	12		T236	1		T160	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T6	6		T30	6		T34	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T11	2		T232	8		T244	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T5	14		T125	17		T134	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T30	11		T135	17		T129	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T44	21		T26	4		T245	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T6	17		T9	9		T37	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T10	4		T12	13		T228	24
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T2	10		T129	2		T228	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T9	10		T145	15		T246	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T5	8		T14	18		T30	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T14	3		T130	8		T245	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T128	11		T38	3		T229	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1449	1			T41	47		T105	21		T126	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	371	1			T106	27		T126	13		T236	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23687

1

T1

156

T2

2

T3

20

auto[1]

auto[0]

4283

1

T2

17

T5

22

T6

23

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27970

1

T1

156

T2

19

T3

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21673

1

T1

156

T2

8

T3

20

auto[ADC_CTRL_FILTER_COND_OUT]

6297

1

T2

11

T5

43

T6

7

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21776

1

T1

156

T3

20

T5

17

auto[1]

6194

1

T2

19

T5

26

T6

7

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23680

1

T1

153

T2

19

T3

20

auto[1]

4290

1

T1

3

T5

19

T9

14

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	31	1			T39	5		T150	25		T52	1
values[0]	14	1			T234	14		-	-		-	-
values[1]	559	1			T5	17		T48	1		T125	7
values[2]	790	1			T132	14		T106	3		T182	1
values[3]	629	1			T132	12		T181	10		T33	5
values[4]	577	1			T2	11		T6	7		T13	13
values[5]	817	1			T6	12		T15	4		T131	16
values[6]	738	1			T11	5		T14	3		T15	24
values[7]	870	1			T2	8		T6	7		T10	15
values[8]	750	1			T9	19		T14	6		T44	17
values[9]	3751	1			T5	26		T9	16		T11	15
minimum	18444	1			T1	156		T3	20		T7	14

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	791	1			T5	17		T48	1		T125	7
values[1]	3060	1			T41	50		T43	19		T132	26
values[2]	639	1			T106	38		T125	13		T181	10
values[3]	731	1			T2	11		T6	7		T13	13
values[4]	685	1			T6	12		T11	5		T14	3
values[5]	829	1			T14	39		T15	24		T44	19
values[6]	801	1			T2	8		T6	7		T10	15
values[7]	718	1			T9	35		T14	6		T44	17
values[8]	950	1			T11	15		T12	14		T131	1
values[9]	310	1			T5	26		T48	1		T32	4
minimum	18456	1			T1	156		T3	20		T7	14

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23687

1

T1

156

T2

2

T3

20

auto[1]

4283

1

T2

17

T5

22

T6

23

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T125	7		T30	7		T135	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T5	9		T48	1		T182	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T132	1		T126	3		T30	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1668	1			T41	50		T43	2		T132	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T106	3		T33	2		T127	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T106	17		T125	13		T181	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T15	1		T141	1		T144	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T2	11		T6	7		T13	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T6	12		T11	3		T44	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T14	2		T182	1		T34	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T14	19		T15	13		T126	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T44	10		T131	1		T106	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T2	8		T6	7		T134	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T10	5		T206	1		T144	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T9	10		T44	10		T33	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T9	11		T14	3		T48	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	290	1			T131	1		T135	18		T160	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T11	8		T12	14		T132	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T48	1		T140	4		T162	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T5	15		T32	4		T145	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18288	1			T1	153		T3	20		T7	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T247	1		T248	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T135	9		T129	6		T249	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T5	8		T129	13		T139	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T132	11		T135	15		T231	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1015	1			T43	17		T132	13		T183	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T33	1		T227	2		T164	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T106	18		T181	2		T33	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T15	3		T144	9		T139	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T13	3		T131	15		T37	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T11	2		T44	12		T16	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T14	1		T34	11		T250	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T14	20		T15	11		T126	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T44	9		T131	2		T106	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T134	11		T16	8		T37	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T10	10		T144	13		T145	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T9	6		T44	7		T137	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T9	8		T14	3		T134	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T135	14		T160	7		T242	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T11	7		T132	3		T26	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T140	10		T162	10		T251	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T5	11		T145	1		T150	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T1	3		T13	4		T33	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T247	10		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T39	1		T150	12		T52	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T234	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T125	7		T126	3		T30	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T5	9		T48	1		T30	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T106	3		T30	11		T135	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T132	1		T182	1		T129	19
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T132	1		T33	2		T127	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T181	8		T33	1		T159	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T144	1		T139	14		T39	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T2	11		T6	7		T13	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T6	12		T15	1		T125	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T131	1		T182	1		T141	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T11	3		T15	13		T44	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T14	2		T106	12		T34	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T2	8		T6	7		T14	19
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T10	5		T44	10		T131	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T44	10		T131	1		T137	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T9	11		T14	3		T48	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	404	1			T9	10		T48	1		T33	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1945	1			T5	15		T11	8		T12	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18288	1			T1	153		T3	20		T7	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T39	4		T150	13		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T234	13		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T135	9		T129	6		T235	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T5	8		T139	1		T229	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T135	15		T232	7		T139	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T132	13		T129	32		T143	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T132	11		T33	1		T231	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T181	2		T33	1		T159	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T144	9		T139	11		T39	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T13	3		T106	18		T37	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T15	3		T128	2		T229	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T131	15		T38	2		T140	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T11	2		T15	11		T44	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T14	1		T106	13		T34	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T14	20		T126	14		T134	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T10	10		T44	9		T131	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T44	7		T137	13		T138	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T9	8		T14	3		T134	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T9	6		T135	14		T137	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1173	1			T5	11		T11	7		T43	17
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T1	3		T13	4		T33	4