Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27970

1

T1

156

T2

19

T3

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

24309

1

T1

156

T3

20

T5

26

auto[ADC_CTRL_FILTER_COND_OUT]

3661

1

T2

19

T5

17

T6

19

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21149

1

T1

155

T2

19

T3

20

auto[1]

6821

1

T1

1

T6

14

T9

19

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23680

1

T1

153

T2

19

T3

20

auto[1]

4290

1

T1

3

T5

19

T9

14

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	742	1			T1	1		T5	17		T11	5
values[0]	33	1			T48	1		T231	2		T274	1
values[1]	702	1			T12	14		T15	4		T106	35
values[2]	3030	1			T2	8		T41	50		T43	19
values[3]	646	1			T6	7		T9	16		T44	19
values[4]	731	1			T6	12		T131	1		T135	28
values[5]	763	1			T9	19		T106	25		T182	1
values[6]	709	1			T5	26		T6	7		T13	13
values[7]	871	1			T2	11		T132	12		T181	10
values[8]	787	1			T44	25		T125	7		T126	3
values[9]	989	1			T10	15		T11	15		T14	9
minimum	17967	1			T1	155		T3	20		T7	14

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	668	1			T12	14		T15	4		T48	1
values[1]	3132	1			T2	8		T6	7		T41	50
values[2]	616	1			T9	16		T44	19		T48	1
values[3]	769	1			T6	12		T131	1		T134	2
values[4]	809	1			T6	7		T9	19		T106	25
values[5]	759	1			T5	26		T13	13		T44	17
values[6]	772	1			T2	11		T44	25		T181	10
values[7]	764	1			T131	3		T125	7		T33	2
values[8]	1008	1			T5	17		T10	15		T11	15
values[9]	84	1			T11	5		T228	11		T146	13
minimum	18589	1			T1	156		T3	20		T7	14

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23687

1

T1

156

T2

2

T3

20

auto[1]

4283

1

T2

17

T5

22

T6

23

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T15	1		T106	17		T16	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T12	14		T48	1		T125	18
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1747	1			T41	50		T43	2		T105	23
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T2	8		T6	7		T125	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T48	1		T37	7		T141	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T9	10		T44	10		T135	19
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T131	1		T206	1		T38	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T6	12		T134	1		T127	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T6	7		T127	1		T130	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T9	11		T106	12		T182	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T5	15		T30	7		T231	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T13	10		T44	10		T48	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T181	8		T134	11		T143	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T2	11		T44	13		T126	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T131	1		T129	3		T144	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T125	7		T33	1		T128	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	300	1			T11	8		T14	21		T15	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T5	9		T10	5		T14	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T228	11		T292	8		T293	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T11	3		T146	13		T253	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18306	1			T1	153		T3	20		T7	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T229	3		T274	1		T230	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T15	3		T106	18		T16	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T138	5		T46	4		T82	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1014	1			T43	17		T183	13		T136	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T26	6		T160	7		T145	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T37	2		T137	9		T147	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T9	6		T44	9		T135	24
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T38	2		T138	7		T140	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T134	1		T159	4		T129	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T130	8		T237	4		T227	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T9	8		T106	13		T16	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T5	11		T231	2		T140	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T13	3		T44	7		T132	24
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T181	2		T134	11		T143	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T44	12		T129	19		T160	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T131	2		T129	6		T144	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T33	1		T128	2		T244	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T11	7		T14	21		T15	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T5	8		T10	10		T14	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T294	12		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T11	2		T253	4		T204	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T1	3		T13	4		T33	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T229	9		T230	3		T276	7

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	586	1			T1	1		T36	3		T13	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T5	9		T11	3		T79	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T231	1		T180	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T48	1		T274	1		T271	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T15	1		T106	17		T16	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T12	14		T125	18		T138	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1722	1			T41	50		T43	2		T105	23
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T2	8		T125	13		T26	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T48	1		T37	7		T141	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T6	7		T9	10		T44	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T131	1		T206	1		T228	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T6	12		T135	13		T127	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T127	1		T138	1		T186	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T9	11		T106	12		T182	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T5	15		T6	7		T30	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T13	10		T44	10		T48	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T181	8		T143	1		T144	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T2	11		T132	1		T232	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T134	11		T129	3		T144	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T44	13		T125	7		T126	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T11	8		T14	2		T15	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T10	5		T14	3		T33	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17811	1			T1	152		T3	20		T7	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T14	20		T135	14		T257	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T5	8		T11	2		T79	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T231	1		T180	13		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T15	3		T106	18		T16	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T138	5		T229	9		T295	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1017	1			T43	17		T183	13		T136	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T26	6		T46	4		T145	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T37	2		T137	9		T147	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T9	6		T44	9		T135	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T38	2		T140	9		T229	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T135	15		T159	4		T129	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T138	7		T237	4		T242	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T9	8		T106	13		T134	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T5	11		T130	8		T231	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T13	3		T44	7		T132	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T181	2		T143	12		T144	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T132	11		T232	7		T250	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T134	11		T129	6		T144	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T44	12		T128	2		T129	19
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T11	7		T14	1		T15	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T10	10		T14	3		T33	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T1	3		T13	4		T33	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T15	4		T106	19		T16	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T12	1		T48	1		T125	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1362	1			T41	3		T43	19		T105	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T2	1		T6	1		T125	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T48	1		T37	8		T141	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T9	7		T44	10		T135	26
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T131	1		T206	1		T38	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T6	1		T134	2		T127	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T6	1		T127	1		T130	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T9	9		T106	14		T182	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T5	12		T30	1		T231	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T13	10		T44	8		T48	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T181	3		T134	12		T143	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T2	1		T44	13		T126	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T131	3		T129	7		T144	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T125	1		T33	2		T128	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T11	8		T14	23		T15	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T5	9		T10	11		T14	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T228	1		T292	1		T293	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T11	3		T146	1		T253	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18487	1			T1	156		T3	20		T7	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T229	10		T274	1		T230	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T106	16		T16	6		T245	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T12	13		T125	17		T245	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1399	1			T41	47		T105	21		T241	40
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T2	7		T6	6		T125	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T37	1		T228	5		T137	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T9	9		T44	9		T135	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T140	3		T229	12		T186	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T6	11		T129	2		T38	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T6	6		T130	8		T227	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T9	10		T106	11		T16	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T5	14		T30	6		T231	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T13	3		T44	9		T232	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T181	7		T134	10		T227	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T2	10		T44	12		T126	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T129	2		T145	15		T296	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T125	6		T128	11		T239	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T11	7		T14	19		T15	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T5	8		T10	4		T14	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T228	10		T292	7		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T11	2		T146	12		T253	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T188	11		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T229	2		T230	4		T271	14

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	536	1			T1	1		T36	3		T13	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T5	9		T11	3		T79	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T231	2		T180	14		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T48	1		T274	1		T271	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T15	4		T106	19		T16	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T12	1		T125	1		T138	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1359	1			T41	3		T43	19		T105	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T2	1		T125	1		T26	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T48	1		T37	8		T141	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T6	1		T9	7		T44	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T131	1		T206	1		T228	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T6	1		T135	16		T127	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T127	1		T138	8		T186	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T9	9		T106	14		T182	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T5	12		T6	1		T30	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T13	10		T44	8		T48	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T181	3		T143	13		T144	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T2	1		T132	12		T232	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T134	12		T129	7		T144	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T44	13		T125	1		T126	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	289	1			T11	8		T14	2		T15	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T10	11		T14	4		T33	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17967	1			T1	155		T3	20		T7	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T14	18		T106	2		T135	17
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T5	8		T11	2		T79	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T271	14		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T106	16		T16	6		T245	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T12	13		T125	17		T229	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1380	1			T41	47		T105	21		T241	40
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T2	7		T125	12		T26	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T37	1		T137	12		T147	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T6	6		T9	9		T44	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T228	5		T140	3		T229	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T6	11		T135	12		T129	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T186	3		T254	4		T240	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T9	10		T106	11		T16	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T5	14		T6	6		T30	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T13	3		T44	9		T139	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T181	7		T140	3		T242	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T2	10		T232	8		T250	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T134	10		T129	2		T227	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T44	12		T125	6		T126	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T11	7		T14	1		T15	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T10	4		T14	2		T236	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23687

1

T1

156

T2

2

T3

20

auto[1]

auto[0]

4283

1

T2

17

T5

22

T6

23