Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27970

1

T1

156

T2

19

T3

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

24278

1

T1

156

T2

8

T3

20

auto[ADC_CTRL_FILTER_COND_OUT]

3692

1

T2

11

T5

17

T6

19

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21895

1

T1

156

T2

11

T3

20

auto[1]

6075

1

T2

8

T5

17

T6

26

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23680

1

T1

153

T2

19

T3

20

auto[1]

4290

1

T1

3

T5

19

T9

14

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	236	1			T15	4		T134	2		T135	15
values[0]	35	1			T297	1		T224	12		T225	21
values[1]	687	1			T2	8		T11	15		T13	13
values[2]	804	1			T11	5		T131	17		T125	13
values[3]	819	1			T6	7		T48	1		T125	18
values[4]	882	1			T5	26		T48	1		T134	22
values[5]	843	1			T6	19		T9	16		T44	44
values[6]	567	1			T2	11		T9	19		T10	15
values[7]	680	1			T5	17		T14	39		T30	11
values[8]	559	1			T14	9		T33	1		T127	1
values[9]	3414	1			T41	50		T43	19		T132	16
minimum	18444	1			T1	156		T3	20		T7	14

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	710	1			T2	8		T11	15		T15	24
values[1]	793	1			T11	5		T131	17		T125	13
values[2]	847	1			T5	26		T6	7		T48	2
values[3]	897	1			T6	7		T48	1		T16	32
values[4]	713	1			T6	12		T9	16		T12	14
values[5]	666	1			T2	11		T5	17		T9	19
values[6]	2934	1			T41	50		T43	19		T105	23
values[7]	599	1			T14	9		T132	12		T33	1
values[8]	1047	1			T15	4		T132	4		T106	60
values[9]	68	1			T140	13		T47	12		T149	6
minimum	18696	1			T1	156		T3	20		T7	14

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23687

1

T1

156

T2

2

T3

20

auto[1]

4283

1

T2

17

T5

22

T6

23

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T2	8		T11	8		T131	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T15	13		T106	3		T125	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T11	3		T131	1		T127	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T131	1		T125	13		T141	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T5	15		T6	7		T125	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T48	2		T30	12		T231	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T48	1		T16	16		T37	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T6	7		T33	1		T135	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T12	14		T44	23		T26	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T6	12		T9	10		T37	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T9	11		T10	5		T228	26
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T2	11		T5	9		T14	19
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1693	1			T41	50		T43	2		T105	23
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T30	11		T229	3		T227	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T14	5		T127	1		T130	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T132	1		T33	1		T128	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T15	1		T132	1		T182	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	414	1			T106	29		T182	1		T126	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T47	6		T268	14		T223	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T140	4		T149	1		T257	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18369	1			T1	153		T3	20		T7	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T44	10		T32	4		T33	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T11	7		T131	2		T132	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T15	11		T181	2		T46	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	299	1			T11	2		T131	15		T130	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T160	7		T238	15		T79	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T5	11		T134	11		T34	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T231	2		T232	7		T234	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T16	16		T37	1		T233	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T33	1		T135	14		T129	19
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T44	21		T26	6		T138	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T9	6		T37	1		T129	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T9	8		T10	10		T234	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T5	8		T14	20		T129	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	963	1			T43	17		T183	13		T136	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T229	9		T227	2		T235	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T14	4		T130	8		T140	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T132	11		T128	2		T138	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T15	3		T132	3		T37	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T106	31		T126	14		T134	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T47	6		T223	9		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T140	9		T149	5		T257	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T1	3		T13	7		T33	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T44	7		T33	1		T135	15

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T15	1		T135	6		T138	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T134	1		T140	4		T161	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T224	1		T225	21		T226	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T297	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T2	8		T11	8		T13	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T15	13		T44	10		T106	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T11	3		T131	1		T130	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T131	1		T125	13		T142	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T6	7		T125	18		T30	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T48	1		T141	1		T232	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T5	15		T134	11		T16	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T48	1		T30	12		T33	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T44	23		T48	1		T26	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T6	19		T9	10		T37	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T9	11		T10	5		T12	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T2	11		T129	3		T206	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T286	19		T160	3		T145	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T5	9		T14	19		T30	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T14	5		T127	1		T130	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T33	1		T128	12		T227	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1714	1			T41	50		T43	2		T132	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	427	1			T132	1		T106	29		T182	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18288	1			T1	153		T3	20		T7	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T15	3		T135	9		T138	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T134	1		T140	9		T250	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T224	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T11	7		T13	3		T131	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T15	11		T44	7		T181	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T11	2		T131	15		T130	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T160	7		T238	15		T204	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T34	11		T159	10		T145	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T232	7		T244	9		T79	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T5	11		T134	11		T16	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T33	1		T135	14		T129	19
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T44	21		T26	6		T138	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T9	6		T37	1		T129	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T9	8		T10	10		T139	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T129	13		T143	12		T204	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T160	9		T145	1		T152	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T5	8		T14	20		T229	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T14	4		T130	8		T237	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T128	2		T227	2		T145	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	973	1			T43	17		T132	3		T183	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	300	1			T132	11		T106	31		T126	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T1	3		T13	4		T33	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T2	1		T11	8		T131	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T15	12		T106	1		T125	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	338	1			T11	3		T131	16		T127	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T131	1		T125	1		T141	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T5	12		T6	1		T125	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T48	2		T30	1		T231	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T48	1		T16	22		T37	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T6	1		T33	2		T135	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T12	1		T44	23		T26	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T6	1		T9	7		T37	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T9	9		T10	11		T228	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T2	1		T5	9		T14	21
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1310	1			T41	3		T43	19		T105	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T30	1		T229	10		T227	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T14	6		T127	1		T130	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T132	12		T33	1		T128	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T15	4		T132	4		T182	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	337	1			T106	33		T182	1		T126	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T47	8		T268	1		T223	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T140	10		T149	6		T257	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18510	1			T1	156		T3	20		T7	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T44	8		T32	3		T33	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T2	7		T11	7		T239	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T15	12		T106	2		T125	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T11	2		T130	2		T229	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T125	12		T160	8		T238	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T5	14		T6	6		T125	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T30	11		T231	14		T232	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T16	10		T239	14		T240	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T6	6		T135	17		T129	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T12	13		T44	21		T26	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T6	11		T9	9		T37	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T9	10		T10	4		T228	24
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T2	10		T5	8		T14	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1346	1			T41	47		T105	21		T241	40
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T30	10		T229	2		T227	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T14	3		T130	8		T140	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T128	11		T147	14		T145	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T126	2		T37	1		T135	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	356	1			T106	27		T126	13		T236	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T47	4		T268	13		T223	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T140	3		T257	2		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T13	3		T242	10		T244	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T44	9		T32	1		T135	12

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T15	4		T135	10		T138	13
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T134	2		T140	10		T161	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T224	12		T225	1		T226	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T297	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T2	1		T11	8		T13	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T15	12		T44	8		T106	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	335	1			T11	3		T131	16		T130	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T131	1		T125	1		T142	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T6	1		T125	1		T30	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T48	1		T141	1		T232	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T5	12		T134	12		T16	22
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T48	1		T30	1		T33	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T44	23		T48	1		T26	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T6	2		T9	7		T37	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T9	9		T10	11		T12	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T2	1		T129	14		T206	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T286	1		T160	10		T145	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T5	9		T14	21		T30	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T14	6		T127	1		T130	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T33	1		T128	3		T227	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1324	1			T41	3		T43	19		T132	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	362	1			T132	12		T106	33		T182	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18444	1			T1	156		T3	20		T7	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T135	5		T235	11		T254	4
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T140	3		T250	9		T298	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T225	20		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T2	7		T11	7		T13	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T15	12		T44	9		T106	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T11	2		T130	2		T229	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T125	12		T236	1		T160	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T6	6		T125	17		T30	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T232	8		T244	11		T146	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T5	14		T134	10		T16	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T30	11		T135	17		T129	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T44	21		T26	4		T139	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T6	17		T9	9		T37	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T9	10		T10	4		T12	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T2	10		T129	2		T228	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T286	18		T160	2		T267	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T5	8		T14	18		T30	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T14	3		T130	8		T245	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T128	11		T227	4		T145	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1363	1			T41	47		T105	21		T126	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	365	1			T106	27		T126	13		T236	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23687

1

T1

156

T2

2

T3

20

auto[1]

auto[0]

4283

1

T2

17

T5

22

T6

23