Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27970

1

T1

156

T2

19

T3

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

24471

1

T1

156

T3

20

T5

43

auto[ADC_CTRL_FILTER_COND_OUT]

3499

1

T2

19

T6

12

T9

16

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21898

1

T1

156

T3

20

T5

17

auto[1]

6072

1

T2

19

T5

26

T9

19

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23680

1

T1

153

T2

19

T3

20

auto[1]

4290

1

T1

3

T5

19

T9

14

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	274	1			T235	21		T75	11		T18	5
values[0]	41	1			T204	2		T255	24		T180	11
values[1]	754	1			T14	3		T44	25		T48	1
values[2]	705	1			T6	7		T14	6		T44	17
values[3]	549	1			T15	4		T44	19		T106	3
values[4]	699	1			T6	7		T9	16		T12	14
values[5]	3283	1			T2	11		T11	15		T13	13
values[6]	719	1			T2	8		T5	26		T131	1
values[7]	671	1			T10	15		T11	5		T15	24
values[8]	807	1			T131	16		T132	4		T106	35
values[9]	1024	1			T5	17		T6	12		T9	19
minimum	18444	1			T1	156		T3	20		T7	14

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	726	1			T14	9		T44	42		T48	1
values[1]	758	1			T6	7		T15	4		T48	1
values[2]	634	1			T9	16		T12	14		T14	39
values[3]	2982	1			T6	7		T41	50		T43	19
values[4]	786	1			T2	11		T11	15		T13	13
values[5]	819	1			T2	8		T5	26		T10	15
values[6]	789	1			T11	5		T15	24		T132	26
values[7]	747	1			T131	16		T132	4		T125	13
values[8]	917	1			T5	17		T6	12		T9	19
values[9]	131	1			T37	2		T75	11		T18	5
minimum	18681	1			T1	156		T3	20		T7	14

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23687

1

T1

156

T2

2

T3

20

auto[1]

4283

1

T2

17

T5

22

T6

23

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T14	3		T44	23		T48	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T14	2		T126	3		T129	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T6	7		T15	1		T48	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T126	14		T229	9		T227	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T182	1		T33	2		T37	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T9	10		T12	14		T14	19
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1710	1			T6	7		T41	50		T43	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T38	2		T245	13		T240	21
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T11	8		T13	10		T30	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T2	11		T137	1		T138	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T5	15		T10	5		T131	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T2	8		T30	11		T135	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T11	3		T132	1		T134	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T15	13		T132	1		T106	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T39	1		T149	1		T253	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T131	1		T132	1		T125	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T5	9		T9	11		T125	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T6	12		T130	3		T143	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T37	1		T75	1		T18	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T52	10		T280	10		T21	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18365	1			T1	153		T3	20		T7	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T79	11		T275	13		T205	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T14	3		T44	19		T16	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T14	1		T129	13		T39	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T15	3		T134	11		T26	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T126	14		T229	5		T227	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T33	1		T37	2		T139	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T9	6		T14	20		T44	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	993	1			T43	17		T131	2		T183	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T38	2		T242	9		T279	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T11	7		T13	3		T237	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T137	13		T138	12		T47	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T5	11		T10	10		T181	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T135	14		T137	9		T138	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T11	2		T132	13		T134	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T15	11		T132	11		T106	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T39	1		T149	8		T253	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T131	15		T132	3		T16	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T5	8		T9	8		T34	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T130	9		T143	12		T231	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T37	1		T75	10		T298	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T52	14		T280	12		T21	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T1	3		T13	4		T33	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T79	2		T275	10		T294	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T235	12		T75	1		T18	5
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T249	12		T52	10		T299	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T204	1		T180	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T255	12		T294	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T44	13		T48	1		T16	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T14	2		T126	3		T129	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T6	7		T14	3		T44	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T39	1		T227	5		T234	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T15	1		T33	2		T37	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T44	10		T106	3		T126	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T6	7		T131	1		T182	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T9	10		T12	14		T14	19
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1777	1			T11	8		T13	10		T41	50
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T2	11		T228	11		T138	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T5	15		T131	1		T181	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T2	8		T30	11		T135	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T10	5		T11	3		T132	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T15	13		T132	1		T125	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T129	3		T39	1		T149	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T131	1		T132	1		T106	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T5	9		T9	11		T125	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T6	12		T130	3		T143	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18288	1			T1	153		T3	20		T7	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T235	9		T75	10		T300	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T249	8		T52	14		T301	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T204	1		T180	10		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T255	12		T294	3		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T44	12		T16	8		T159	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T14	1		T129	13		T17	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T14	3		T44	7		T134	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T39	4		T227	9		T234	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T15	3		T33	1		T37	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T44	9		T126	14		T33	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T131	2		T140	10		T164	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T9	6		T14	20		T106	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1026	1			T11	7		T13	3		T43	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T138	12		T242	9		T47	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T5	11		T181	2		T138	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T135	14		T137	13		T138	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T10	10		T11	2		T132	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T15	11		T132	11		T37	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T129	6		T39	1		T149	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T131	15		T132	3		T106	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T5	8		T9	8		T34	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T130	9		T143	12		T231	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T1	3		T13	4		T33	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T14	4		T44	21		T48	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T14	2		T126	1		T129	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T6	1		T15	4		T48	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T126	15		T229	6		T227	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T182	1		T33	3		T37	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T9	7		T12	1		T14	21
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1338	1			T6	1		T41	3		T43	19
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T38	4		T245	1		T240	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T11	8		T13	10		T30	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T2	1		T137	14		T138	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T5	12		T10	11		T131	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T2	1		T30	1		T135	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T11	3		T132	14		T134	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T15	12		T132	12		T106	19
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T39	2		T149	9		T253	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T131	16		T132	4		T125	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	322	1			T5	9		T9	9		T125	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T6	1		T130	10		T143	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T37	2		T75	11		T18	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T52	15		T280	13		T21	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18542	1			T1	156		T3	20		T7	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T79	3		T275	11		T205	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T14	2		T44	21		T16	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T14	1		T126	2		T129	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T6	6		T134	10		T26	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T126	13		T229	8		T227	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T37	1		T139	3		T243	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T9	9		T12	13		T14	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1365	1			T6	6		T41	47		T105	21
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T245	12		T240	20		T242	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T11	7		T13	3		T30	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T2	10		T245	5		T47	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T5	14		T10	4		T181	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T2	7		T30	10		T135	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T11	2		T129	2		T186	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T15	12		T106	16		T125	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T253	2		T249	9		T265	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T125	12		T16	6		T147	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T5	8		T9	10		T125	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T6	11		T130	2		T231	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T18	1		T298	8		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T52	9		T280	9		T21	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T140	3		T235	15		T244	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T79	10		T275	12		T302	5

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T235	10		T75	11		T18	4
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T249	9		T52	15		T299	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T204	2		T180	11		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T255	13		T294	4		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	292	1			T44	13		T48	1		T16	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T14	2		T126	1		T129	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T6	1		T14	4		T44	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T39	5		T227	10		T234	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T15	4		T33	3		T37	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T44	10		T106	1		T126	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T6	1		T131	3		T182	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T9	7		T12	1		T14	21
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1391	1			T11	8		T13	10		T41	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T2	1		T228	1		T138	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T5	12		T131	1		T181	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T2	1		T30	1		T135	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T10	11		T11	3		T132	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T15	12		T132	12		T125	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T129	7		T39	2		T149	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T131	16		T132	4		T106	19
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	338	1			T5	9		T9	9		T125	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T6	1		T130	10		T143	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18444	1			T1	156		T3	20		T7	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T235	11		T18	1		T300	6
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T249	11		T52	9		T299	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T255	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T44	12		T16	4		T140	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T14	1		T126	2		T129	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T6	6		T14	2		T44	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T227	4		T165	9		T154	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T37	1		T135	12		T139	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T44	9		T106	2		T126	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T6	6		T236	12		T140	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T9	9		T12	13		T14	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1412	1			T11	7		T13	3		T41	47
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T2	10		T228	10		T245	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T5	14		T181	7		T30	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T2	7		T30	10		T135	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T10	4		T11	2		T186	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T15	12		T125	17		T37	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T129	2		T150	11		T79	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T106	16		T125	12		T16	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T5	8		T9	10		T125	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T6	11		T130	2		T231	14

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23687

1

T1

156

T2

2

T3

20

auto[1]

auto[0]

4283

1

T2

17

T5

22

T6

23