Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27970

1

T1

156

T2

19

T3

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

24163

1

T1

156

T2

19

T3

20

auto[ADC_CTRL_FILTER_COND_OUT]

3807

1

T5

26

T6

12

T11

5

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21555

1

T1

156

T2

19

T3

20

auto[1]

6415

1

T5

26

T6

19

T9

19

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23680

1

T1

153

T2

19

T3

20

auto[1]

4290

1

T1

3

T5

19

T9

14

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	222	1			T9	19		T32	4		T127	1
values[0]	66	1			T197	9		T303	13		T304	1
values[1]	778	1			T48	1		T131	3		T181	10
values[2]	824	1			T2	19		T9	16		T11	20
values[3]	686	1			T6	7		T44	25		T48	1
values[4]	718	1			T5	26		T14	39		T132	12
values[5]	707	1			T6	12		T26	11		T30	12
values[6]	772	1			T5	17		T10	15		T182	1
values[7]	676	1			T6	7		T12	14		T13	13
values[8]	3116	1			T41	50		T43	19		T44	17
values[9]	961	1			T15	4		T44	19		T132	4
minimum	18444	1			T1	156		T3	20		T7	14

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	748	1			T48	1		T131	3		T33	2
values[1]	834	1			T2	19		T9	16		T11	20
values[2]	665	1			T6	7		T131	16		T132	12
values[3]	705	1			T5	26		T14	39		T182	1
values[4]	707	1			T6	12		T10	15		T182	1
values[5]	907	1			T5	17		T12	14		T106	35
values[6]	2913	1			T6	7		T13	13		T14	9
values[7]	718	1			T44	17		T131	1		T132	4
values[8]	919	1			T9	19		T15	4		T106	3
values[9]	135	1			T44	19		T243	20		T47	1
minimum	18719	1			T1	156		T3	20		T7	14

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23687

1

T1

156

T2

2

T3

20

auto[1]

4283

1

T2

17

T5

22

T6

23

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T135	18		T231	15		T139	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T48	1		T131	1		T33	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T2	19		T9	10		T11	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T11	3		T44	13		T138	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T6	7		T132	1		T125	20
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T131	1		T16	8		T30	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T30	12		T37	6		T127	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T5	15		T14	19		T182	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T10	5		T182	1		T26	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T6	12		T144	1		T286	19
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T5	9		T12	14		T106	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T34	11		T37	2		T128	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1703	1			T6	7		T13	10		T14	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T14	3		T33	2		T37	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T44	10		T131	1		T126	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T132	1		T106	12		T30	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T9	11		T15	1		T106	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T127	1		T130	12		T236	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T44	10		T243	9		T47	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T82	10		T291	16		T305	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18328	1			T1	153		T3	20		T7	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T181	8		T143	1		T263	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T135	14		T231	2		T139	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T131	2		T33	1		T238	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T9	6		T11	7		T15	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T11	2		T44	12		T138	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T132	11		T140	9		T235	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T131	15		T16	8		T250	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T37	1		T231	1		T235	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T5	11		T14	20		T135	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T10	10		T26	6		T159	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T144	13		T160	7		T149	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T5	8		T106	18		T126	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T34	11		T37	2		T128	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	958	1			T13	3		T14	1		T43	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T14	3		T33	1		T37	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T44	7		T134	11		T238	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T132	3		T106	13		T135	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T9	8		T15	3		T16	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T130	17		T137	13		T17	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T44	9		T243	11		T306	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T82	11		T100	6		T277	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T1	3		T13	4		T33	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T181	2		T143	12		T263	14

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T9	11		T32	4		T159	14
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T127	1		T130	9		T82	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T197	1		T304	1		T225	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T303	5		T307	1		T308	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T48	1		T135	18		T231	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T131	1		T181	8		T33	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T2	19		T9	10		T11	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T11	3		T48	1		T138	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T6	7		T48	1		T125	20
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T44	13		T131	1		T16	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T132	1		T37	6		T127	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T5	15		T14	19		T182	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T26	5		T30	12		T33	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T6	12		T286	19		T160	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T5	9		T10	5		T182	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T34	11		T37	2		T128	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T6	7		T12	14		T13	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T14	3		T33	2		T38	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1714	1			T41	50		T43	2		T44	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T30	11		T37	1		T135	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T15	1		T44	10		T106	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T132	1		T106	12		T130	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18288	1			T1	153		T3	20		T7	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T9	8		T159	10		T243	23
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T130	8		T82	11		T249	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T197	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T303	8		T307	4		T308	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T135	14		T231	2		T139	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T131	2		T181	2		T33	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T9	6		T11	7		T15	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T11	2		T138	12		T147	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T140	9		T39	4		T235	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T44	12		T131	15		T16	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T132	11		T37	1		T231	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T5	11		T14	20		T135	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T26	6		T129	13		T137	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T160	7		T149	8		T244	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T5	8		T10	10		T126	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T34	11		T37	2		T128	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T13	3		T14	1		T132	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T14	3		T33	1		T38	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1080	1			T43	17		T44	7		T183	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T37	1		T135	15		T138	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T15	3		T44	9		T16	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T132	3		T106	13		T130	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T1	3		T13	4		T33	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T135	15		T231	3		T139	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	302	1			T48	1		T131	3		T33	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T2	2		T9	7		T11	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T11	3		T44	13		T138	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T6	1		T132	12		T125	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T131	16		T16	10		T30	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T30	1		T37	6		T127	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T5	12		T14	21		T182	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T10	11		T182	1		T26	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T6	1		T144	14		T286	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	289	1			T5	9		T12	1		T106	19
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T34	12		T37	3		T128	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1305	1			T6	1		T13	10		T14	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T14	4		T33	3		T37	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T44	8		T131	1		T126	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T132	4		T106	14		T30	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T9	9		T15	4		T106	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T127	1		T130	19		T236	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T44	10		T243	12		T47	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T82	12		T291	1		T305	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18498	1			T1	156		T3	20		T7	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T181	3		T143	13		T263	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T135	17		T231	14		T139	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T238	11		T242	9		T246	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T2	17		T9	9		T11	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T11	2		T44	12		T229	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T6	6		T125	18		T140	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T16	6		T30	6		T228	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T30	11		T37	1		T235	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T5	14		T14	18		T135	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T10	4		T26	4		T129	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T6	11		T286	18		T160	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T5	8		T12	13		T106	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T34	10		T37	1		T128	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1356	1			T6	6		T13	3		T14	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T14	2		T245	12		T160	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T44	9		T126	2		T134	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T106	11		T30	10		T135	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T9	10		T106	2		T16	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T130	10		T236	12		T145	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T44	9		T243	8		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T82	9		T291	15		T266	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T254	4		T162	5		T225	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T181	7		T263	10		T253	2

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T9	9		T32	3		T159	11
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T127	1		T130	9		T82	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T197	9		T304	1		T225	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T303	9		T307	5		T308	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T48	1		T135	15		T231	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T131	3		T181	3		T33	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T2	2		T9	7		T11	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T11	3		T48	1		T138	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T6	1		T48	1		T125	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T44	13		T131	16		T16	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T132	12		T37	6		T127	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T5	12		T14	21		T182	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T26	7		T30	1		T33	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T6	1		T286	1		T160	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T5	9		T10	11		T182	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T34	12		T37	3		T128	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T6	1		T12	1		T13	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T14	4		T33	3		T38	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1430	1			T41	3		T43	19		T44	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T30	1		T37	2		T135	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T15	4		T44	10		T106	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	311	1			T132	4		T106	14		T130	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18444	1			T1	156		T3	20		T7	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T9	10		T32	1		T159	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T130	8		T82	9		T249	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T225	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T303	4		T308	7		T189	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T135	17		T231	14		T139	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T181	7		T263	10		T253	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T2	17		T9	9		T11	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T11	2		T147	14		T238	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T6	6		T125	18		T140	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T44	12		T16	6		T30	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T37	1		T139	13		T235	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T5	14		T14	18		T135	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T26	4		T30	11		T129	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T6	11		T286	18		T160	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T5	8		T10	4		T126	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T34	10		T37	1		T128	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T6	6		T12	13		T13	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T14	2		T245	17		T146	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1364	1			T41	47		T44	9		T105	21
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T30	10		T135	12		T160	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T44	9		T106	2		T16	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T106	11		T130	2		T236	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23687

1

T1

156

T2

2

T3

20

auto[1]

auto[0]

4283

1

T2

17

T5

22

T6

23