Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27970

1

T1

156

T2

19

T3

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

24297

1

T1

156

T3

20

T6

19

auto[ADC_CTRL_FILTER_COND_OUT]

3673

1

T2

19

T5

43

T6

7

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21513

1

T1

156

T2

8

T3

20

auto[1]

6457

1

T2

11

T5

43

T6

12

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23680

1

T1

153

T2

19

T3

20

auto[1]

4290

1

T1

3

T5

19

T9

14

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	198	1			T30	11		T143	13		T240	8
values[0]	58	1			T255	24		T256	29		T207	4
values[1]	750	1			T5	26		T6	12		T181	10
values[2]	782	1			T9	19		T131	1		T132	14
values[3]	580	1			T48	2		T132	4		T134	2
values[4]	871	1			T12	14		T48	1		T182	1
values[5]	3285	1			T5	17		T15	24		T41	50
values[6]	577	1			T6	7		T13	13		T14	3
values[7]	660	1			T2	19		T11	5		T14	6
values[8]	598	1			T10	15		T106	35		T126	3
values[9]	1167	1			T6	7		T9	16		T11	15
minimum	18444	1			T1	156		T3	20		T7	14

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	878	1			T6	12		T181	10		T134	22
values[1]	681	1			T9	19		T131	1		T132	14
values[2]	642	1			T48	3		T132	4		T126	28
values[3]	3335	1			T12	14		T41	50		T43	19
values[4]	798	1			T5	17		T15	24		T125	13
values[5]	670	1			T6	7		T13	13		T14	3
values[6]	511	1			T2	19		T10	15		T11	5
values[7]	650	1			T14	39		T106	35		T126	3
values[8]	1066	1			T6	7		T9	16		T15	4
values[9]	128	1			T11	15		T125	7		T182	1
minimum	18611	1			T1	156		T3	20		T5	26

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23687

1

T1

156

T2

2

T3

20

auto[1]

4283

1

T2

17

T5

22

T6

23

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T6	12		T134	11		T128	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T181	8		T33	1		T159	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T9	11		T131	1		T127	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T132	1		T37	8		T129	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T48	2		T132	1		T141	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T48	1		T126	14		T134	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1882	1			T12	14		T41	50		T43	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T125	18		T182	1		T32	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T125	13		T16	8		T236	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T5	9		T15	13		T135	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T44	10		T228	11		T144	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T6	7		T13	10		T14	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T10	5		T11	3		T14	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T2	19		T106	3		T39	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T106	17		T16	8		T37	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T14	19		T126	3		T135	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T6	7		T44	13		T33	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	357	1			T9	10		T15	1		T44	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T11	8		T125	7		T182	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T30	11		T143	1		T258	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18323	1			T1	153		T3	20		T7	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T5	15		T206	1		T160	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T134	11		T128	2		T243	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T181	2		T159	10		T137	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T9	8		T130	9		T38	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T132	13		T37	3		T129	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T132	3		T137	9		T140	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T126	14		T134	1		T235	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1116	1			T43	17		T131	2		T183	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T231	2		T229	14		T242	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T16	8		T231	1		T138	19
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T5	8		T15	11		T135	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T44	9		T144	9		T237	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T13	3		T14	1		T131	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T10	10		T11	2		T14	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T39	1		T160	9		T197	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T106	18		T16	8		T37	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T14	20		T135	9		T130	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T44	12		T33	1		T139	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T9	6		T15	3		T44	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T11	7		T265	14		T94	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T143	12		T258	9		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T1	3		T13	4		T33	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T5	11		T160	7		T255	12

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T240	8		T75	1		T151	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T30	11		T143	1		T309	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T256	15		T207	3		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T255	12		T310	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T6	12		T128	12		T148	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T5	15		T181	8		T33	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T9	11		T131	1		T134	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T132	1		T37	2		T159	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T48	1		T132	1		T141	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T48	1		T134	1		T37	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	289	1			T12	14		T48	1		T30	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T182	1		T126	14		T32	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1819	1			T41	50		T43	2		T131	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T5	9		T15	13		T125	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T228	11		T138	1		T144	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T6	7		T13	10		T14	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T11	3		T14	3		T44	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T2	19		T131	1		T106	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T10	5		T106	17		T16	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T126	3		T135	6		T130	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T6	7		T11	8		T44	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	383	1			T9	10		T14	19		T15	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18288	1			T1	153		T3	20		T7	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T265	14		T257	1		T87	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T143	12		T309	7		T24	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T256	14		T207	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T255	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T128	2		T243	1		T47	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T5	11		T181	2		T137	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T9	8		T134	11		T130	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	309	1			T132	13		T37	2		T159	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T132	3		T137	22		T140	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T134	1		T37	1		T164	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T232	7		T227	9		T238	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T126	14		T235	15		T192	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1036	1			T43	17		T131	2		T183	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T5	8		T15	11		T135	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T138	7		T144	9		T237	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T13	3		T14	1		T135	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T11	2		T14	3		T44	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T131	15		T160	9		T238	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T10	10		T106	18		T16	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T135	9		T130	8		T138	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T11	7		T44	12		T33	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	333	1			T9	6		T14	20		T15	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T1	3		T13	4		T33	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T6	1		T134	12		T128	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T181	3		T33	1		T159	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T9	9		T131	1		T127	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T132	14		T37	9		T129	20
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T48	2		T132	4		T141	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T48	1		T126	15		T134	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1494	1			T12	1		T41	3		T43	19
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T125	1		T182	1		T32	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T125	1		T16	12		T236	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T5	9		T15	12		T135	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T44	10		T228	1		T144	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T6	1		T13	10		T14	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T10	11		T11	3		T14	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T2	2		T106	1		T39	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T106	19		T16	10		T37	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T14	21		T126	1		T135	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T6	1		T44	13		T33	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	337	1			T9	7		T15	4		T44	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T11	8		T125	1		T182	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T30	1		T143	13		T258	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18482	1			T1	156		T3	20		T7	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T5	12		T206	1		T160	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T6	11		T134	10		T128	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T181	7		T159	13		T236	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T9	10		T130	2		T250	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T37	2		T129	15		T228	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T137	12		T140	3		T150	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T126	13		T235	15		T46	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1504	1			T12	13		T41	47		T105	21
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T125	17		T32	1		T231	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T125	12		T16	4		T236	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T5	8		T15	12		T135	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T44	9		T228	10		T244	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T6	6		T13	3		T14	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T10	4		T11	2		T14	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T2	17		T106	2		T245	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T106	16		T16	6		T244	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T14	18		T126	2		T135	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T6	6		T44	12		T139	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	300	1			T9	9		T44	9		T129	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T11	7		T125	6		T265	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T30	10		T258	1		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T82	4		T256	14		T188	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T5	14		T160	8		T255	11

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T240	1		T75	1		T151	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T30	1		T143	13		T309	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T256	15		T207	4		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T255	13		T310	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T6	1		T128	3		T148	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T5	12		T181	3		T33	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T9	9		T131	1		T134	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	354	1			T132	14		T37	3		T159	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T48	1		T132	4		T141	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T48	1		T134	2		T37	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	312	1			T12	1		T48	1		T30	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T182	1		T126	15		T32	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1396	1			T41	3		T43	19		T131	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T5	9		T15	12		T125	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T228	1		T138	8		T144	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T6	1		T13	10		T14	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T11	3		T14	4		T44	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T2	2		T131	16		T106	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T10	11		T106	19		T16	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T126	1		T135	10		T130	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T6	1		T11	8		T44	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	399	1			T9	7		T14	21		T15	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18444	1			T1	156		T3	20		T7	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T240	7		T265	12		T87	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T30	10		T309	7		T24	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T256	14		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T255	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T6	11		T128	11		T254	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T5	14		T181	7		T236	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T9	10		T134	10		T130	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T37	1		T159	13		T129	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T137	12		T140	3		T150	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T37	1		T228	5		T46	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T12	13		T30	11		T228	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T126	13		T32	1		T235	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1459	1			T41	47		T105	21		T125	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T5	8		T15	12		T125	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T228	10		T243	8		T244	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T6	6		T13	3		T14	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T11	2		T14	2		T44	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T2	17		T106	2		T30	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T10	4		T106	16		T16	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T126	2		T135	5		T130	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T6	6		T11	7		T44	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	317	1			T9	9		T14	18		T44	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23687

1

T1

156

T2

2

T3

20

auto[1]

auto[0]

4283

1

T2

17

T5

22

T6

23