Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27970

1

T1

156

T2

19

T3

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

24195

1

T1

156

T3

20

T6

7

auto[ADC_CTRL_FILTER_COND_OUT]

3775

1

T2

19

T5

43

T6

19

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21745

1

T1

156

T2

11

T3

20

auto[1]

6225

1

T2

8

T5

43

T6

19

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23680

1

T1

153

T2

19

T3

20

auto[1]

4290

1

T1

3

T5

19

T9

14

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	370	1			T126	28		T134	2		T34	22
values[0]	83	1			T106	25		T37	4		T229	14
values[1]	746	1			T9	16		T11	15		T14	45
values[2]	806	1			T10	15		T132	14		T16	16
values[3]	599	1			T131	16		T182	1		T126	3
values[4]	3135	1			T2	11		T6	7		T41	50
values[5]	501	1			T5	26		T6	19		T12	14
values[6]	851	1			T9	19		T14	3		T44	42
values[7]	580	1			T13	13		T15	24		T131	3
values[8]	734	1			T2	8		T11	5		T48	1
values[9]	1121	1			T5	17		T44	19		T132	16
minimum	18444	1			T1	156		T3	20		T7	14

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	858	1			T11	15		T14	39		T48	1
values[1]	654	1			T10	15		T132	14		T30	7
values[2]	612	1			T131	16		T182	1		T126	3
values[3]	3102	1			T2	11		T6	26		T41	50
values[4]	546	1			T5	26		T12	14		T15	4
values[5]	846	1			T9	19		T14	3		T44	17
values[6]	572	1			T13	13		T15	24		T48	1
values[7]	855	1			T2	8		T11	5		T44	19
values[8]	1076	1			T5	17		T132	12		T126	28
values[9]	155	1			T132	4		T134	2		T163	11
minimum	18694	1			T1	156		T3	20		T7	14

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23687

1

T1

156

T2

2

T3

20

auto[1]

4283

1

T2

17

T5

22

T6

23

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T11	8		T48	1		T16	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T14	19		T106	12		T37	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T236	16		T139	14		T229	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T10	5		T132	1		T30	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T134	11		T135	6		T130	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T131	1		T182	1		T126	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1672	1			T6	7		T41	50		T43	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T2	11		T6	19		T106	20
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T12	14		T130	9		T236	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T5	15		T15	1		T44	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T9	11		T14	2		T48	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T44	10		T125	13		T30	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T15	13		T48	1		T131	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T13	10		T135	18		T159	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T11	3		T44	10		T228	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T2	8		T125	18		T26	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T132	1		T33	1		T129	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T5	9		T126	14		T34	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T163	11		T146	12		T311	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T132	1		T134	1		T265	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18345	1			T1	153		T3	20		T7	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T9	10		T14	3		T127	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T11	7		T16	8		T37	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T14	20		T106	13		T37	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T139	1		T229	9		T149	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T10	10		T132	13		T147	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T134	11		T135	9		T130	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T131	15		T137	18		T238	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	955	1			T43	17		T183	13		T136	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T106	18		T159	10		T197	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T130	8		T39	4		T227	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T5	11		T15	3		T44	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T9	8		T14	1		T181	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T44	7		T33	1		T38	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T15	11		T131	2		T140	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T13	3		T135	14		T159	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T11	2		T44	9		T138	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T26	6		T144	9		T227	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T132	11		T33	1		T129	19
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	300	1			T5	8		T126	14		T34	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T257	1		T258	9		T312	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T132	3		T134	1		T265	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T1	3		T13	4		T33	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T9	6		T14	3		T250	8

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T129	16		T162	13		T146	12
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T126	14		T134	1		T34	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T37	2		T229	9		T263	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T106	12		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T11	8		T48	1		T30	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T9	10		T14	22		T37	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T16	8		T236	16		T232	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T10	5		T132	1		T30	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T134	11		T135	6		T130	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T131	1		T182	1		T126	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1694	1			T6	7		T41	50		T43	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T2	11		T106	20		T182	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T12	14		T130	9		T186	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T5	15		T6	19		T15	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T9	11		T14	2		T48	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T44	23		T125	13		T135	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T15	13		T131	1		T125	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T13	10		T30	12		T33	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T11	3		T48	1		T228	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T2	8		T125	18		T26	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T44	10		T132	1		T33	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	311	1			T5	9		T132	1		T141	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18288	1			T1	153		T3	20		T7	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T129	19		T162	10		T82	5
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T126	14		T134	1		T34	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T37	2		T229	5		T263	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T106	13		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T11	7		T37	1		T129	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T9	6		T14	23		T37	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T16	8		T232	7		T229	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T10	10		T132	13		T147	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T134	11		T135	9		T130	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T131	15		T137	18		T160	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	962	1			T43	17		T183	13		T136	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T106	18		T159	10		T164	28
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T130	8		T39	4		T227	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T5	11		T15	3		T235	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T9	8		T14	1		T16	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T44	19		T135	15		T38	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T15	11		T131	2		T181	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T13	3		T33	1		T135	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T11	2		T39	1		T243	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T26	6		T145	13		T150	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T44	9		T132	11		T33	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	360	1			T5	8		T132	3		T129	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T1	3		T13	4		T33	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T11	8		T48	1		T16	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T14	21		T106	14		T37	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T236	1		T139	2		T229	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T10	11		T132	14		T30	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T134	12		T135	10		T130	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T131	16		T182	1		T126	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1298	1			T6	1		T41	3		T43	19
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T2	1		T6	2		T106	20
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T12	1		T130	9		T236	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T5	12		T15	4		T44	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T9	9		T14	2		T48	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T44	8		T125	1		T30	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T15	12		T48	1		T131	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T13	10		T135	15		T159	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T11	3		T44	10		T228	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T2	1		T125	1		T26	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	295	1			T132	12		T33	2		T129	20
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	346	1			T5	9		T126	15		T34	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T163	1		T146	1		T311	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T132	4		T134	2		T265	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18538	1			T1	156		T3	20		T7	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T9	7		T14	4		T127	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T11	7		T16	4		T30	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T14	18		T106	11		T242	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T236	15		T139	13		T229	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T10	4		T30	6		T147	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T134	10		T135	5		T130	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T126	2		T32	1		T228	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1329	1			T6	6		T41	47		T105	21
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T2	10		T6	17		T106	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T12	13		T130	8		T236	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T5	14		T44	12		T135	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T9	10		T14	1		T181	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T44	9		T125	12		T30	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T15	12		T125	6		T140	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T13	3		T135	17		T236	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T11	2		T44	9		T228	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T2	7		T125	17		T26	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T129	15		T231	14		T240	20
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T5	8		T126	13		T34	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T163	10		T146	11		T257	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T265	12		T299	14		T309	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T37	1		T263	10		T313	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T9	9		T14	2		T250	9

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T129	20		T162	11		T146	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T126	15		T134	2		T34	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T37	3		T229	6		T263	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T106	14		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T11	8		T48	1		T30	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T9	7		T14	25		T37	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T16	12		T236	1		T232	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T10	11		T132	14		T30	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T134	12		T135	10		T130	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T131	16		T182	1		T126	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1310	1			T6	1		T41	3		T43	19
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T2	1		T106	20		T182	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T12	1		T130	9		T186	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T5	12		T6	2		T15	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T9	9		T14	2		T48	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T44	21		T125	1		T135	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T15	12		T131	3		T125	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T13	10		T30	1		T33	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T11	3		T48	1		T228	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T2	1		T125	1		T26	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T44	10		T132	12		T33	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	418	1			T5	9		T132	4		T141	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18444	1			T1	156		T3	20		T7	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T129	15		T162	12		T146	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T126	13		T34	10		T128	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T37	1		T229	8		T263	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T106	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T11	7		T30	10		T37	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T9	9		T14	20		T250	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T16	4		T236	15		T232	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T10	4		T30	6		T147	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T134	10		T135	5		T130	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T126	2		T137	9		T160	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1346	1			T6	6		T41	47		T105	21
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T2	10		T106	18		T32	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T12	13		T130	8		T186	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T5	14		T6	17		T235	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T9	10		T14	1		T16	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T44	21		T125	12		T135	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T15	12		T125	6		T181	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T13	3		T30	11		T135	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T11	2		T228	10		T243	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T2	7		T125	17		T26	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T44	9		T231	14		T240	20
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T5	8		T129	2		T137	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23687

1

T1

156

T2

2

T3

20

auto[1]

auto[0]

4283

1

T2

17

T5

22

T6

23