Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27970

1

T1

156

T2

19

T3

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

24271

1

T1

156

T2

19

T3

20

auto[ADC_CTRL_FILTER_COND_OUT]

3699

1

T5

26

T6

12

T11

5

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21590

1

T1

156

T2

19

T3

20

auto[1]

6380

1

T5

26

T6

19

T9

19

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23680

1

T1

153

T2

19

T3

20

auto[1]

4290

1

T1

3

T5

19

T9

14

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	57	1			T9	19		T314	1		T187	10
values[0]	106	1			T206	1		T234	7		T197	9
values[1]	716	1			T2	8		T48	1		T181	10
values[2]	831	1			T2	11		T9	16		T11	5
values[3]	685	1			T6	7		T11	15		T44	25
values[4]	610	1			T5	26		T131	16		T132	12
values[5]	806	1			T14	39		T26	11		T30	12
values[6]	822	1			T5	17		T6	12		T10	15
values[7]	618	1			T6	7		T12	14		T13	13
values[8]	3111	1			T41	50		T43	19		T44	17
values[9]	1164	1			T15	4		T44	19		T132	4
minimum	18444	1			T1	156		T3	20		T7	14

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1010	1			T48	2		T131	3		T181	10
values[1]	825	1			T2	19		T9	16		T11	20
values[2]	618	1			T6	7		T131	16		T125	20
values[3]	714	1			T5	26		T14	39		T132	12
values[4]	782	1			T5	17		T6	12		T10	15
values[5]	818	1			T12	14		T106	35		T126	28
values[6]	2965	1			T6	7		T13	13		T14	9
values[7]	693	1			T132	4		T106	25		T126	3
values[8]	918	1			T9	19		T15	4		T106	3
values[9]	141	1			T44	19		T243	20		T47	1
minimum	18486	1			T1	156		T3	20		T7	14

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23687

1

T1

156

T2

2

T3

20

auto[1]

4283

1

T2

17

T5

22

T6

23

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T48	1		T134	1		T135	18
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	332	1			T48	1		T131	1		T181	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T2	19		T9	10		T11	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T11	3		T44	13		T138	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T6	7		T125	20		T231	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T131	1		T16	8		T30	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T132	1		T30	12		T37	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T5	15		T14	19		T182	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T5	9		T10	5		T26	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T6	12		T182	1		T34	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T12	14		T126	14		T129	19
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T106	17		T37	2		T128	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1743	1			T6	7		T13	10		T14	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T14	3		T37	1		T245	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T134	11		T51	1		T238	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T132	1		T106	12		T126	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	296	1			T9	11		T15	1		T106	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T127	1		T130	9		T17	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T44	10		T243	9		T47	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T82	10		T291	16		T305	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18294	1			T1	153		T3	20		T7	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T303	5		T308	8		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T134	1		T135	14		T231	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T131	2		T181	2		T33	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T9	6		T11	7		T15	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T11	2		T44	12		T138	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T231	1		T140	9		T235	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T131	15		T16	8		T135	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T132	11		T37	1		T235	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T5	11		T14	20		T137	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T5	8		T10	10		T26	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T34	11		T144	13		T160	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T126	14		T129	25		T138	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T106	18		T37	2		T128	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	999	1			T13	3		T14	1		T43	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T14	3		T37	1		T160	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T134	11		T238	7		T244	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T132	3		T106	13		T33	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T9	8		T15	3		T16	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T130	8		T17	1		T145	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T44	9		T243	11		T306	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T82	11		T100	6		T277	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T1	3		T13	4		T33	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T303	8		T308	7		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T9	11		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T314	1		T187	1		T315	16
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T197	1		T294	1		T302	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T206	1		T234	1		T276	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T2	8		T48	1		T135	18
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T181	8		T33	1		T206	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T2	11		T9	10		T15	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T11	3		T48	1		T131	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T6	7		T11	8		T48	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T44	13		T16	8		T228	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T132	1		T37	6		T127	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T5	15		T131	1		T182	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T26	5		T30	12		T33	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T14	19		T160	9		T164	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T5	9		T10	5		T126	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T6	12		T106	17		T182	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T6	7		T12	14		T13	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T14	3		T33	2		T38	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1693	1			T41	50		T43	2		T44	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T126	3		T30	11		T37	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	324	1			T15	1		T44	10		T106	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	305	1			T132	1		T106	12		T127	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18288	1			T1	153		T3	20		T7	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T9	8		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T187	9		T315	11		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T197	8		T294	12		T302	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T234	6		T276	7		T303	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T135	14		T231	2		T139	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T181	2		T33	1		T143	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T9	6		T15	11		T134	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T11	2		T131	2		T138	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T11	7		T140	9		T39	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T44	12		T16	8		T144	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T132	11		T37	1		T231	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T5	11		T131	15		T135	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T26	6		T129	13		T137	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T14	20		T160	7		T164	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T5	8		T10	10		T126	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T106	18		T34	11		T37	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T13	3		T14	1		T132	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T14	3		T33	1		T38	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1084	1			T43	17		T44	7		T183	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T37	1		T135	15		T138	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T15	3		T44	9		T16	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T132	3		T106	13		T130	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T1	3		T13	4		T33	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T48	1		T134	2		T135	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	367	1			T48	1		T131	3		T181	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T2	2		T9	7		T11	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T11	3		T44	13		T138	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T6	1		T125	2		T231	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T131	16		T16	10		T30	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T132	12		T30	1		T37	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T5	12		T14	21		T182	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T5	9		T10	11		T26	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T6	1		T182	1		T34	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T12	1		T126	15		T129	27
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T106	19		T37	3		T128	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1355	1			T6	1		T13	10		T14	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T14	4		T37	2		T245	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T134	12		T51	1		T238	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T132	4		T106	14		T126	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T9	9		T15	4		T106	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T127	1		T130	9		T17	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T44	10		T243	12		T47	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T82	12		T291	1		T305	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18454	1			T1	156		T3	20		T7	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T303	9		T308	8		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T135	17		T231	14		T139	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T181	7		T245	5		T238	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T2	17		T9	9		T11	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T11	2		T44	12		T229	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T6	6		T125	18		T140	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T16	6		T30	6		T135	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T30	11		T37	1		T235	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T5	14		T14	18		T137	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T5	8		T10	4		T26	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T6	11		T34	10		T286	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T12	13		T126	13		T129	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T106	16		T37	1		T128	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1387	1			T6	6		T13	3		T14	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T14	2		T245	5		T160	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T134	10		T238	4		T244	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T106	11		T126	2		T30	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T9	10		T106	2		T16	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T130	8		T145	15		T82	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T44	9		T243	8		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T82	9		T291	15		T277	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T254	4		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T303	4		T308	7		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T9	9		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T314	1		T187	10		T315	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T197	9		T294	13		T302	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T206	1		T234	7		T276	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T2	1		T48	1		T135	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T181	3		T33	2		T206	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T2	1		T9	7		T15	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T11	3		T48	1		T131	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T6	1		T11	8		T48	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T44	13		T16	10		T228	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T132	12		T37	6		T127	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T5	12		T131	16		T182	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T26	7		T30	1		T33	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T14	21		T160	8		T164	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T5	9		T10	11		T126	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T6	1		T106	19		T182	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T6	1		T12	1		T13	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T14	4		T33	3		T38	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1432	1			T41	3		T43	19		T44	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T126	1		T30	1		T37	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	337	1			T15	4		T44	10		T106	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	343	1			T132	4		T106	14		T127	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18444	1			T1	156		T3	20		T7	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T9	10		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T315	15		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T302	5		T316	4		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T303	4		T317	9		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T2	7		T135	17		T231	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T181	7		T245	5		T263	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T2	10		T9	9		T15	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T11	2		T30	6		T147	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T6	6		T11	7		T125	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T44	12		T16	6		T228	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T37	1		T235	15		T163	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T5	14		T135	5		T137	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T26	4		T30	11		T129	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T14	18		T160	8		T244	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T5	8		T10	4		T126	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T6	11		T106	16		T34	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T6	6		T12	13		T13	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T14	2		T245	5		T233	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1345	1			T41	47		T44	9		T105	21
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T126	2		T30	10		T135	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T44	9		T106	2		T16	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T106	11		T130	8		T163	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23687

1

T1

156

T2

2

T3

20

auto[1]

auto[0]

4283

1

T2

17

T5

22

T6

23