Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_7

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T125	1		T30	1		T135	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	304	1			T5	9		T48	1		T182	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T132	12		T126	1		T30	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1358	1			T41	3		T43	19		T132	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T106	1		T33	3		T127	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T106	19		T125	1		T181	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T15	4		T141	1		T144	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T2	1		T6	1		T13	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T6	1		T11	3		T44	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T14	2		T182	1		T34	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T14	21		T15	12		T126	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	320	1			T44	10		T131	3		T106	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T2	1		T6	1		T134	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T10	11		T206	1		T144	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T9	7		T44	8		T33	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T9	9		T14	4		T48	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T131	1		T135	15		T160	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T11	8		T12	1		T132	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T48	1		T140	11		T162	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T5	12		T32	3		T145	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18444	1			T1	156		T3	20		T7	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T247	11		T248	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T125	6		T30	6		T135	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T5	8		T30	11		T129	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T126	2		T30	10		T135	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1325	1			T41	47		T105	21		T241	40
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T106	2		T236	1		T227	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T106	16		T125	12		T181	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T139	13		T229	2		T238	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T2	10		T6	6		T13	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T6	11		T11	2		T44	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T14	1		T34	10		T228	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T14	18		T15	12		T126	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T44	9		T106	11		T236	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T2	7		T6	6		T134	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T10	4		T240	20		T145	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T9	9		T44	9		T137	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T9	10		T14	2		T228	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T135	17		T160	8		T242	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T11	7		T12	13		T26	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T140	3		T162	12		T252	20
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T5	14		T32	1		T150	11

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	8	40	83.33	8

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T39	5		T150	14		T52	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T234	14		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T125	1		T126	1		T30	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T5	9		T48	1		T30	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T106	1		T30	1		T135	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T132	14		T182	1		T129	34
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T132	12		T33	3		T127	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T181	3		T33	2		T159	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T144	10		T139	12		T39	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T2	1		T6	1		T13	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T6	1		T15	4		T125	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T131	16		T182	1		T141	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T11	3		T15	12		T44	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	304	1			T14	2		T106	14		T34	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T2	1		T6	1		T14	21
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T10	11		T44	10		T131	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T44	8		T131	1		T137	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T9	9		T14	4		T48	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T9	7		T48	1		T33	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1559	1			T5	12		T11	8		T12	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18444	1			T1	156		T3	20		T7	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T150	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T125	6		T126	2		T30	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T5	8		T30	11		T139	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T106	2		T30	10		T135	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T129	17		T231	14		T253	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T236	1		T227	4		T254	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T181	7		T229	8		T235	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T139	13		T238	4		T163	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T2	10		T6	6		T13	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T6	11		T125	17		T128	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T228	5		T140	3		T186	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T11	2		T15	12		T44	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T14	1		T106	11		T34	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T2	7		T6	6		T14	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T10	4		T44	9		T227	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T44	9		T239	5		T150	21
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T9	10		T14	2		T137	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	346	1			T9	9		T135	17		T137	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1559	1			T5	14		T11	7		T12	13

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23687

1

T1

156

T2

2

T3

20

auto[1]

auto[0]

4283

1

T2

17

T5

22

T6

23