Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27970

1

T1

156

T2

19

T3

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

24325

1

T1

156

T3

20

T6

19

auto[ADC_CTRL_FILTER_COND_OUT]

3645

1

T2

19

T5

43

T6

7

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21499

1

T1

156

T2

8

T3

20

auto[1]

6471

1

T2

11

T5

43

T6

12

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23680

1

T1

153

T2

19

T3

20

auto[1]

4290

1

T1

3

T5

19

T9

14

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for max_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	63	1			T255	24		T256	29		T188	6
values[1]	773	1			T5	26		T6	12		T181	10
values[2]	716	1			T9	19		T131	1		T132	14
values[3]	642	1			T48	2		T132	4		T134	2
values[4]	908	1			T12	14		T48	1		T182	1
values[5]	3189	1			T5	17		T15	24		T41	50
values[6]	568	1			T6	7		T13	13		T14	3
values[7]	702	1			T2	19		T11	5		T14	6
values[8]	656	1			T10	15		T106	35		T126	3
values[9]	1309	1			T6	7		T9	16		T11	15
minimum	18444	1			T1	156		T3	20		T7	14

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1023	1			T6	12		T181	10		T134	22
values[1]	672	1			T9	19		T131	1		T132	14
values[2]	715	1			T48	3		T132	4		T126	28
values[3]	3288	1			T12	14		T41	50		T43	19
values[4]	753	1			T15	24		T125	13		T16	16
values[5]	659	1			T5	17		T6	7		T13	13
values[6]	580	1			T2	8		T10	15		T11	5
values[7]	631	1			T2	11		T14	39		T106	35
values[8]	989	1			T6	7		T9	16		T15	4
values[9]	188	1			T11	15		T44	25		T125	7
minimum	18472	1			T1	156		T3	20		T5	26

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23687

1

T1

156

T2

2

T3

20

auto[1]

4283

1

T2

17

T5

22

T6

23

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	318	1			T6	12		T134	11		T128	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T181	8		T159	14		T206	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T9	11		T131	1		T127	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T132	1		T33	1		T37	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T48	2		T132	1		T137	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T48	1		T126	14		T134	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1868	1			T12	14		T41	50		T43	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T125	18		T182	1		T32	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T125	13		T16	8		T236	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T15	13		T135	13		T129	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T44	10		T228	11		T144	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T5	9		T6	7		T13	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T10	5		T11	3		T14	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T2	8		T106	3		T39	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T106	17		T16	8		T37	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T2	11		T14	19		T126	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T6	7		T33	1		T139	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T9	10		T15	1		T44	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T11	8		T44	13		T125	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T30	11		T129	3		T143	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18289	1			T1	153		T3	20		T7	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T5	15		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T134	11		T128	2		T243	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T181	2		T159	10		T137	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T9	8		T130	9		T38	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T132	13		T37	3		T129	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T132	3		T137	9		T140	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T126	14		T134	1		T235	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1095	1			T43	17		T131	2		T183	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T231	2		T229	5		T242	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T16	8		T231	1		T138	19
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T15	11		T135	15		T129	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T44	9		T144	9		T237	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T5	8		T13	3		T14	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T10	10		T11	2		T14	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T39	1		T160	9		T197	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T106	18		T16	8		T37	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T14	20		T135	9		T130	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T33	1		T139	11		T235	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T9	6		T15	3		T44	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T11	7		T44	12		T257	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T129	6		T143	12		T258	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T1	3		T13	4		T33	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T5	11		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T256	15		T188	6		T207	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T255	12		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T6	12		T128	12		T254	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T5	15		T181	8		T33	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T9	11		T131	1		T134	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T132	1		T37	2		T159	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T48	1		T132	1		T141	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T48	1		T134	1		T37	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	298	1			T12	14		T48	1		T30	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T182	1		T126	14		T32	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1804	1			T41	50		T43	2		T131	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T5	9		T15	13		T125	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T228	11		T138	2		T144	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T6	7		T13	10		T14	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T11	3		T14	3		T44	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T2	19		T131	1		T106	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T10	5		T106	17		T16	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T126	3		T135	6		T130	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	300	1			T6	7		T11	8		T44	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	381	1			T9	10		T14	19		T15	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18288	1			T1	153		T3	20		T7	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T256	14		T207	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T255	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T128	2		T243	1		T47	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T5	11		T181	2		T137	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T9	8		T134	11		T130	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T132	13		T37	2		T159	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T132	3		T137	22		T140	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T134	1		T37	1		T164	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T232	7		T227	9		T238	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T126	14		T231	2		T229	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1000	1			T43	17		T131	2		T183	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T5	8		T15	11		T135	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T138	19		T144	9		T140	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T13	3		T14	1		T159	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T11	2		T14	3		T44	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T131	15		T135	14		T160	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T10	10		T106	18		T16	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T135	9		T130	8		T139	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	288	1			T11	7		T44	12		T33	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	340	1			T9	6		T14	20		T15	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T1	3		T13	4		T33	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T6	1		T134	12		T128	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T181	3		T159	11		T206	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T9	9		T131	1		T127	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	312	1			T132	14		T33	1		T37	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T48	2		T132	4		T137	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T48	1		T126	15		T134	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1469	1			T12	1		T41	3		T43	19
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T125	1		T182	1		T32	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T125	1		T16	12		T236	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T15	12		T135	16		T129	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T44	10		T228	1		T144	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T5	9		T6	1		T13	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T10	11		T11	3		T14	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T2	1		T106	1		T39	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T106	19		T16	10		T37	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T2	1		T14	21		T126	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T6	1		T33	2		T139	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	300	1			T9	7		T15	4		T44	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T11	8		T44	13		T125	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T30	1		T129	7		T143	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18446	1			T1	156		T3	20		T7	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T5	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T6	11		T134	10		T128	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T181	7		T159	13		T236	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T9	10		T130	2		T250	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T37	2		T129	15		T228	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T137	12		T140	3		T162	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T126	13		T235	15		T46	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1494	1			T12	13		T41	47		T105	21
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T125	17		T32	1		T231	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T125	12		T16	4		T236	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T15	12		T135	12		T129	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T44	9		T228	10		T244	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T5	8		T6	6		T13	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T10	4		T11	2		T14	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T2	7		T106	2		T245	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T106	16		T16	6		T186	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T2	10		T14	18		T126	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T6	6		T139	13		T235	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T9	9		T44	9		T229	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T11	7		T44	12		T125	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T30	10		T129	2		T236	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T5	14		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T256	15		T188	1		T207	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T255	13		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T6	1		T128	3		T254	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T5	12		T181	3		T33	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T9	9		T131	1		T134	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	325	1			T132	14		T37	3		T159	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T48	1		T132	4		T141	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T48	1		T134	2		T37	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	320	1			T12	1		T48	1		T30	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T182	1		T126	15		T32	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1355	1			T41	3		T43	19		T131	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T5	9		T15	12		T125	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T228	1		T138	21		T144	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T6	1		T13	10		T14	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T11	3		T14	4		T44	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T2	2		T131	16		T106	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T10	11		T106	19		T16	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T126	1		T135	10		T130	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	362	1			T6	1		T11	8		T44	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	409	1			T9	7		T14	21		T15	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18444	1			T1	156		T3	20		T7	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T256	14		T188	5		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T255	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T6	11		T128	11		T254	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T5	14		T181	7		T236	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T9	10		T134	10		T130	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T37	1		T159	13		T129	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T137	12		T140	3		T150	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T37	1		T228	5		T46	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T12	13		T30	11		T228	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T126	13		T32	1		T231	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1449	1			T41	47		T105	21		T125	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T5	8		T15	12		T125	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T228	10		T140	3		T243	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T6	6		T13	3		T14	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T11	2		T14	2		T44	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T2	17		T106	2		T30	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T10	4		T106	16		T16	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T126	2		T135	5		T130	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T6	6		T11	7		T44	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	312	1			T9	9		T14	18		T44	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23687

1

T1

156

T2

2

T3

20

auto[1]

auto[0]

4283

1

T2

17

T5

22

T6

23