Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27970

1

T1

156

T2

19

T3

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

24174

1

T1

156

T3

20

T6

7

auto[ADC_CTRL_FILTER_COND_OUT]

3796

1

T2

19

T5

43

T6

19

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21741

1

T1

156

T2

11

T3

20

auto[1]

6229

1

T2

8

T5

43

T6

19

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23680

1

T1

153

T2

19

T3

20

auto[1]

4290

1

T1

3

T5

19

T9

14

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	1	1			T259	1		-	-		-	-
values[0]	123	1			T106	25		T37	4		T229	14
values[1]	720	1			T9	16		T11	15		T14	45
values[2]	823	1			T132	14		T134	22		T16	16
values[3]	576	1			T10	15		T131	16		T182	2
values[4]	3135	1			T2	11		T6	19		T41	50
values[5]	535	1			T5	26		T6	7		T12	14
values[6]	860	1			T9	19		T14	3		T15	28
values[7]	555	1			T13	13		T48	1		T131	3
values[8]	709	1			T2	8		T11	5		T125	18
values[9]	1489	1			T5	17		T44	19		T132	16
minimum	18444	1			T1	156		T3	20		T7	14

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1106	1			T9	16		T11	15		T14	45
values[1]	558	1			T10	15		T132	14		T30	7
values[2]	689	1			T131	16		T182	2		T126	3
values[3]	3086	1			T2	11		T6	14		T41	50
values[4]	621	1			T5	26		T6	12		T12	14
values[5]	823	1			T9	19		T14	3		T48	1
values[6]	519	1			T2	8		T13	13		T15	24
values[7]	859	1			T11	5		T125	18		T26	11
values[8]	866	1			T5	17		T44	19		T132	12
values[9]	374	1			T132	4		T134	2		T163	11
minimum	18469	1			T1	156		T3	20		T7	14

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23687

1

T1

156

T2

2

T3

20

auto[1]

4283

1

T2

17

T5

22

T6

23

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T48	1		T16	8		T30	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	300	1			T9	10		T11	8		T14	22
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T236	16		T229	3		T161	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T10	5		T132	1		T30	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T134	11		T135	6		T130	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T131	1		T182	2		T126	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1684	1			T6	7		T41	50		T43	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T2	11		T6	7		T106	20
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T12	14		T130	9		T236	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T5	15		T6	12		T15	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T9	11		T14	2		T48	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T125	13		T30	12		T33	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T15	13		T48	1		T131	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T2	8		T13	10		T135	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T11	3		T228	11		T138	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T125	18		T26	5		T141	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T44	10		T132	1		T33	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T5	9		T126	14		T34	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T163	11		T146	12		T260	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T132	1		T134	1		T149	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18299	1			T1	153		T3	20		T7	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T16	8		T37	3		T129	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T9	6		T11	7		T14	23
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T229	9		T149	8		T49	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T10	10		T132	13		T147	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T134	11		T135	9		T130	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T131	15		T137	18		T238	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	953	1			T43	17		T183	13		T136	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T106	18		T159	10		T197	27
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T130	8		T39	4		T227	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T5	11		T15	3		T44	19
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T9	8		T14	1		T181	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T33	1		T144	13		T229	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T15	11		T131	2		T140	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T13	3		T135	14		T159	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T11	2		T138	5		T39	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T26	6		T144	9		T227	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T44	9		T132	11		T33	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T5	8		T126	14		T34	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T260	7		T261	9		T262	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T132	3		T134	1		T149	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T1	3		T13	4		T33	4

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T259	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T37	2		T229	9		T263	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T106	12		T250	10		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T48	1		T30	11		T37	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T9	10		T11	8		T14	22
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T134	11		T16	8		T236	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T132	1		T30	7		T137	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T135	6		T130	3		T143	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T10	5		T131	1		T182	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1689	1			T6	7		T41	50		T43	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	300	1			T2	11		T6	12		T106	20
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T12	14		T130	9		T186	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T5	15		T6	7		T229	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T9	11		T14	2		T15	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T15	1		T44	23		T125	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T48	1		T131	1		T125	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T13	10		T33	2		T135	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T11	3		T228	11		T236	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T2	8		T125	18		T26	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	370	1			T44	10		T132	1		T33	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	388	1			T5	9		T132	1		T126	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18288	1			T1	153		T3	20		T7	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T37	2		T229	5		T263	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T106	13		T250	8		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T37	1		T129	13		T264	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T9	6		T11	7		T14	23
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T134	11		T16	8		T232	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T132	13		T137	18		T147	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T135	9		T130	9		T143	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T10	10		T131	15		T160	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	966	1			T43	17		T183	13		T136	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T106	18		T159	10		T164	28
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T130	8		T39	4		T227	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T5	11		T229	10		T235	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T9	8		T14	1		T15	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T15	3		T44	19		T135	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T131	2		T181	2		T140	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T13	3		T33	1		T135	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T11	2		T39	1		T243	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T26	6		T160	9		T145	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	300	1			T44	9		T132	11		T33	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	431	1			T5	8		T132	3		T126	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T1	3		T13	4		T33	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	346	1			T48	1		T16	12		T30	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	308	1			T9	7		T11	8		T14	25
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T236	1		T229	10		T161	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T10	11		T132	14		T30	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T134	12		T135	10		T130	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T131	16		T182	2		T126	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1298	1			T6	1		T41	3		T43	19
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T2	1		T6	1		T106	20
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T12	1		T130	9		T236	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T5	12		T6	1		T15	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T9	9		T14	2		T48	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T125	1		T30	1		T33	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T15	12		T48	1		T131	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T2	1		T13	10		T135	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T11	3		T228	1		T138	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T125	1		T26	7		T141	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T44	10		T132	12		T33	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T5	9		T126	15		T34	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T163	1		T146	1		T260	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T132	4		T134	2		T149	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18459	1			T1	156		T3	20		T7	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T16	4		T30	10		T37	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T9	9		T11	7		T14	20
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T236	15		T229	2		T239	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T10	4		T30	6		T147	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T134	10		T135	5		T130	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T126	2		T32	1		T228	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1339	1			T6	6		T41	47		T105	21
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T2	10		T6	6		T106	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T12	13		T130	8		T236	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T5	14		T6	11		T44	21
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T9	10		T14	1		T181	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T125	12		T30	11		T228	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T15	12		T125	6		T236	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T2	7		T13	3		T135	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T11	2		T228	10		T243	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T125	17		T26	4		T227	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T44	9		T129	15		T231	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T5	8		T126	13		T34	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T163	10		T146	11		T260	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T244	11		T196	13		T265	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T263	10		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T259	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T37	3		T229	6		T263	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T106	14		T250	9		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T48	1		T30	1		T37	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T9	7		T11	8		T14	25
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T134	12		T16	12		T236	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T132	14		T30	1		T137	19
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T135	10		T130	10		T143	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T10	11		T131	16		T182	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1313	1			T6	1		T41	3		T43	19
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T2	1		T6	1		T106	20
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T12	1		T130	9		T186	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T5	12		T6	1		T229	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T9	9		T14	2		T15	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T15	4		T44	21		T125	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T48	1		T131	3		T125	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T13	10		T33	3		T135	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T11	3		T228	1		T236	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T2	1		T125	1		T26	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	376	1			T44	10		T132	12		T33	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	499	1			T5	9		T132	4		T126	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18444	1			T1	156		T3	20		T7	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T37	1		T229	8		T263	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T106	11		T250	9		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T30	10		T37	1		T129	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T9	9		T11	7		T14	20
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T134	10		T16	4		T236	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T30	6		T137	9		T147	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T135	5		T130	2		T139	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T10	4		T126	2		T160	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1342	1			T6	6		T41	47		T105	21
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T2	10		T6	11		T106	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T12	13		T130	8		T186	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T5	14		T6	6		T229	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T9	10		T14	1		T15	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T44	21		T125	12		T30	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T125	6		T181	7		T140	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T13	3		T135	17		T228	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T11	2		T228	10		T236	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T2	7		T125	17		T26	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	294	1			T44	9		T129	15		T231	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	320	1			T5	8		T126	13		T34	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23687

1

T1

156

T2

2

T3

20

auto[1]

auto[0]

4283

1

T2

17

T5

22

T6

23