Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27970

1

T1

156

T2

19

T3

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21598

1

T1

156

T2

8

T3

20

auto[ADC_CTRL_FILTER_COND_OUT]

6372

1

T2

11

T5

43

T6

7

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21753

1

T1

156

T3

20

T5

17

auto[1]

6217

1

T2

19

T5

26

T6

7

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23680

1

T1

153

T2

19

T3

20

auto[1]

4290

1

T1

3

T5

19

T9

14

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	452	1			T26	11		T135	32		T140	14
values[0]	1	1			T48	1		-	-		-	-
values[1]	554	1			T5	17		T125	7		T30	7
values[2]	772	1			T132	14		T182	1		T126	3
values[3]	657	1			T132	12		T106	3		T181	10
values[4]	604	1			T2	11		T6	7		T13	13
values[5]	787	1			T6	12		T15	4		T131	16
values[6]	750	1			T11	5		T14	3		T15	24
values[7]	822	1			T2	8		T6	7		T10	15
values[8]	775	1			T9	19		T14	6		T44	17
values[9]	3352	1			T5	26		T9	16		T11	15
minimum	18444	1			T1	156		T3	20		T7	14

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	623	1			T132	14		T125	7		T182	1
values[1]	3003	1			T41	50		T43	19		T132	12
values[2]	661	1			T106	38		T125	13		T181	10
values[3]	703	1			T2	11		T6	7		T13	13
values[4]	729	1			T6	12		T14	3		T125	18
values[5]	856	1			T11	5		T14	39		T15	24
values[6]	789	1			T2	8		T6	7		T10	15
values[7]	710	1			T9	35		T14	6		T44	17
values[8]	996	1			T11	15		T12	14		T131	1
values[9]	260	1			T5	26		T48	1		T140	14
minimum	18640	1			T1	156		T3	20		T5	17

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23687

1

T1

156

T2

2

T3

20

auto[1]

4283

1

T2

17

T5

22

T6

23

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T125	7		T135	6		T129	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T132	1		T182	1		T129	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T132	1		T126	3		T30	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1683	1			T41	50		T43	2		T105	23
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T106	3		T33	2		T127	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T106	17		T125	13		T181	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T15	1		T141	1		T144	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T2	11		T6	7		T13	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T6	12		T125	18		T16	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T14	2		T182	1		T34	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T11	3		T14	19		T15	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T44	10		T106	12		T236	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T2	8		T6	7		T134	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T10	5		T131	1		T37	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T9	10		T44	10		T33	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T9	11		T14	3		T48	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	285	1			T131	1		T135	18		T160	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T11	8		T12	14		T132	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T48	1		T140	4		T162	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T5	15		T39	1		T145	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18343	1			T1	153		T3	20		T7	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T5	9		T17	2		T234	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T135	9		T129	6		T249	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T132	13		T129	13		T139	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T132	11		T231	1		T232	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	998	1			T43	17		T183	13		T135	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T33	1		T227	2		T164	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T106	18		T181	2		T33	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T15	3		T144	9		T229	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T13	3		T131	15		T37	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T16	8		T128	2		T130	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T14	1		T34	11		T38	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T11	2		T14	20		T15	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T44	9		T106	13		T138	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T134	11		T16	8		T37	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T10	10		T131	2		T37	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T9	6		T44	7		T137	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T9	8		T14	3		T134	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T135	14		T160	7		T204	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T11	7		T132	3		T26	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T140	10		T162	10		T251	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T5	11		T39	4		T145	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T1	3		T13	4		T33	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T5	8		T17	1		T234	13

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T135	18		T140	4		T162	13
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T26	5		T39	1		T148	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T48	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T125	7		T30	7		T135	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T5	9		T139	14		T229	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T126	3		T30	11		T206	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T132	1		T182	1		T30	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T132	1		T106	3		T33	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T181	8		T33	1		T159	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T141	1		T144	1		T39	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T2	11		T6	7		T13	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T6	12		T15	1		T125	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T131	1		T182	1		T37	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T11	3		T15	13		T44	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T14	2		T106	12		T34	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T2	8		T6	7		T14	19
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T10	5		T44	10		T131	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T44	10		T137	1		T138	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T9	11		T14	3		T48	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T9	10		T48	1		T131	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1869	1			T5	15		T11	8		T12	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18288	1			T1	153		T3	20		T7	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T135	14		T140	10		T162	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T26	6		T39	4		T149	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T135	9		T129	6		T199	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T5	8		T139	1		T229	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T232	7		T139	11		T235	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T132	13		T135	15		T129	32
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T132	11		T33	1		T231	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T181	2		T33	1		T159	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T144	9		T39	1		T238	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T13	3		T106	18		T38	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T15	3		T128	2		T130	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T131	15		T37	2		T38	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T11	2		T15	11		T44	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T14	1		T106	13		T34	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T14	20		T126	14		T134	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T10	10		T44	9		T131	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T44	7		T137	13		T138	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T9	8		T14	3		T134	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T9	6		T137	9		T160	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1143	1			T5	11		T11	7		T43	17
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T1	3		T13	4		T33	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T125	1		T135	10		T129	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T132	14		T182	1		T129	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T132	12		T126	1		T30	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1343	1			T41	3		T43	19		T105	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T106	1		T33	3		T127	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T106	19		T125	1		T181	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T15	4		T141	1		T144	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T2	1		T6	1		T13	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T6	1		T125	1		T16	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T14	2		T182	1		T34	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T11	3		T14	21		T15	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	340	1			T44	10		T106	14		T236	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T2	1		T6	1		T134	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T10	11		T131	3		T37	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T9	7		T44	8		T33	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T9	9		T14	4		T48	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T131	1		T135	15		T160	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	318	1			T11	8		T12	1		T132	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T48	1		T140	11		T162	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T5	12		T39	5		T145	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18485	1			T1	156		T3	20		T7	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T5	9		T17	3		T234	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T125	6		T135	5		T129	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T129	2		T139	13		T229	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T126	2		T30	10		T232	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1338	1			T41	47		T105	21		T241	40
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T106	2		T236	1		T227	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T106	16		T125	12		T181	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T229	2		T238	4		T243	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T2	10		T6	6		T13	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T6	11		T125	17		T16	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T14	1		T34	10		T228	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T11	2		T14	18		T15	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T44	9		T106	11		T236	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T2	7		T6	6		T134	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T10	4		T240	20		T145	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T9	9		T44	9		T137	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T9	10		T14	2		T228	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T135	17		T160	8		T252	30
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T11	7		T12	13		T26	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T140	3		T162	12		T266	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T5	14		T267	11		T268	17
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T30	6		T269	13		T225	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T5	8		T270	11		T256	14

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T135	15		T140	11		T162	11
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T26	7		T39	5		T148	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T48	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T125	1		T30	1		T135	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T5	9		T139	2		T229	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T126	1		T30	1		T206	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T132	14		T182	1		T30	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T132	12		T106	1		T33	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T181	3		T33	2		T159	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T141	1		T144	10		T39	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T2	1		T6	1		T13	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T6	1		T15	4		T125	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T131	16		T182	1		T37	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T11	3		T15	12		T44	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T14	2		T106	14		T34	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T2	1		T6	1		T14	21
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T10	11		T44	10		T131	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T44	8		T137	14		T138	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T9	9		T14	4		T48	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T9	7		T48	1		T131	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1505	1			T5	12		T11	8		T12	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18444	1			T1	156		T3	20		T7	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T135	17		T140	3		T162	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T26	4		T267	11		T268	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T125	6		T30	6		T135	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T5	8		T139	13		T229	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T126	2		T30	10		T232	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T30	11		T135	12		T129	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T106	2		T236	1		T227	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T181	7		T229	8		T235	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T238	4		T163	8		T165	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T2	10		T6	6		T13	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T6	11		T125	17		T128	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T37	1		T228	5		T186	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T11	2		T15	12		T44	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T14	1		T106	11		T34	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T2	7		T6	6		T14	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T10	4		T44	9		T227	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T44	9		T239	5		T146	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T9	10		T14	2		T137	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T9	9		T137	12		T160	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1507	1			T5	14		T11	7		T12	13

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23687

1

T1

156

T2

2

T3

20

auto[1]

auto[0]

4283

1

T2

17

T5

22

T6

23