Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27970

1

T1

156

T2

19

T3

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

24176

1

T1

156

T3

20

T5

26

auto[ADC_CTRL_FILTER_COND_OUT]

3794

1

T2

19

T5

17

T6

19

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21124

1

T1

155

T2

19

T3

20

auto[1]

6846

1

T1

1

T6

14

T9

19

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23680

1

T1

153

T2

19

T3

20

auto[1]

4290

1

T1

3

T5

19

T9

14

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	479	1			T1	1		T36	3		T13	2
values[0]	64	1			T48	1		T138	6		T149	6
values[1]	636	1			T12	14		T15	4		T106	35
values[2]	3025	1			T2	8		T41	50		T43	19
values[3]	705	1			T6	7		T9	16		T44	19
values[4]	633	1			T131	1		T135	28		T127	1
values[5]	862	1			T6	12		T9	19		T106	25
values[6]	701	1			T5	26		T6	7		T13	13
values[7]	866	1			T2	11		T132	12		T181	10
values[8]	730	1			T44	25		T125	7		T126	3
values[9]	1302	1			T5	17		T10	15		T11	20
minimum	17967	1			T1	155		T3	20		T7	14

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	786	1			T12	14		T15	4		T106	35
values[1]	3126	1			T2	8		T6	7		T41	50
values[2]	587	1			T9	16		T44	19		T48	1
values[3]	783	1			T6	12		T131	1		T134	2
values[4]	775	1			T9	19		T106	25		T182	2
values[5]	838	1			T5	26		T6	7		T13	13
values[6]	726	1			T2	11		T44	25		T181	10
values[7]	772	1			T125	7		T33	3		T128	14
values[8]	917	1			T5	17		T10	15		T11	15
values[9]	189	1			T11	5		T14	6		T15	24
minimum	18471	1			T1	156		T3	20		T7	14

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23687

1

T1

156

T2

2

T3

20

auto[1]

4283

1

T2

17

T5

22

T6

23

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T15	1		T106	17		T141	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T12	14		T125	18		T16	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1768	1			T41	50		T43	2		T105	23
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T2	8		T6	7		T125	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T9	10		T44	10		T48	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T135	19		T228	6		T147	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T37	6		T206	1		T38	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T6	12		T131	1		T134	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T9	11		T182	1		T236	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T106	12		T182	1		T16	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T5	15		T6	7		T30	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T13	10		T44	10		T48	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T181	8		T134	11		T143	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T2	11		T44	13		T126	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T125	7		T33	2		T128	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T138	1		T245	13		T243	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T11	8		T14	2		T131	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	330	1			T5	9		T10	5		T14	19
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T14	3		T15	13		T132	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T11	3		T146	13		T79	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18294	1			T1	153		T3	20		T7	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T48	1		T271	15		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T15	3		T106	18		T231	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T16	8		T33	1		T138	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1008	1			T43	17		T183	13		T136	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T26	6		T39	4		T49	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T9	6		T44	9		T37	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T135	24		T147	15		T160	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T37	1		T38	2		T137	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T134	1		T159	4		T129	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T9	8		T237	4		T227	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T106	13		T16	8		T34	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T5	11		T231	2		T140	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T13	3		T44	7		T132	24
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T181	2		T134	11		T143	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T44	12		T129	19		T232	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T33	1		T128	2		T129	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T138	12		T243	1		T244	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T11	7		T14	1		T131	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T5	8		T10	10		T14	20
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T14	3		T15	11		T132	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T11	2		T79	2		T272	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T1	3		T13	4		T33	4

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	478	1			T1	1		T36	3		T13	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T149	1		T251	1		T273	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T48	1		T138	1		T274	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T15	1		T106	17		T141	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T12	14		T125	18		T16	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1756	1			T41	50		T43	2		T105	23
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T2	8		T125	13		T236	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T9	10		T44	10		T48	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T6	7		T135	6		T147	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T141	1		T206	1		T140	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T131	1		T135	13		T127	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T9	11		T236	16		T38	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T6	12		T106	12		T182	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T5	15		T6	7		T182	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T13	10		T44	10		T48	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T181	8		T134	11		T143	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T2	11		T132	1		T148	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T125	7		T128	12		T129	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T44	13		T126	3		T32	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	308	1			T11	8		T14	5		T15	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	419	1			T5	9		T10	5		T11	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17811	1			T1	152		T3	20		T7	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T257	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T149	5		T251	7		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T138	5		T230	3		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T15	3		T106	18		T231	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T16	8		T26	6		T33	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1002	1			T43	17		T183	13		T136	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T39	4		T275	15		T255	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T9	6		T44	9		T37	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T135	9		T147	15		T160	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T140	9		T229	10		T276	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T135	15		T129	13		T38	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T9	8		T38	2		T137	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T106	13		T134	1		T16	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T5	11		T231	2		T227	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T13	3		T44	7		T132	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T181	2		T134	11		T143	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T132	11		T164	22		T242	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T128	2		T129	6		T144	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T44	12		T129	19		T160	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T11	7		T14	4		T15	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	367	1			T5	8		T10	10		T11	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T1	3		T13	4		T33	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T15	4		T106	19		T141	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T12	1		T125	1		T16	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1363	1			T41	3		T43	19		T105	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T2	1		T6	1		T125	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T9	7		T44	10		T48	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T135	26		T228	1		T147	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T37	6		T206	1		T38	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T6	1		T131	1		T134	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T9	9		T182	1		T236	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T106	14		T182	1		T16	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T5	12		T6	1		T30	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T13	10		T44	8		T48	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T181	3		T134	12		T143	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T2	1		T44	13		T126	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T125	1		T33	3		T128	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T138	13		T245	1		T243	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T11	8		T14	2		T131	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	349	1			T5	9		T10	11		T14	21
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T14	4		T15	12		T132	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T11	3		T146	1		T79	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18450	1			T1	156		T3	20		T7	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T48	1		T271	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T106	16		T245	5		T160	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T12	13		T125	17		T16	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1413	1			T41	47		T105	21		T241	40
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T2	7		T6	6		T125	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T9	9		T44	9		T137	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T135	17		T228	5		T147	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T37	1		T137	9		T140	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T6	11		T129	2		T38	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T9	10		T236	15		T227	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T106	11		T16	4		T34	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T5	14		T6	6		T30	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T13	3		T44	9		T130	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T181	7		T134	10		T227	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T2	10		T44	12		T126	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T125	6		T128	11		T129	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T245	12		T240	24		T244	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T11	7		T14	1		T106	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T5	8		T10	4		T14	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T14	2		T15	12		T262	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T11	2		T146	12		T79	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T189	5		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T271	14		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	479	1			T1	1		T36	3		T13	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T149	6		T251	8		T273	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T48	1		T138	6		T274	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T15	4		T106	19		T141	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T12	1		T125	1		T16	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1355	1			T41	3		T43	19		T105	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T2	1		T125	1		T236	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T9	7		T44	10		T48	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T6	1		T135	10		T147	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T141	1		T206	1		T140	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T131	1		T135	16		T127	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T9	9		T236	1		T38	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T6	1		T106	14		T182	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T5	12		T6	1		T182	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T13	10		T44	8		T48	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T181	3		T134	12		T143	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T2	1		T132	12		T148	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T125	1		T128	3		T129	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T44	13		T126	1		T32	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T11	8		T14	6		T15	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	441	1			T5	9		T10	11		T11	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17967	1			T1	155		T3	20		T7	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T273	14		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T230	4		T271	14		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T106	16		T245	5		T160	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T12	13		T125	17		T16	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1403	1			T41	47		T105	21		T241	40
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T2	7		T125	12		T236	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T9	9		T44	9		T37	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T6	6		T135	5		T147	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T140	3		T229	12		T163	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T135	12		T129	2		T228	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T9	10		T236	15		T137	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T6	11		T106	11		T16	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T5	14		T6	6		T30	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T13	3		T44	9		T130	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T181	7		T134	10		T140	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T2	10		T242	10		T191	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T125	6		T128	11		T129	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T44	12		T126	2		T32	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T11	7		T14	3		T15	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	345	1			T5	8		T10	4		T11	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23687

1

T1

156

T2

2

T3

20

auto[1]

auto[0]

4283

1

T2

17

T5

22

T6

23