Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27970

1

T1

156

T2

19

T3

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

24397

1

T1

156

T2

19

T3

20

auto[ADC_CTRL_FILTER_COND_OUT]

3573

1

T5

17

T6

12

T9

16

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21874

1

T1

156

T2

11

T3

20

auto[1]

6096

1

T2

8

T5

43

T9

19

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23680

1

T1

153

T2

19

T3

20

auto[1]

4290

1

T1

3

T5

19

T9

14

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	48	1			T277	22		T278	26		-	-
values[0]	104	1			T204	2		T275	23		T279	15
values[1]	693	1			T14	3		T48	1		T126	3
values[2]	607	1			T6	7		T14	6		T15	4
values[3]	677	1			T9	16		T44	19		T126	28
values[4]	706	1			T6	7		T12	14		T14	39
values[5]	3232	1			T2	11		T11	15		T13	13
values[6]	701	1			T2	8		T5	26		T131	1
values[7]	683	1			T10	15		T11	5		T15	24
values[8]	826	1			T131	16		T132	4		T106	35
values[9]	1249	1			T5	17		T6	12		T9	19
minimum	18444	1			T1	156		T3	20		T7	14

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	917	1			T6	7		T14	9		T44	25
values[1]	765	1			T15	4		T44	17		T48	1
values[2]	646	1			T9	16		T12	14		T14	39
values[3]	3011	1			T6	7		T41	50		T43	19
values[4]	808	1			T2	11		T11	15		T13	13
values[5]	781	1			T2	8		T5	26		T10	15
values[6]	733	1			T11	5		T15	24		T131	16
values[7]	811	1			T125	13		T182	1		T16	16
values[8]	890	1			T5	17		T9	19		T132	4
values[9]	148	1			T6	12		T37	2		T75	11
minimum	18460	1			T1	156		T3	20		T7	14

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23687

1

T1

156

T2

2

T3

20

auto[1]

4283

1

T2

17

T5

22

T6

23

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T6	7		T14	3		T44	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T14	2		T126	3		T16	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T15	1		T44	10		T48	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T126	14		T134	11		T229	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T106	3		T182	1		T33	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T9	10		T12	14		T14	19
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1723	1			T6	7		T41	50		T43	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T131	1		T38	2		T245	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T2	11		T11	8		T13	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T228	11		T137	1		T138	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T2	8		T5	15		T10	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T135	18		T228	15		T137	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T11	3		T132	1		T125	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T15	13		T131	1		T132	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T39	1		T254	5		T149	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T125	13		T182	1		T16	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T9	11		T125	7		T30	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T5	9		T132	1		T34	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T37	1		T75	1		T18	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T6	12		T52	10		T280	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18289	1			T1	153		T3	20		T7	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T190	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T14	3		T44	12		T159	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T14	1		T16	8		T129	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T15	3		T44	7		T26	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T126	14		T134	11		T229	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T33	1		T139	11		T243	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T9	6		T14	20		T44	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	995	1			T43	17		T183	13		T136	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T131	2		T38	2		T242	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T11	7		T13	3		T237	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T137	13		T138	12		T47	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T5	11		T10	10		T181	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T135	14		T137	9		T138	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T11	2		T132	13		T134	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T15	11		T131	15		T132	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T39	1		T149	8		T253	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T16	8		T129	6		T147	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T9	8		T135	9		T128	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T5	8		T132	3		T34	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T37	1		T75	10		T152	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T52	14		T280	12		T88	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T1	3		T13	4		T33	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T190	2		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T277	12		T278	13		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T204	1		T255	12		T23	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T275	13		T279	1		T190	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T48	1		T141	1		T159	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T14	2		T126	3		T16	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T6	7		T14	3		T15	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T227	5		T234	1		T246	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T33	2		T37	2		T135	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T9	10		T44	10		T126	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T6	7		T106	3		T182	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T12	14		T14	19		T131	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1816	1			T2	11		T11	8		T13	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T138	1		T245	6		T240	21
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T2	8		T5	15		T131	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T135	18		T228	11		T137	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T10	5		T11	3		T132	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T15	13		T132	1		T37	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T39	1		T148	1		T149	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T131	1		T132	1		T106	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T9	11		T125	7		T30	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	388	1			T5	9		T6	12		T34	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18288	1			T1	153		T3	20		T7	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T277	10		T278	13		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T204	1		T255	12		T23	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T275	10		T279	14		T190	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T159	4		T144	13		T140	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T14	1		T16	8		T129	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T14	3		T15	3		T44	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T227	9		T234	6		T154	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T33	1		T37	2		T135	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T9	6		T44	9		T126	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T140	10		T164	14		T242	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T14	20		T131	2		T106	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1089	1			T11	7		T13	3		T43	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T138	12		T242	9		T47	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T5	11		T181	2		T229	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T135	14		T137	13		T138	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T10	10		T11	2		T132	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T15	11		T132	11		T37	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T39	1		T149	8		T150	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T131	15		T132	3		T106	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T9	8		T37	1		T135	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	330	1			T5	8		T34	11		T231	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T1	3		T13	4		T33	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	303	1			T6	1		T14	4		T44	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T14	2		T126	1		T16	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T15	4		T44	8		T48	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T126	15		T134	12		T229	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T106	1		T182	1		T33	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T9	7		T12	1		T14	21
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1343	1			T6	1		T41	3		T43	19
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T131	3		T38	4		T245	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T2	1		T11	8		T13	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T228	1		T137	14		T138	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T2	1		T5	12		T10	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T135	15		T228	1		T137	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T11	3		T132	14		T125	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T15	12		T131	16		T132	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T39	2		T254	1		T149	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T125	1		T182	1		T16	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T9	9		T125	1		T30	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T5	9		T132	4		T34	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T37	2		T75	11		T18	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T6	1		T52	15		T280	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18445	1			T1	156		T3	20		T7	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T190	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T6	6		T14	2		T44	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T14	1		T126	2		T16	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T44	9		T26	4		T37	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T126	13		T134	10		T229	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T106	2		T139	3		T243	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T9	9		T12	13		T14	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1375	1			T6	6		T41	47		T105	21
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T245	12		T240	20		T242	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T2	10		T11	7		T13	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T228	10		T245	5		T47	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T2	7		T5	14		T10	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T135	17		T228	14		T137	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T11	2		T125	17		T186	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T15	12		T106	16		T37	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T254	4		T253	2		T249	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T125	12		T16	6		T129	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T9	10		T125	6		T30	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T5	8		T34	10		T130	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T18	1		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T6	11		T52	9		T280	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T190	11		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T277	11		T278	14		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T204	2		T255	13		T23	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T275	11		T279	15		T190	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T48	1		T141	1		T159	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T14	2		T126	1		T16	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T6	1		T14	4		T15	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T227	10		T234	7		T246	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T33	3		T37	3		T135	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T9	7		T44	10		T126	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T6	1		T106	1		T182	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T12	1		T14	21		T131	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1460	1			T2	1		T11	8		T13	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T138	13		T245	1		T240	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T2	1		T5	12		T131	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T135	15		T228	1		T137	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T10	11		T11	3		T132	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T15	12		T132	12		T37	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T39	2		T148	1		T149	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T131	16		T132	4		T106	19
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	330	1			T9	9		T125	1		T30	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	393	1			T5	9		T6	1		T34	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18444	1			T1	156		T3	20		T7	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T277	11		T278	12		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T255	11		T23	1		T281	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T275	12		T190	11		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T140	3		T235	15		T250	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T14	1		T126	2		T16	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T6	6		T14	2		T44	21
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T227	4		T246	15		T154	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T37	1		T135	12		T139	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T9	9		T44	9		T126	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T6	6		T106	2		T236	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T12	13		T14	18		T106	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1445	1			T2	10		T11	7		T13	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T245	5		T240	20		T242	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T2	7		T5	14		T181	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T135	17		T228	10		T139	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T10	4		T11	2		T125	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T15	12		T37	1		T159	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T150	11		T79	9		T249	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T106	16		T125	12		T16	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T9	10		T125	6		T30	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	325	1			T5	8		T6	11		T34	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23687

1

T1

156

T2

2

T3

20

auto[1]

auto[0]

4283

1

T2

17

T5

22

T6

23