Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27970

1

T1

156

T2

19

T3

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

24290

1

T1

156

T2

11

T3

20

auto[ADC_CTRL_FILTER_COND_OUT]

3680

1

T2

8

T6

12

T9

16

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21776

1

T1

156

T2

8

T3

20

auto[1]

6194

1

T2

11

T6

12

T9

16

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23680

1

T1

153

T2

19

T3

20

auto[1]

4290

1

T1

3

T5

19

T9

14

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	43	1			T48	1		T37	4		T228	11
values[0]	45	1			T243	20		T282	1		T178	1
values[1]	602	1			T6	12		T125	13		T16	16
values[2]	3057	1			T13	13		T41	50		T43	19
values[3]	928	1			T6	7		T131	1		T125	18
values[4]	763	1			T5	17		T11	15		T14	6
values[5]	759	1			T11	5		T48	1		T126	3
values[6]	693	1			T5	26		T6	7		T9	19
values[7]	540	1			T9	16		T44	25		T141	1
values[8]	782	1			T2	11		T14	3		T106	3
values[9]	1314	1			T2	8		T12	14		T14	39
minimum	18444	1			T1	156		T3	20		T7	14

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	808	1			T6	12		T13	13		T44	17
values[1]	3111	1			T41	50		T43	19		T105	23
values[2]	927	1			T5	17		T6	7		T44	19
values[3]	853	1			T11	15		T132	12		T126	3
values[4]	660	1			T5	26		T10	15		T11	5
values[5]	643	1			T6	7		T9	19		T32	4
values[6]	519	1			T9	16		T14	3		T44	25
values[7]	882	1			T2	11		T131	16		T132	14
values[8]	736	1			T2	8		T12	14		T14	39
values[9]	387	1			T15	24		T48	1		T131	3
minimum	18444	1			T1	156		T3	20		T7	14

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23687

1

T1

156

T2

2

T3

20

auto[1]

4283

1

T2

17

T5

22

T6

23

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T13	10		T44	10		T125	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T6	12		T132	1		T30	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1760	1			T41	50		T43	2		T105	23
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T106	17		T125	18		T37	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T5	9		T6	7		T44	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T181	8		T126	14		T138	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T11	8		T126	3		T16	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T132	1		T30	11		T33	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T5	15		T11	3		T182	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T10	5		T14	3		T48	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T6	7		T9	11		T32	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T141	1		T128	12		T129	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T283	1		T161	1		T250	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T9	10		T14	2		T44	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T2	11		T132	1		T26	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T131	1		T245	13		T240	21
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T14	19		T15	1		T48	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T2	8		T12	14		T127	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T48	1		T131	1		T106	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T15	13		T125	7		T134	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18288	1			T1	153		T3	20		T7	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T13	3		T44	7		T16	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T132	3		T33	1		T159	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1062	1			T43	17		T183	13		T136	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T106	18		T37	1		T137	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T5	8		T44	9		T34	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T181	2		T126	14		T138	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T11	7		T16	8		T139	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T132	11		T33	1		T129	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T5	11		T11	2		T238	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T10	10		T14	3		T38	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T9	8		T235	15		T243	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T128	2		T129	19		T138	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T250	8		T284	7		T275	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T9	6		T14	1		T44	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T132	13		T26	6		T37	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T131	15		T17	1		T272	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T14	20		T15	3		T37	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T164	14		T149	5		T79	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T131	2		T106	13		T243	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T15	11		T134	1		T232	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T1	3		T13	4		T33	4

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T48	1		T37	2		T228	11
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T162	6		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T282	1		T178	1		T285	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T243	9		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T125	13		T16	8		T135	18
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T6	12		T30	7		T33	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1721	1			T13	10		T41	50		T43	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T132	1		T106	17		T37	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T6	7		T131	1		T16	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T125	18		T181	8		T126	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T5	9		T11	8		T44	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T14	3		T132	1		T33	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T11	3		T126	3		T229	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T48	1		T30	11		T129	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T5	15		T6	7		T9	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T10	5		T141	1		T128	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T141	1		T283	1		T235	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T9	10		T44	13		T138	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T2	11		T182	1		T26	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T14	2		T106	3		T134	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	325	1			T14	19		T15	1		T48	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	389	1			T2	8		T12	14		T15	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18288	1			T1	153		T3	20		T7	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T37	2		T83	5		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T162	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T285	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T243	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T16	8		T135	14		T129	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T33	1		T159	10		T140	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1022	1			T13	3		T43	17		T44	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T132	3		T106	18		T37	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T16	8		T34	11		T130	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T181	2		T126	14		T138	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T5	8		T11	7		T44	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T14	3		T132	11		T33	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T11	2		T229	9		T147	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T129	6		T38	4		T39	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T5	11		T9	8		T243	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T10	10		T128	2		T129	19
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T235	15		T152	14		T284	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T9	6		T44	12		T138	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T26	6		T37	1		T231	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T14	1		T134	11		T135	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T14	20		T15	3		T131	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	349	1			T15	11		T131	15		T134	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T1	3		T13	4		T33	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T13	10		T44	8		T125	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T6	1		T132	4		T30	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1424	1			T41	3		T43	19		T105	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T106	19		T125	1		T37	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T5	9		T6	1		T44	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T181	3		T126	15		T138	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	289	1			T11	8		T126	1		T16	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T132	12		T30	1		T33	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T5	12		T11	3		T182	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T10	11		T14	4		T48	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T6	1		T9	9		T32	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T141	1		T128	3		T129	20
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T283	1		T161	1		T250	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T9	7		T14	2		T44	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T2	1		T132	14		T26	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T131	16		T245	1		T240	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T14	21		T15	4		T48	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T2	1		T12	1		T127	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T48	1		T131	3		T106	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T15	12		T125	1		T134	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18444	1			T1	156		T3	20		T7	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T13	3		T44	9		T125	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T6	11		T30	6		T159	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1398	1			T41	47		T105	21		T241	40
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T106	16		T125	17		T37	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T5	8		T6	6		T44	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T181	7		T126	13		T245	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T11	7		T126	2		T16	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T30	10		T129	2		T236	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T5	14		T11	2		T238	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T10	4		T14	2		T38	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T6	6		T9	10		T32	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T128	11		T129	15		T140	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T250	9		T246	15		T275	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T9	9		T14	1		T44	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T2	10		T26	4		T228	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T245	12		T240	20		T146	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T14	18		T37	1		T236	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T2	7		T12	13		T239	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T106	11		T228	10		T286	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T15	12		T125	6		T232	8

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T48	1		T37	3		T228	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T162	11		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T282	1		T178	1		T285	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T243	12		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T125	1		T16	10		T135	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T6	1		T30	1		T33	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1376	1			T13	10		T41	3		T43	19
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T132	4		T106	19		T37	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	340	1			T6	1		T131	1		T16	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T125	1		T181	3		T126	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T5	9		T11	8		T44	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T14	4		T132	12		T33	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T11	3		T126	1		T229	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T48	1		T30	1		T129	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T5	12		T6	1		T9	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T10	11		T141	1		T128	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T141	1		T283	1		T235	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T9	7		T44	13		T138	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T2	1		T182	1		T26	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T14	2		T106	1		T134	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	314	1			T14	21		T15	4		T48	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	437	1			T2	1		T12	1		T15	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18444	1			T1	156		T3	20		T7	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T37	1		T228	10		T83	4
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T162	5		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T285	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T243	8		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T125	12		T16	6		T135	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T6	11		T30	6		T159	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1367	1			T13	3		T41	47		T44	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T106	16		T37	1		T229	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T6	6		T16	4		T34	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T125	17		T181	7		T126	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T5	8		T11	7		T44	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T14	2		T236	15		T137	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T11	2		T126	2		T229	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T30	10		T129	2		T38	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T5	14		T6	6		T9	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T10	4		T128	11		T129	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T235	15		T254	4		T246	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T9	9		T44	12		T244	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T2	10		T26	4		T228	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T14	1		T106	2		T134	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T14	18		T106	11		T236	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	301	1			T2	7		T12	13		T15	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23687

1

T1

156

T2

2

T3

20

auto[1]

auto[0]

4283

1

T2

17

T5

22

T6

23