Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27970

1

T1

156

T2

19

T3

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

24303

1

T1

156

T2

11

T3

20

auto[ADC_CTRL_FILTER_COND_OUT]

3667

1

T2

8

T6

12

T9

16

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21738

1

T1

156

T2

8

T3

20

auto[1]

6232

1

T2

11

T6

12

T9

16

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23680

1

T1

153

T2

19

T3

20

auto[1]

4290

1

T1

3

T5

19

T9

14

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	177	1			T48	1		T37	4		T127	1
values[0]	23	1			T285	23		-	-		-	-
values[1]	640	1			T6	12		T44	17		T125	13
values[2]	3043	1			T13	13		T41	50		T43	19
values[3]	928	1			T6	7		T131	1		T125	18
values[4]	775	1			T5	17		T11	15		T44	19
values[5]	769	1			T11	5		T14	6		T48	1
values[6]	661	1			T5	26		T6	7		T9	19
values[7]	581	1			T9	16		T44	25		T141	1
values[8]	706	1			T2	11		T14	3		T106	3
values[9]	1223	1			T2	8		T12	14		T14	39
minimum	18444	1			T1	156		T3	20		T7	14

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	542	1			T6	12		T13	13		T44	17
values[1]	3127	1			T41	50		T43	19		T105	23
values[2]	953	1			T5	17		T6	7		T44	19
values[3]	772	1			T11	15		T132	12		T30	23
values[4]	720	1			T5	26		T10	15		T11	5
values[5]	663	1			T6	7		T9	19		T32	4
values[6]	499	1			T9	16		T44	25		T106	3
values[7]	845	1			T2	11		T14	3		T131	16
values[8]	963	1			T2	8		T12	14		T14	39
values[9]	194	1			T125	7		T134	2		T228	11
minimum	18692	1			T1	156		T3	20		T7	14

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23687

1

T1

156

T2

2

T3

20

auto[1]

4283

1

T2

17

T5

22

T6

23

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T13	10		T44	10		T125	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T6	12		T132	1		T30	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1758	1			T41	50		T43	2		T105	23
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T106	17		T37	6		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T5	9		T6	7		T44	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T125	18		T181	8		T126	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T11	8		T30	12		T139	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T132	1		T30	11		T33	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T5	15		T11	3		T182	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T10	5		T14	3		T48	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T6	7		T9	11		T32	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T128	12		T129	16		T138	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T44	13		T283	1		T161	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T9	10		T106	3		T134	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T2	11		T132	1		T26	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T14	2		T131	1		T245	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T14	19		T15	1		T48	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	310	1			T2	8		T12	14		T15	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T228	11		T286	19		T287	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T125	7		T134	1		T162	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18319	1			T1	153		T3	20		T7	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T33	1		T159	14		T204	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T13	3		T44	7		T135	29
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T132	3		T33	1		T140	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1060	1			T43	17		T183	13		T136	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T106	18		T37	1		T137	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T5	8		T44	9		T16	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T181	2		T126	14		T138	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T11	7		T139	1		T229	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T132	11		T33	1		T129	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T5	11		T11	2		T160	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T10	10		T14	3		T39	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T9	8		T235	15		T243	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T128	2		T129	19		T138	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T44	12		T250	8		T284	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T9	6		T134	11		T135	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T132	13		T26	6		T37	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T14	1		T131	15		T17	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T14	20		T15	3		T131	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T15	11		T232	7		T164	22
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T83	5		T288	11		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T134	1		T162	10		T75	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T1	3		T13	4		T16	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T159	10		T204	13		T270	4

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T48	1		T37	2		T287	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T127	1		T239	15		T162	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T285	13		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T44	10		T125	13		T16	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T6	12		T30	7		T33	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1721	1			T13	10		T41	50		T43	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T132	1		T106	17		T37	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T6	7		T131	1		T16	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T125	18		T181	8		T126	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T5	9		T11	8		T44	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T132	1		T30	11		T33	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T11	3		T126	3		T147	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T14	3		T48	1		T129	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T5	15		T6	7		T9	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T10	5		T141	1		T128	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T44	13		T141	1		T283	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T9	10		T138	1		T144	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T2	11		T182	1		T26	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T14	2		T106	3		T134	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T14	19		T15	1		T48	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	381	1			T2	8		T12	14		T15	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18288	1			T1	153		T3	20		T7	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T37	2		T83	5		T288	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T162	10		T75	10		T260	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T285	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T44	7		T16	8		T135	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T33	1		T159	10		T140	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1031	1			T13	3		T43	17		T183	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T132	3		T106	18		T37	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T16	8		T34	11		T130	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T181	2		T126	14		T138	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T5	8		T11	7		T44	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T132	11		T33	1		T137	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T11	2		T147	15		T160	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T14	3		T129	6		T38	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T5	11		T9	8		T243	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T10	10		T128	2		T129	19
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T44	12		T235	15		T250	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T9	6		T138	12		T144	22
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T26	6		T37	1		T231	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T14	1		T134	11		T135	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T14	20		T15	3		T131	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	331	1			T15	11		T131	15		T134	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T1	3		T13	4		T33	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T13	10		T44	8		T125	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T6	1		T132	4		T30	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1422	1			T41	3		T43	19		T105	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T106	19		T37	6		T137	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	294	1			T5	9		T6	1		T44	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T125	1		T181	3		T126	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T11	8		T30	1		T139	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T132	12		T30	1		T33	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T5	12		T11	3		T182	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T10	11		T14	4		T48	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T6	1		T9	9		T32	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T128	3		T129	20		T138	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T44	13		T283	1		T161	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T9	7		T106	1		T134	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T2	1		T132	14		T26	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T14	2		T131	16		T245	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T14	21		T15	4		T48	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T2	1		T12	1		T15	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T228	1		T286	1		T287	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T125	1		T134	2		T162	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18510	1			T1	156		T3	20		T7	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T33	1		T159	11		T204	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T13	3		T44	9		T125	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T6	11		T30	6		T140	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1396	1			T41	47		T105	21		T241	40
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T106	16		T37	1		T78	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T5	8		T6	6		T44	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T125	17		T181	7		T126	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T11	7		T30	11		T139	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T30	10		T129	2		T236	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T5	14		T11	2		T126	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T10	4		T14	2		T227	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T6	6		T9	10		T32	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T128	11		T129	15		T140	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T44	12		T250	9		T246	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T9	9		T106	2		T134	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T2	10		T26	4		T228	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T14	1		T245	12		T146	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T14	18		T106	11		T37	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T2	7		T12	13		T15	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T228	10		T286	18		T83	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T125	6		T162	5		T260	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T16	6		T129	2		T289	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T159	13		T204	11		T290	11

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T48	1		T37	3		T287	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T127	1		T239	1		T162	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T285	11		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T44	8		T125	1		T16	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T6	1		T30	1		T33	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1385	1			T13	10		T41	3		T43	19
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T132	4		T106	19		T37	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	312	1			T6	1		T131	1		T16	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T125	1		T181	3		T126	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T5	9		T11	8		T44	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T132	12		T30	1		T33	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T11	3		T126	1		T147	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T14	4		T48	1		T129	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T5	12		T6	1		T9	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T10	11		T141	1		T128	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T44	13		T141	1		T283	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T9	7		T138	13		T144	24
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T2	1		T182	1		T26	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T14	2		T106	1		T134	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T14	21		T15	4		T48	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	401	1			T2	1		T12	1		T15	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18444	1			T1	156		T3	20		T7	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T37	1		T249	7		T291	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T239	14		T162	5		T260	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T285	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T44	9		T125	12		T16	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T6	11		T30	6		T159	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1367	1			T13	3		T41	47		T105	21
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T106	16		T37	1		T78	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T6	6		T16	4		T34	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T125	17		T181	7		T126	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T5	8		T11	7		T44	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T30	10		T137	9		T163	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T11	2		T126	2		T147	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T14	2		T129	2		T38	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T5	14		T6	6		T9	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T10	4		T128	11		T129	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T44	12		T235	15		T254	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T9	9		T244	9		T49	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T2	10		T26	4		T228	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T14	1		T106	2		T134	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T14	18		T106	11		T228	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	311	1			T2	7		T12	13		T15	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23687

1

T1

156

T2

2

T3

20

auto[1]

auto[0]

4283

1

T2

17

T5

22

T6

23