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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.71 99.07 96.62 100.00 100.00 98.83 98.33 91.09


Total test records in report: 918
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T791 /workspace/coverage/default/32.adc_ctrl_filters_polled.2774502083 Mar 21 12:45:56 PM PDT 24 Mar 21 12:59:09 PM PDT 24 325365722253 ps
T792 /workspace/coverage/default/33.adc_ctrl_filters_wakeup_fixed.1902021177 Mar 21 12:46:13 PM PDT 24 Mar 21 12:50:18 PM PDT 24 404574347150 ps
T327 /workspace/coverage/default/47.adc_ctrl_fsm_reset.289371979 Mar 21 12:47:52 PM PDT 24 Mar 21 12:55:31 PM PDT 24 108961569499 ps
T793 /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.3807678309 Mar 21 12:37:57 PM PDT 24 Mar 21 12:38:00 PM PDT 24 428277019 ps
T794 /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.650603284 Mar 21 12:37:45 PM PDT 24 Mar 21 12:37:46 PM PDT 24 316664928 ps
T57 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.1652651276 Mar 21 12:37:47 PM PDT 24 Mar 21 12:37:51 PM PDT 24 4468312458 ps
T61 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.405431625 Mar 21 12:37:50 PM PDT 24 Mar 21 12:37:52 PM PDT 24 327756681 ps
T65 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.4251627645 Mar 21 12:38:02 PM PDT 24 Mar 21 12:38:05 PM PDT 24 583900836 ps
T66 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.3077972431 Mar 21 12:37:50 PM PDT 24 Mar 21 12:37:52 PM PDT 24 552569881 ps
T67 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.3319788344 Mar 21 12:37:46 PM PDT 24 Mar 21 12:37:48 PM PDT 24 469886958 ps
T58 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.2540820677 Mar 21 12:38:04 PM PDT 24 Mar 21 12:38:12 PM PDT 24 4390225630 ps
T59 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.121787980 Mar 21 12:37:53 PM PDT 24 Mar 21 12:38:05 PM PDT 24 8293419389 ps
T84 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.4064670696 Mar 21 12:38:08 PM PDT 24 Mar 21 12:38:10 PM PDT 24 490951444 ps
T68 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.26794710 Mar 21 12:37:57 PM PDT 24 Mar 21 12:38:00 PM PDT 24 636121472 ps
T70 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.454985015 Mar 21 12:37:40 PM PDT 24 Mar 21 12:37:42 PM PDT 24 675117204 ps
T54 /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.2656832947 Mar 21 12:37:59 PM PDT 24 Mar 21 12:38:08 PM PDT 24 2473218937 ps
T120 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.1333758519 Mar 21 12:37:58 PM PDT 24 Mar 21 12:37:59 PM PDT 24 598124377 ps
T85 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.1987517582 Mar 21 12:37:59 PM PDT 24 Mar 21 12:38:00 PM PDT 24 530239112 ps
T107 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.3593534498 Mar 21 12:37:42 PM PDT 24 Mar 21 12:37:43 PM PDT 24 446429169 ps
T55 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.1097427920 Mar 21 12:37:54 PM PDT 24 Mar 21 12:39:22 PM PDT 24 51127357062 ps
T69 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.732923757 Mar 21 12:37:46 PM PDT 24 Mar 21 12:37:49 PM PDT 24 1619424110 ps
T795 /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.720831112 Mar 21 12:37:35 PM PDT 24 Mar 21 12:37:38 PM PDT 24 392170566 ps
T108 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.3070596683 Mar 21 12:37:43 PM PDT 24 Mar 21 12:37:44 PM PDT 24 484470598 ps
T56 /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.1070375113 Mar 21 12:37:50 PM PDT 24 Mar 21 12:37:52 PM PDT 24 4618732089 ps
T796 /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.2687143631 Mar 21 12:37:45 PM PDT 24 Mar 21 12:37:47 PM PDT 24 505165082 ps
T797 /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.1018090036 Mar 21 12:38:08 PM PDT 24 Mar 21 12:38:09 PM PDT 24 497034960 ps
T798 /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.1557863285 Mar 21 12:37:50 PM PDT 24 Mar 21 12:37:51 PM PDT 24 319067960 ps
T799 /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.3378620959 Mar 21 12:37:58 PM PDT 24 Mar 21 12:37:59 PM PDT 24 432477311 ps
T121 /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.1551150687 Mar 21 12:37:45 PM PDT 24 Mar 21 12:37:51 PM PDT 24 5196610524 ps
T800 /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.1011690743 Mar 21 12:37:58 PM PDT 24 Mar 21 12:37:59 PM PDT 24 419516614 ps
T801 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.3056152178 Mar 21 12:37:36 PM PDT 24 Mar 21 12:37:37 PM PDT 24 591581322 ps
T802 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.4083665909 Mar 21 12:37:56 PM PDT 24 Mar 21 12:38:00 PM PDT 24 485868243 ps
T71 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.1331626578 Mar 21 12:37:50 PM PDT 24 Mar 21 12:37:51 PM PDT 24 495484449 ps
T72 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.256473227 Mar 21 12:37:43 PM PDT 24 Mar 21 12:37:46 PM PDT 24 388025128 ps
T109 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.1093145091 Mar 21 12:37:43 PM PDT 24 Mar 21 12:37:45 PM PDT 24 551757062 ps
T318 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.710886532 Mar 21 12:37:49 PM PDT 24 Mar 21 12:37:54 PM PDT 24 4237154903 ps
T803 /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.2352574086 Mar 21 12:37:48 PM PDT 24 Mar 21 12:37:50 PM PDT 24 418388291 ps
T804 /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.105139337 Mar 21 12:37:48 PM PDT 24 Mar 21 12:37:49 PM PDT 24 410545423 ps
T805 /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.2600418061 Mar 21 12:38:00 PM PDT 24 Mar 21 12:38:01 PM PDT 24 371283498 ps
T806 /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.3444907521 Mar 21 12:38:02 PM PDT 24 Mar 21 12:38:04 PM PDT 24 449455311 ps
T807 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.390964280 Mar 21 12:37:56 PM PDT 24 Mar 21 12:38:02 PM PDT 24 8578681287 ps
T110 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.2268601980 Mar 21 12:37:49 PM PDT 24 Mar 21 12:37:50 PM PDT 24 499211720 ps
T122 /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.3213824573 Mar 21 12:37:45 PM PDT 24 Mar 21 12:37:53 PM PDT 24 2794313190 ps
T808 /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.3311266293 Mar 21 12:38:37 PM PDT 24 Mar 21 12:38:39 PM PDT 24 467197689 ps
T809 /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.3469694242 Mar 21 12:37:54 PM PDT 24 Mar 21 12:37:56 PM PDT 24 518543207 ps
T810 /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.1021884001 Mar 21 12:37:47 PM PDT 24 Mar 21 12:37:49 PM PDT 24 504325596 ps
T811 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.3025733387 Mar 21 12:37:41 PM PDT 24 Mar 21 12:37:44 PM PDT 24 874584643 ps
T812 /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.3050194686 Mar 21 12:37:59 PM PDT 24 Mar 21 12:38:01 PM PDT 24 311564135 ps
T111 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.314083329 Mar 21 12:37:41 PM PDT 24 Mar 21 12:37:45 PM PDT 24 1209949522 ps
T813 /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.1687105023 Mar 21 12:37:48 PM PDT 24 Mar 21 12:37:50 PM PDT 24 474207543 ps
T814 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.3764098324 Mar 21 12:37:48 PM PDT 24 Mar 21 12:37:51 PM PDT 24 1254771832 ps
T815 /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.3258875636 Mar 21 12:37:58 PM PDT 24 Mar 21 12:38:00 PM PDT 24 423098318 ps
T123 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.868671599 Mar 21 12:37:58 PM PDT 24 Mar 21 12:38:00 PM PDT 24 368833120 ps
T816 /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.1208469360 Mar 21 12:38:10 PM PDT 24 Mar 21 12:38:19 PM PDT 24 2203279578 ps
T322 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.1688945323 Mar 21 12:37:50 PM PDT 24 Mar 21 12:37:58 PM PDT 24 8477199850 ps
T817 /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.2254400711 Mar 21 12:37:50 PM PDT 24 Mar 21 12:37:52 PM PDT 24 458318721 ps
T818 /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.2742665769 Mar 21 12:38:16 PM PDT 24 Mar 21 12:38:18 PM PDT 24 422572921 ps
T819 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.2484642751 Mar 21 12:37:46 PM PDT 24 Mar 21 12:37:49 PM PDT 24 1328956266 ps
T820 /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.4098078722 Mar 21 12:37:39 PM PDT 24 Mar 21 12:37:53 PM PDT 24 4633347549 ps
T112 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.1186291993 Mar 21 12:37:48 PM PDT 24 Mar 21 12:37:50 PM PDT 24 419212080 ps
T821 /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.415005044 Mar 21 12:37:46 PM PDT 24 Mar 21 12:37:58 PM PDT 24 4825903962 ps
T822 /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.2599167778 Mar 21 12:37:47 PM PDT 24 Mar 21 12:37:49 PM PDT 24 285761906 ps
T823 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.1051179182 Mar 21 12:38:07 PM PDT 24 Mar 21 12:38:08 PM PDT 24 527892628 ps
T824 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.568729014 Mar 21 12:37:57 PM PDT 24 Mar 21 12:37:59 PM PDT 24 435217252 ps
T113 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.3968667461 Mar 21 12:37:49 PM PDT 24 Mar 21 12:37:51 PM PDT 24 518062203 ps
T825 /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.1021690279 Mar 21 12:37:40 PM PDT 24 Mar 21 12:37:43 PM PDT 24 4360219293 ps
T114 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.539638513 Mar 21 12:37:32 PM PDT 24 Mar 21 12:38:06 PM PDT 24 33382010569 ps
T826 /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.3361684624 Mar 21 12:38:01 PM PDT 24 Mar 21 12:38:07 PM PDT 24 475820599 ps
T827 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.1218623894 Mar 21 12:37:56 PM PDT 24 Mar 21 12:38:18 PM PDT 24 8234367329 ps
T828 /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.159943007 Mar 21 12:37:52 PM PDT 24 Mar 21 12:37:53 PM PDT 24 303167612 ps
T829 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.1207710650 Mar 21 12:37:47 PM PDT 24 Mar 21 12:37:49 PM PDT 24 1093648929 ps
T830 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.276333515 Mar 21 12:37:34 PM PDT 24 Mar 21 12:37:37 PM PDT 24 318812385 ps
T831 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.2518090220 Mar 21 12:37:45 PM PDT 24 Mar 21 12:37:46 PM PDT 24 528970374 ps
T832 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.3685684051 Mar 21 12:37:43 PM PDT 24 Mar 21 12:37:45 PM PDT 24 425997401 ps
T833 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.1489110971 Mar 21 12:37:52 PM PDT 24 Mar 21 12:37:54 PM PDT 24 525934262 ps
T834 /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.2589230349 Mar 21 12:38:03 PM PDT 24 Mar 21 12:38:04 PM PDT 24 516870046 ps
T835 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.1584784614 Mar 21 12:37:39 PM PDT 24 Mar 21 12:37:43 PM PDT 24 4567411091 ps
T836 /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.4044428414 Mar 21 12:38:00 PM PDT 24 Mar 21 12:38:02 PM PDT 24 307400054 ps
T115 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.1238310798 Mar 21 12:37:47 PM PDT 24 Mar 21 12:37:49 PM PDT 24 458194869 ps
T837 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.1962265685 Mar 21 12:37:39 PM PDT 24 Mar 21 12:37:41 PM PDT 24 450327130 ps
T838 /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.2356533123 Mar 21 12:37:48 PM PDT 24 Mar 21 12:37:50 PM PDT 24 392298277 ps
T839 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.4136529083 Mar 21 12:37:32 PM PDT 24 Mar 21 12:37:36 PM PDT 24 955380983 ps
T840 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.759954199 Mar 21 12:37:29 PM PDT 24 Mar 21 12:37:40 PM PDT 24 4428436843 ps
T841 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.1567374997 Mar 21 12:38:04 PM PDT 24 Mar 21 12:38:06 PM PDT 24 475843993 ps
T842 /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.1531330457 Mar 21 12:37:50 PM PDT 24 Mar 21 12:37:51 PM PDT 24 496393447 ps
T843 /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.731119575 Mar 21 12:37:48 PM PDT 24 Mar 21 12:37:50 PM PDT 24 386811379 ps
T844 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.3077089367 Mar 21 12:37:52 PM PDT 24 Mar 21 12:37:54 PM PDT 24 559163101 ps
T845 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.4224901588 Mar 21 12:37:48 PM PDT 24 Mar 21 12:37:49 PM PDT 24 376637074 ps
T846 /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.441360725 Mar 21 12:37:49 PM PDT 24 Mar 21 12:37:50 PM PDT 24 388982409 ps
T847 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.4252912557 Mar 21 12:37:49 PM PDT 24 Mar 21 12:37:50 PM PDT 24 500326579 ps
T116 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.1545409988 Mar 21 12:37:56 PM PDT 24 Mar 21 12:38:01 PM PDT 24 864872443 ps
T848 /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.30226784 Mar 21 12:37:55 PM PDT 24 Mar 21 12:37:56 PM PDT 24 446912645 ps
T849 /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.1684830620 Mar 21 12:37:57 PM PDT 24 Mar 21 12:37:59 PM PDT 24 469044678 ps
T850 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.3585310167 Mar 21 12:37:49 PM PDT 24 Mar 21 12:37:51 PM PDT 24 423241025 ps
T851 /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.2259143034 Mar 21 12:37:51 PM PDT 24 Mar 21 12:37:53 PM PDT 24 344359768 ps
T852 /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.1101609211 Mar 21 12:37:51 PM PDT 24 Mar 21 12:37:55 PM PDT 24 4689865690 ps
T853 /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.3673391933 Mar 21 12:37:52 PM PDT 24 Mar 21 12:37:58 PM PDT 24 2078011108 ps
T854 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.461705488 Mar 21 12:37:43 PM PDT 24 Mar 21 12:38:07 PM PDT 24 8679798859 ps
T855 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.3012147201 Mar 21 12:38:01 PM PDT 24 Mar 21 12:38:03 PM PDT 24 523707399 ps
T856 /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.704363848 Mar 21 12:37:55 PM PDT 24 Mar 21 12:37:59 PM PDT 24 2135015900 ps
T857 /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.1655922617 Mar 21 12:37:47 PM PDT 24 Mar 21 12:37:49 PM PDT 24 2791823059 ps
T858 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.1114775074 Mar 21 12:37:38 PM PDT 24 Mar 21 12:37:41 PM PDT 24 586315844 ps
T859 /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.1606979818 Mar 21 12:37:58 PM PDT 24 Mar 21 12:38:00 PM PDT 24 495163158 ps
T860 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.1906318348 Mar 21 12:37:48 PM PDT 24 Mar 21 12:37:50 PM PDT 24 731368025 ps
T861 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.2190151157 Mar 21 12:37:45 PM PDT 24 Mar 21 12:37:53 PM PDT 24 8868860481 ps
T862 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.208838092 Mar 21 12:37:56 PM PDT 24 Mar 21 12:38:01 PM PDT 24 4120861484 ps
T863 /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.2177818283 Mar 21 12:38:01 PM PDT 24 Mar 21 12:38:03 PM PDT 24 460941011 ps
T864 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.3022334538 Mar 21 12:38:06 PM PDT 24 Mar 21 12:38:10 PM PDT 24 459721612 ps
T117 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.1614251713 Mar 21 12:37:40 PM PDT 24 Mar 21 12:38:35 PM PDT 24 43965308510 ps
T865 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.504040451 Mar 21 12:37:43 PM PDT 24 Mar 21 12:37:44 PM PDT 24 603468351 ps
T866 /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.1713722959 Mar 21 12:37:50 PM PDT 24 Mar 21 12:37:51 PM PDT 24 511892352 ps
T867 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.522153336 Mar 21 12:37:55 PM PDT 24 Mar 21 12:37:57 PM PDT 24 421074211 ps
T868 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.1236615889 Mar 21 12:37:53 PM PDT 24 Mar 21 12:37:55 PM PDT 24 585628012 ps
T869 /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.415029382 Mar 21 12:38:21 PM PDT 24 Mar 21 12:38:23 PM PDT 24 446448340 ps
T870 /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.72095862 Mar 21 12:37:56 PM PDT 24 Mar 21 12:37:59 PM PDT 24 477939887 ps
T871 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.2791060431 Mar 21 12:37:47 PM PDT 24 Mar 21 12:37:49 PM PDT 24 370572306 ps
T872 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.1307046092 Mar 21 12:37:43 PM PDT 24 Mar 21 12:37:51 PM PDT 24 8483327330 ps
T873 /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.2519074074 Mar 21 12:37:49 PM PDT 24 Mar 21 12:37:50 PM PDT 24 522489668 ps
T319 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.720182728 Mar 21 12:37:57 PM PDT 24 Mar 21 12:38:10 PM PDT 24 4321433832 ps
T874 /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.1640075931 Mar 21 12:37:58 PM PDT 24 Mar 21 12:37:59 PM PDT 24 431907208 ps
T875 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.1331935800 Mar 21 12:37:42 PM PDT 24 Mar 21 12:37:45 PM PDT 24 503267051 ps
T876 /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.2955720587 Mar 21 12:37:51 PM PDT 24 Mar 21 12:38:02 PM PDT 24 4640735046 ps
T877 /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.3984256855 Mar 21 12:38:01 PM PDT 24 Mar 21 12:38:06 PM PDT 24 1921925365 ps
T878 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.4072406733 Mar 21 12:37:52 PM PDT 24 Mar 21 12:37:55 PM PDT 24 482694415 ps
T118 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.588741485 Mar 21 12:37:48 PM PDT 24 Mar 21 12:37:50 PM PDT 24 499656121 ps
T879 /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.2009330954 Mar 21 12:37:53 PM PDT 24 Mar 21 12:38:02 PM PDT 24 4906845437 ps
T880 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.454439745 Mar 21 12:37:49 PM PDT 24 Mar 21 12:37:51 PM PDT 24 516540794 ps
T881 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.2120215215 Mar 21 12:37:44 PM PDT 24 Mar 21 12:37:55 PM PDT 24 4346364757 ps
T882 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.3561195018 Mar 21 12:37:51 PM PDT 24 Mar 21 12:37:53 PM PDT 24 479853590 ps
T883 /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.2758476490 Mar 21 12:37:39 PM PDT 24 Mar 21 12:37:42 PM PDT 24 2358123374 ps
T320 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.1096486349 Mar 21 12:37:59 PM PDT 24 Mar 21 12:38:11 PM PDT 24 7679209400 ps
T884 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.206087331 Mar 21 12:37:37 PM PDT 24 Mar 21 12:37:39 PM PDT 24 678160285 ps
T885 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.74458978 Mar 21 12:37:46 PM PDT 24 Mar 21 12:38:07 PM PDT 24 8099901631 ps
T886 /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.304280993 Mar 21 12:37:54 PM PDT 24 Mar 21 12:37:56 PM PDT 24 408055693 ps
T887 /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.833987767 Mar 21 12:37:39 PM PDT 24 Mar 21 12:37:40 PM PDT 24 501560154 ps
T888 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.201311025 Mar 21 12:37:47 PM PDT 24 Mar 21 12:37:51 PM PDT 24 552475489 ps
T889 /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.924861711 Mar 21 12:37:29 PM PDT 24 Mar 21 12:37:36 PM PDT 24 5339321987 ps
T890 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.1389867240 Mar 21 12:37:49 PM PDT 24 Mar 21 12:37:52 PM PDT 24 354591204 ps
T891 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.521451448 Mar 21 12:37:59 PM PDT 24 Mar 21 12:38:02 PM PDT 24 489045774 ps
T892 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.3079263089 Mar 21 12:38:00 PM PDT 24 Mar 21 12:38:02 PM PDT 24 515130338 ps
T893 /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.2729536640 Mar 21 12:37:59 PM PDT 24 Mar 21 12:38:00 PM PDT 24 470955174 ps
T894 /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.2006862514 Mar 21 12:37:50 PM PDT 24 Mar 21 12:37:51 PM PDT 24 557109551 ps
T895 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.3773736041 Mar 21 12:37:56 PM PDT 24 Mar 21 12:38:10 PM PDT 24 4372175977 ps
T896 /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.3328153458 Mar 21 12:37:58 PM PDT 24 Mar 21 12:37:59 PM PDT 24 381175964 ps
T897 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.450263573 Mar 21 12:37:59 PM PDT 24 Mar 21 12:38:00 PM PDT 24 542299857 ps
T898 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.3863210867 Mar 21 12:37:48 PM PDT 24 Mar 21 12:37:52 PM PDT 24 1493155659 ps
T899 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.3763377674 Mar 21 12:37:56 PM PDT 24 Mar 21 12:37:59 PM PDT 24 666507627 ps
T900 /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.3700601673 Mar 21 12:37:50 PM PDT 24 Mar 21 12:37:51 PM PDT 24 481043432 ps
T901 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.2855870145 Mar 21 12:37:47 PM PDT 24 Mar 21 12:37:49 PM PDT 24 393892946 ps
T902 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.720603342 Mar 21 12:37:35 PM PDT 24 Mar 21 12:38:02 PM PDT 24 27979643791 ps
T903 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.3121281378 Mar 21 12:37:46 PM PDT 24 Mar 21 12:37:49 PM PDT 24 515289646 ps
T321 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.691642099 Mar 21 12:37:47 PM PDT 24 Mar 21 12:38:07 PM PDT 24 8383022000 ps
T119 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.3873067073 Mar 21 12:37:51 PM PDT 24 Mar 21 12:39:24 PM PDT 24 49972372683 ps
T904 /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.4205857049 Mar 21 12:37:48 PM PDT 24 Mar 21 12:37:59 PM PDT 24 4457963328 ps
T905 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.879040468 Mar 21 12:37:41 PM PDT 24 Mar 21 12:37:45 PM PDT 24 974516774 ps
T906 /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.1206686249 Mar 21 12:37:49 PM PDT 24 Mar 21 12:37:50 PM PDT 24 358709052 ps
T907 /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.621115334 Mar 21 12:37:55 PM PDT 24 Mar 21 12:37:58 PM PDT 24 2139687544 ps
T908 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.2208450320 Mar 21 12:37:57 PM PDT 24 Mar 21 12:38:00 PM PDT 24 762459765 ps
T909 /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.3156440705 Mar 21 12:37:56 PM PDT 24 Mar 21 12:38:09 PM PDT 24 4842120332 ps
T910 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.1947115085 Mar 21 12:37:47 PM PDT 24 Mar 21 12:37:50 PM PDT 24 381904041 ps
T911 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.3050106364 Mar 21 12:37:48 PM PDT 24 Mar 21 12:37:50 PM PDT 24 507212914 ps
T912 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.1629385585 Mar 21 12:37:52 PM PDT 24 Mar 21 12:38:14 PM PDT 24 8049696644 ps
T913 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.663258863 Mar 21 12:38:01 PM PDT 24 Mar 21 12:38:04 PM PDT 24 994334363 ps
T914 /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.4252321946 Mar 21 12:37:44 PM PDT 24 Mar 21 12:37:45 PM PDT 24 497119576 ps
T915 /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.2899313941 Mar 21 12:38:02 PM PDT 24 Mar 21 12:38:03 PM PDT 24 378947030 ps
T916 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.2678810366 Mar 21 12:37:37 PM PDT 24 Mar 21 12:37:38 PM PDT 24 371410832 ps
T917 /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.2261877967 Mar 21 12:37:53 PM PDT 24 Mar 21 12:37:54 PM PDT 24 449370671 ps
T918 /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.4006319160 Mar 21 12:38:04 PM PDT 24 Mar 21 12:38:05 PM PDT 24 376630938 ps

Test location /workspace/coverage/default/20.adc_ctrl_filters_both.2851546478
Short name T9
Test name
Test status
Simulation time 329436061923 ps
CPU time 794.7 seconds
Started Mar 21 12:44:59 PM PDT 24
Finished Mar 21 12:58:14 PM PDT 24
Peak memory 201700 kb
Host smart-2aca56cb-bb53-4a64-8968-87f4b63acade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851546478 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.2851546478
Directory /workspace/20.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/14.adc_ctrl_fsm_reset.2679867762
Short name T36
Test name
Test status
Simulation time 118353696187 ps
CPU time 615.8 seconds
Started Mar 21 12:44:52 PM PDT 24
Finished Mar 21 12:55:08 PM PDT 24
Peak memory 202200 kb
Host smart-e6288908-7216-4c7f-8f5d-0c974aa40173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679867762 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.2679867762
Directory /workspace/14.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.894266181
Short name T16
Test name
Test status
Simulation time 353052623896 ps
CPU time 133.12 seconds
Started Mar 21 12:45:12 PM PDT 24
Finished Mar 21 12:47:25 PM PDT 24
Peak memory 210092 kb
Host smart-a196b625-7f59-4f7c-a76a-b4224e898e0a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894266181 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all_with_rand_reset.894266181
Directory /workspace/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.4248965693
Short name T37
Test name
Test status
Simulation time 281979505635 ps
CPU time 216.14 seconds
Started Mar 21 12:46:10 PM PDT 24
Finished Mar 21 12:49:47 PM PDT 24
Peak memory 210752 kb
Host smart-3c51d7e0-62b0-4b12-95a0-e328803930cb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248965693 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all_with_rand_reset.4248965693
Directory /workspace/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_clock_gating.1363161137
Short name T44
Test name
Test status
Simulation time 494876667696 ps
CPU time 1027.02 seconds
Started Mar 21 12:47:12 PM PDT 24
Finished Mar 21 01:04:19 PM PDT 24
Peak memory 201864 kb
Host smart-c71d809b-f5ab-4cc7-9a7f-96b360ab27cd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363161137 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gat
ing.1363161137
Directory /workspace/43.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.3621016689
Short name T260
Test name
Test status
Simulation time 276299972429 ps
CPU time 449.99 seconds
Started Mar 21 12:46:19 PM PDT 24
Finished Mar 21 12:53:50 PM PDT 24
Peak memory 210480 kb
Host smart-de025a7b-d613-4c7d-a221-c8a2569722cc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621016689 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all_with_rand_reset.3621016689
Directory /workspace/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_both.2287422454
Short name T135
Test name
Test status
Simulation time 515845772417 ps
CPU time 1187.87 seconds
Started Mar 21 12:47:12 PM PDT 24
Finished Mar 21 01:07:00 PM PDT 24
Peak memory 201688 kb
Host smart-2ef24b9c-2401-4cba-af05-6be575c8566b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287422454 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.2287422454
Directory /workspace/42.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/38.adc_ctrl_clock_gating.2254658142
Short name T145
Test name
Test status
Simulation time 519245032904 ps
CPU time 157.4 seconds
Started Mar 21 12:46:51 PM PDT 24
Finished Mar 21 12:49:28 PM PDT 24
Peak memory 201812 kb
Host smart-114f7767-8385-4cb2-aeb5-c9fcb23eeff3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254658142 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gat
ing.2254658142
Directory /workspace/38.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all.1064462343
Short name T51
Test name
Test status
Simulation time 312693469158 ps
CPU time 1124.79 seconds
Started Mar 21 12:44:21 PM PDT 24
Finished Mar 21 01:03:06 PM PDT 24
Peak memory 210296 kb
Host smart-02f071f9-16c3-4818-8ec9-409712c80d89
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064462343 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.
1064462343
Directory /workspace/7.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt.3695991300
Short name T132
Test name
Test status
Simulation time 487393564792 ps
CPU time 597.15 seconds
Started Mar 21 12:48:01 PM PDT 24
Finished Mar 21 12:57:58 PM PDT 24
Peak memory 201860 kb
Host smart-47327d77-a88d-438c-92fc-e9c348d2e31f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695991300 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.3695991300
Directory /workspace/49.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/32.adc_ctrl_clock_gating.178547172
Short name T229
Test name
Test status
Simulation time 513021530057 ps
CPU time 1221.2 seconds
Started Mar 21 12:45:57 PM PDT 24
Finished Mar 21 01:06:18 PM PDT 24
Peak memory 201856 kb
Host smart-1cf276d5-05da-40e6-a9ba-609210a21492
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178547172 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gati
ng.178547172
Directory /workspace/32.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.405431625
Short name T61
Test name
Test status
Simulation time 327756681 ps
CPU time 2.3 seconds
Started Mar 21 12:37:50 PM PDT 24
Finished Mar 21 12:37:52 PM PDT 24
Peak memory 201896 kb
Host smart-23cd04ca-36b1-4f44-a5a5-886c66146533
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405431625 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.405431625
Directory /workspace/15.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/3.adc_ctrl_clock_gating.1292939133
Short name T129
Test name
Test status
Simulation time 541709213323 ps
CPU time 298.15 seconds
Started Mar 21 12:44:09 PM PDT 24
Finished Mar 21 12:49:07 PM PDT 24
Peak memory 201860 kb
Host smart-eb2afd93-603b-45bc-95f8-374faeab6ebe
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292939133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gati
ng.1292939133
Directory /workspace/3.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_both.2910958551
Short name T106
Test name
Test status
Simulation time 531212616245 ps
CPU time 314.16 seconds
Started Mar 21 12:47:41 PM PDT 24
Finished Mar 21 12:52:55 PM PDT 24
Peak memory 201872 kb
Host smart-0f132c0e-62d7-4844-a24f-05e51be9bc50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910958551 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.2910958551
Directory /workspace/47.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/41.adc_ctrl_clock_gating.3326234730
Short name T140
Test name
Test status
Simulation time 360302030962 ps
CPU time 134.14 seconds
Started Mar 21 12:47:05 PM PDT 24
Finished Mar 21 12:49:20 PM PDT 24
Peak memory 201812 kb
Host smart-ab363644-160d-4567-82e7-47b80b987c5b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326234730 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gat
ing.3326234730
Directory /workspace/41.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup_fixed.3757283556
Short name T41
Test name
Test status
Simulation time 603678842536 ps
CPU time 134.08 seconds
Started Mar 21 12:45:13 PM PDT 24
Finished Mar 21 12:47:28 PM PDT 24
Peak memory 201772 kb
Host smart-be16e753-f13f-4726-8289-58dacc9f50af
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757283556 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21
.adc_ctrl_filters_wakeup_fixed.3757283556
Directory /workspace/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_both.3163186695
Short name T244
Test name
Test status
Simulation time 377856770421 ps
CPU time 238.6 seconds
Started Mar 21 12:45:49 PM PDT 24
Finished Mar 21 12:49:48 PM PDT 24
Peak memory 201712 kb
Host smart-baefef27-4c88-4739-ac92-739a26fe3b21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163186695 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.3163186695
Directory /workspace/28.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/1.adc_ctrl_alert_test.1332431279
Short name T336
Test name
Test status
Simulation time 481710229 ps
CPU time 1.38 seconds
Started Mar 21 12:44:07 PM PDT 24
Finished Mar 21 12:44:08 PM PDT 24
Peak memory 201380 kb
Host smart-2aa30607-ae2e-40de-adbb-8d411472d65e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332431279 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.1332431279
Directory /workspace/1.adc_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.1097427920
Short name T55
Test name
Test status
Simulation time 51127357062 ps
CPU time 87.36 seconds
Started Mar 21 12:37:54 PM PDT 24
Finished Mar 21 12:39:22 PM PDT 24
Peak memory 201916 kb
Host smart-f82d4ef2-709b-462a-8620-f05bd146dab0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097427920 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_
bash.1097427920
Directory /workspace/3.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_both.2817406452
Short name T249
Test name
Test status
Simulation time 499654763492 ps
CPU time 310.19 seconds
Started Mar 21 12:44:47 PM PDT 24
Finished Mar 21 12:49:58 PM PDT 24
Peak memory 201748 kb
Host smart-8d59c8aa-f9fd-414e-877f-cd4a5d4fb54b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817406452 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.2817406452
Directory /workspace/16.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_clock_gating.2132990628
Short name T238
Test name
Test status
Simulation time 354394576638 ps
CPU time 279.77 seconds
Started Mar 21 12:47:32 PM PDT 24
Finished Mar 21 12:52:11 PM PDT 24
Peak memory 201716 kb
Host smart-2a16fcf5-99e0-4cd1-9a6d-0bc532db74ee
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132990628 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gat
ing.2132990628
Directory /workspace/45.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_sec_cm.1997427644
Short name T73
Test name
Test status
Simulation time 3945825856 ps
CPU time 5.23 seconds
Started Mar 21 12:44:11 PM PDT 24
Finished Mar 21 12:44:17 PM PDT 24
Peak memory 217260 kb
Host smart-9c3cf89a-2927-4977-bd1e-7e532410374c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997427644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.1997427644
Directory /workspace/0.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all.1968028443
Short name T255
Test name
Test status
Simulation time 370083837780 ps
CPU time 244.77 seconds
Started Mar 21 12:44:32 PM PDT 24
Finished Mar 21 12:48:37 PM PDT 24
Peak memory 201804 kb
Host smart-a72f6cc6-fdd6-4fc3-8ea4-544db301283c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968028443 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.
1968028443
Directory /workspace/9.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.adc_ctrl_clock_gating.2328973102
Short name T5
Test name
Test status
Simulation time 332270161851 ps
CPU time 686.4 seconds
Started Mar 21 12:44:36 PM PDT 24
Finished Mar 21 12:56:02 PM PDT 24
Peak memory 201696 kb
Host smart-c8090a9e-df8e-492a-9415-70350baebec5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328973102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gat
ing.2328973102
Directory /workspace/11.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup.66175600
Short name T146
Test name
Test status
Simulation time 352133273447 ps
CPU time 199.05 seconds
Started Mar 21 12:45:37 PM PDT 24
Finished Mar 21 12:48:56 PM PDT 24
Peak memory 201808 kb
Host smart-08cad84b-e277-4a49-8fd2-118b0223a642
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66175600 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_
wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_w
akeup.66175600
Directory /workspace/26.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup.594013930
Short name T125
Test name
Test status
Simulation time 526160184692 ps
CPU time 654.92 seconds
Started Mar 21 12:44:59 PM PDT 24
Finished Mar 21 12:55:55 PM PDT 24
Peak memory 201696 kb
Host smart-9fe61134-44d1-4a64-9440-47d5a90463e2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594013930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_
wakeup.594013930
Directory /workspace/21.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_both.3393052008
Short name T277
Test name
Test status
Simulation time 527473662140 ps
CPU time 234.5 seconds
Started Mar 21 12:44:49 PM PDT 24
Finished Mar 21 12:48:43 PM PDT 24
Peak memory 201716 kb
Host smart-b06381ab-c742-448e-91fa-2e2795732e9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393052008 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.3393052008
Directory /workspace/14.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.268151657
Short name T47
Test name
Test status
Simulation time 236801505202 ps
CPU time 293.89 seconds
Started Mar 21 12:44:12 PM PDT 24
Finished Mar 21 12:49:06 PM PDT 24
Peak memory 218680 kb
Host smart-c8249e86-beda-4f4d-8702-504aff82fe2f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268151657 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all_with_rand_reset.268151657
Directory /workspace/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.1218623894
Short name T827
Test name
Test status
Simulation time 8234367329 ps
CPU time 19.72 seconds
Started Mar 21 12:37:56 PM PDT 24
Finished Mar 21 12:38:18 PM PDT 24
Peak memory 201800 kb
Host smart-3ba2a036-55da-4304-ad74-981d032b5a04
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218623894 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_in
tg_err.1218623894
Directory /workspace/9.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all.3977999828
Short name T303
Test name
Test status
Simulation time 366814523380 ps
CPU time 367.9 seconds
Started Mar 21 12:45:12 PM PDT 24
Finished Mar 21 12:51:20 PM PDT 24
Peak memory 201696 kb
Host smart-1efa69f8-b88f-45e3-b893-b521c8f5d84c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977999828 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all
.3977999828
Directory /workspace/24.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_both.809971099
Short name T275
Test name
Test status
Simulation time 353657436012 ps
CPU time 827.35 seconds
Started Mar 21 12:45:12 PM PDT 24
Finished Mar 21 12:59:00 PM PDT 24
Peak memory 201712 kb
Host smart-2cf3b013-bc0b-4969-beae-6f08f311be0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809971099 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.809971099
Directory /workspace/25.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/34.adc_ctrl_clock_gating.2411452822
Short name T126
Test name
Test status
Simulation time 329535222698 ps
CPU time 89 seconds
Started Mar 21 12:46:06 PM PDT 24
Finished Mar 21 12:47:35 PM PDT 24
Peak memory 201812 kb
Host smart-a9318af6-b734-47ae-97d5-0623127c61c2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411452822 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gat
ing.2411452822
Directory /workspace/34.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup.2998700731
Short name T225
Test name
Test status
Simulation time 529851836055 ps
CPU time 1182.98 seconds
Started Mar 21 12:44:22 PM PDT 24
Finished Mar 21 01:04:05 PM PDT 24
Peak memory 202084 kb
Host smart-4f445faa-f6b8-4a43-9074-e8ad5787cfff
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998700731 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_
wakeup.2998700731
Directory /workspace/6.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled.1419889421
Short name T48
Test name
Test status
Simulation time 483653539060 ps
CPU time 1089.73 seconds
Started Mar 21 12:45:03 PM PDT 24
Finished Mar 21 01:03:13 PM PDT 24
Peak memory 201744 kb
Host smart-4c40fecf-8be8-44a5-8991-54cb9be32ce9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419889421 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.1419889421
Directory /workspace/20.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all.1814427199
Short name T285
Test name
Test status
Simulation time 425768721679 ps
CPU time 689.68 seconds
Started Mar 21 12:44:59 PM PDT 24
Finished Mar 21 12:56:29 PM PDT 24
Peak memory 210184 kb
Host smart-50e00147-43e7-4e5c-b488-7c8af7773656
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814427199 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all
.1814427199
Directory /workspace/21.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all.27365468
Short name T52
Test name
Test status
Simulation time 610609506639 ps
CPU time 1662.24 seconds
Started Mar 21 12:44:08 PM PDT 24
Finished Mar 21 01:11:50 PM PDT 24
Peak memory 213280 kb
Host smart-33008b4d-b552-4bb8-8d91-ff683361185e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27365468 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all.27365468
Directory /workspace/3.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.adc_ctrl_clock_gating.4008788281
Short name T227
Test name
Test status
Simulation time 329583814912 ps
CPU time 509.96 seconds
Started Mar 21 12:44:51 PM PDT 24
Finished Mar 21 12:53:21 PM PDT 24
Peak memory 201824 kb
Host smart-1e1d88e9-c5d9-4de2-bb49-70af42edcab3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008788281 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gat
ing.4008788281
Directory /workspace/14.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt.889310703
Short name T180
Test name
Test status
Simulation time 483629572681 ps
CPU time 188.12 seconds
Started Mar 21 12:44:36 PM PDT 24
Finished Mar 21 12:47:44 PM PDT 24
Peak memory 201768 kb
Host smart-afc9a0ba-e84d-4f74-a507-5d96060103bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889310703 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.889310703
Directory /workspace/11.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/33.adc_ctrl_clock_gating.2198162001
Short name T256
Test name
Test status
Simulation time 329342243975 ps
CPU time 61.11 seconds
Started Mar 21 12:46:11 PM PDT 24
Finished Mar 21 12:47:13 PM PDT 24
Peak memory 201716 kb
Host smart-a7cd5908-bab2-43c5-b668-f97cc9e513d6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198162001 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gat
ing.2198162001
Directory /workspace/33.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt_fixed.3513621396
Short name T175
Test name
Test status
Simulation time 167686012305 ps
CPU time 105.29 seconds
Started Mar 21 12:44:37 PM PDT 24
Finished Mar 21 12:46:22 PM PDT 24
Peak memory 201916 kb
Host smart-c6aedd8d-1646-4193-b2cf-73f58f1148f1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513621396 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interru
pt_fixed.3513621396
Directory /workspace/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_both.600528188
Short name T15
Test name
Test status
Simulation time 436232806721 ps
CPU time 791.89 seconds
Started Mar 21 12:46:43 PM PDT 24
Finished Mar 21 12:59:57 PM PDT 24
Peak memory 201780 kb
Host smart-656e63ae-cbfb-4c56-a0af-db67f3150147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600528188 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.600528188
Directory /workspace/37.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup.4093069242
Short name T30
Test name
Test status
Simulation time 564510444659 ps
CPU time 444.73 seconds
Started Mar 21 12:44:45 PM PDT 24
Finished Mar 21 12:52:10 PM PDT 24
Peak memory 202008 kb
Host smart-3db36fb1-2c37-470a-9159-469acd45bbc6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093069242 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters
_wakeup.4093069242
Directory /workspace/15.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_both.631808771
Short name T11
Test name
Test status
Simulation time 449972531942 ps
CPU time 507.9 seconds
Started Mar 21 12:45:55 PM PDT 24
Finished Mar 21 12:54:23 PM PDT 24
Peak memory 201720 kb
Host smart-61031a7d-d3d0-42ba-9c0b-44754bf59d1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631808771 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.631808771
Directory /workspace/32.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all.1663329995
Short name T162
Test name
Test status
Simulation time 432477101493 ps
CPU time 522.6 seconds
Started Mar 21 12:44:21 PM PDT 24
Finished Mar 21 12:53:04 PM PDT 24
Peak memory 210232 kb
Host smart-4f94c38f-7f1c-41aa-b599-5caae73fa1f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663329995 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.
1663329995
Directory /workspace/5.adc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.3593534498
Short name T107
Test name
Test status
Simulation time 446429169 ps
CPU time 1.08 seconds
Started Mar 21 12:37:42 PM PDT 24
Finished Mar 21 12:37:43 PM PDT 24
Peak memory 201704 kb
Host smart-ddbdd060-6016-4d71-9bb8-147f26e8d10e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593534498 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.3593534498
Directory /workspace/0.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup.3967070374
Short name T228
Test name
Test status
Simulation time 556155862718 ps
CPU time 224.64 seconds
Started Mar 21 12:44:58 PM PDT 24
Finished Mar 21 12:48:44 PM PDT 24
Peak memory 201788 kb
Host smart-09feb994-41af-4c0b-ba7e-4f853bdc297d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967070374 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters
_wakeup.3967070374
Directory /workspace/20.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt.3627530595
Short name T197
Test name
Test status
Simulation time 492722077290 ps
CPU time 1192.33 seconds
Started Mar 21 12:45:33 PM PDT 24
Finished Mar 21 01:05:26 PM PDT 24
Peak memory 201796 kb
Host smart-2e457ae5-2833-44d4-970f-322486bdecfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627530595 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.3627530595
Directory /workspace/27.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/36.adc_ctrl_clock_gating.2372753422
Short name T243
Test name
Test status
Simulation time 536051234236 ps
CPU time 929.96 seconds
Started Mar 21 12:46:31 PM PDT 24
Finished Mar 21 01:02:02 PM PDT 24
Peak memory 201728 kb
Host smart-d042ef73-8502-4cb7-9bd5-fa4a765269bd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372753422 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gat
ing.2372753422
Directory /workspace/36.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt.1208648056
Short name T234
Test name
Test status
Simulation time 480461076027 ps
CPU time 1106.52 seconds
Started Mar 21 12:44:07 PM PDT 24
Finished Mar 21 01:02:34 PM PDT 24
Peak memory 201732 kb
Host smart-350a6a70-300c-4816-a2ab-9718f40bce75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208648056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.1208648056
Directory /workspace/0.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt.1421754693
Short name T149
Test name
Test status
Simulation time 494170145152 ps
CPU time 1147.47 seconds
Started Mar 21 12:44:08 PM PDT 24
Finished Mar 21 01:03:16 PM PDT 24
Peak memory 201868 kb
Host smart-9229abe0-585d-4d10-809c-43537d3eb66a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421754693 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.1421754693
Directory /workspace/1.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.2655912015
Short name T190
Test name
Test status
Simulation time 1120262979241 ps
CPU time 559.47 seconds
Started Mar 21 12:46:00 PM PDT 24
Finished Mar 21 12:55:20 PM PDT 24
Peak memory 210684 kb
Host smart-c055fb38-6d17-40d9-b233-3843dfdd3da0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655912015 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all_with_rand_reset.2655912015
Directory /workspace/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_clock_gating.2442911119
Short name T315
Test name
Test status
Simulation time 176391846509 ps
CPU time 97.67 seconds
Started Mar 21 12:46:52 PM PDT 24
Finished Mar 21 12:48:30 PM PDT 24
Peak memory 202176 kb
Host smart-fa894415-6f1f-47fa-b934-05173eeee7e8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442911119 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gat
ing.2442911119
Directory /workspace/40.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_fsm_reset.4255039342
Short name T50
Test name
Test status
Simulation time 82377886905 ps
CPU time 269.83 seconds
Started Mar 21 12:47:13 PM PDT 24
Finished Mar 21 12:51:43 PM PDT 24
Peak memory 202092 kb
Host smart-2a4f5436-547b-4c07-9770-4155a465c0c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255039342 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.4255039342
Directory /workspace/42.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all.2110110846
Short name T224
Test name
Test status
Simulation time 278243423383 ps
CPU time 989.65 seconds
Started Mar 21 12:47:31 PM PDT 24
Finished Mar 21 01:04:00 PM PDT 24
Peak memory 202032 kb
Host smart-b0202165-ee79-405e-96e2-152513928948
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110110846 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all
.2110110846
Directory /workspace/45.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup.2751544434
Short name T254
Test name
Test status
Simulation time 205685816504 ps
CPU time 494.95 seconds
Started Mar 21 12:44:34 PM PDT 24
Finished Mar 21 12:52:50 PM PDT 24
Peak memory 201852 kb
Host smart-da7020fb-10ee-4b54-aec6-db0df0484161
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751544434 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters
_wakeup.2751544434
Directory /workspace/11.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.2218806322
Short name T257
Test name
Test status
Simulation time 129909413215 ps
CPU time 181.42 seconds
Started Mar 21 12:44:35 PM PDT 24
Finished Mar 21 12:47:37 PM PDT 24
Peak memory 210268 kb
Host smart-d19310a8-c3a8-47e1-8cff-9e636c4db2ba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218806322 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all_with_rand_reset.2218806322
Directory /workspace/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled.3613847114
Short name T259
Test name
Test status
Simulation time 485806349480 ps
CPU time 1157.48 seconds
Started Mar 21 12:45:29 PM PDT 24
Finished Mar 21 01:04:47 PM PDT 24
Peak memory 201708 kb
Host smart-da2c9a5c-060e-4407-9453-af87dc6eb7b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613847114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.3613847114
Directory /workspace/26.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt.2471723653
Short name T247
Test name
Test status
Simulation time 326145038095 ps
CPU time 356.82 seconds
Started Mar 21 12:45:59 PM PDT 24
Finished Mar 21 12:51:55 PM PDT 24
Peak memory 201704 kb
Host smart-bccb713e-c000-4080-8f8f-25b19001c5de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471723653 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.2471723653
Directory /workspace/30.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/31.adc_ctrl_fsm_reset.360951053
Short name T212
Test name
Test status
Simulation time 104815192340 ps
CPU time 443.3 seconds
Started Mar 21 12:45:55 PM PDT 24
Finished Mar 21 12:53:18 PM PDT 24
Peak memory 202072 kb
Host smart-35120ce2-7f69-4013-9715-50c02f980a8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360951053 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.360951053
Directory /workspace/31.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup.2340273047
Short name T271
Test name
Test status
Simulation time 181966082731 ps
CPU time 98.74 seconds
Started Mar 21 12:44:28 PM PDT 24
Finished Mar 21 12:46:07 PM PDT 24
Peak memory 201868 kb
Host smart-72d8a099-ca3e-477c-bb53-fe2b7ddf7ea2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340273047 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_
wakeup.2340273047
Directory /workspace/8.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_both.2042323862
Short name T298
Test name
Test status
Simulation time 497405503107 ps
CPU time 617.41 seconds
Started Mar 21 12:44:36 PM PDT 24
Finished Mar 21 12:54:53 PM PDT 24
Peak memory 201712 kb
Host smart-4bd815b3-ba7a-42dc-bc0e-f46a00ee1732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042323862 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.2042323862
Directory /workspace/11.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_both.2223192497
Short name T150
Test name
Test status
Simulation time 502089372460 ps
CPU time 272 seconds
Started Mar 21 12:44:50 PM PDT 24
Finished Mar 21 12:49:23 PM PDT 24
Peak memory 201696 kb
Host smart-19cf0a27-359c-4f48-a43a-c0df9813f350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223192497 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.2223192497
Directory /workspace/15.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/16.adc_ctrl_fsm_reset.2701120171
Short name T705
Test name
Test status
Simulation time 136958724073 ps
CPU time 437.69 seconds
Started Mar 21 12:44:51 PM PDT 24
Finished Mar 21 12:52:09 PM PDT 24
Peak memory 202176 kb
Host smart-cb5d5ee3-c75b-4744-a627-3a4690b57aff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701120171 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.2701120171
Directory /workspace/16.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt.1617000500
Short name T143
Test name
Test status
Simulation time 167873105507 ps
CPU time 418.96 seconds
Started Mar 21 12:46:31 PM PDT 24
Finished Mar 21 12:53:30 PM PDT 24
Peak memory 201800 kb
Host smart-3b887bb2-07b9-4676-a0f9-b2f6daae37b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617000500 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.1617000500
Directory /workspace/37.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled.2080068157
Short name T297
Test name
Test status
Simulation time 335655848194 ps
CPU time 694.15 seconds
Started Mar 21 12:44:22 PM PDT 24
Finished Mar 21 12:55:56 PM PDT 24
Peak memory 201736 kb
Host smart-9f5c22d5-6ecc-42d0-b6fb-1196927393c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080068157 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.2080068157
Directory /workspace/6.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.732923757
Short name T69
Test name
Test status
Simulation time 1619424110 ps
CPU time 3.09 seconds
Started Mar 21 12:37:46 PM PDT 24
Finished Mar 21 12:37:49 PM PDT 24
Peak memory 201876 kb
Host smart-8d73fc73-264f-4ba9-aefd-0264ec6d7ece
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732923757 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.732923757
Directory /workspace/0.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.720182728
Short name T319
Test name
Test status
Simulation time 4321433832 ps
CPU time 11.89 seconds
Started Mar 21 12:37:57 PM PDT 24
Finished Mar 21 12:38:10 PM PDT 24
Peak memory 201864 kb
Host smart-6ac84a7b-e84a-4b07-9797-3a4c19f5539c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720182728 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_int
g_err.720182728
Directory /workspace/0.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.390964280
Short name T807
Test name
Test status
Simulation time 8578681287 ps
CPU time 4.58 seconds
Started Mar 21 12:37:56 PM PDT 24
Finished Mar 21 12:38:02 PM PDT 24
Peak memory 201812 kb
Host smart-b43e6a60-baca-4b4b-b7a3-35b582511c67
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390964280 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_in
tg_err.390964280
Directory /workspace/11.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup.2207520824
Short name T240
Test name
Test status
Simulation time 556716864089 ps
CPU time 1215.86 seconds
Started Mar 21 12:44:36 PM PDT 24
Finished Mar 21 01:04:52 PM PDT 24
Peak memory 201716 kb
Host smart-132bb88d-2ad9-41f1-8a78-2121401af6bf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207520824 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters
_wakeup.2207520824
Directory /workspace/10.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt.1696780709
Short name T138
Test name
Test status
Simulation time 497156734645 ps
CPU time 1126.73 seconds
Started Mar 21 12:44:34 PM PDT 24
Finished Mar 21 01:03:21 PM PDT 24
Peak memory 201784 kb
Host smart-fbe87e93-1cf4-4409-a17d-31d8315851c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696780709 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.1696780709
Directory /workspace/12.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.1785203715
Short name T83
Test name
Test status
Simulation time 79547112864 ps
CPU time 141.54 seconds
Started Mar 21 12:44:50 PM PDT 24
Finished Mar 21 12:47:12 PM PDT 24
Peak memory 210040 kb
Host smart-ed075b80-1edf-4972-b494-9e43e4043332
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785203715 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all_with_rand_reset.1785203715
Directory /workspace/15.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_both.1979604235
Short name T189
Test name
Test status
Simulation time 340245798809 ps
CPU time 221.1 seconds
Started Mar 21 12:44:53 PM PDT 24
Finished Mar 21 12:48:35 PM PDT 24
Peak memory 201824 kb
Host smart-77177d58-5e8d-4a4e-960a-966a4652d262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979604235 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.1979604235
Directory /workspace/19.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all.3412066020
Short name T205
Test name
Test status
Simulation time 781739738736 ps
CPU time 1321.08 seconds
Started Mar 21 12:45:00 PM PDT 24
Finished Mar 21 01:07:02 PM PDT 24
Peak memory 210224 kb
Host smart-8e9e00dd-558f-4161-90fe-3b67962f0372
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412066020 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all
.3412066020
Directory /workspace/19.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.adc_ctrl_clock_gating.296739850
Short name T316
Test name
Test status
Simulation time 325702790469 ps
CPU time 201.57 seconds
Started Mar 21 12:45:11 PM PDT 24
Finished Mar 21 12:48:33 PM PDT 24
Peak memory 201692 kb
Host smart-93a9cd81-8ebd-4d30-9261-79bebbf84e8c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296739850 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gati
ng.296739850
Directory /workspace/22.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/22.adc_ctrl_fsm_reset.1900530912
Short name T219
Test name
Test status
Simulation time 115749982658 ps
CPU time 459.62 seconds
Started Mar 21 12:45:15 PM PDT 24
Finished Mar 21 12:52:55 PM PDT 24
Peak memory 201104 kb
Host smart-6cb92365-2fd5-4422-a185-901a1e09828b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900530912 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.1900530912
Directory /workspace/22.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup.1819150456
Short name T188
Test name
Test status
Simulation time 545329090071 ps
CPU time 68.81 seconds
Started Mar 21 12:45:43 PM PDT 24
Finished Mar 21 12:46:52 PM PDT 24
Peak memory 201720 kb
Host smart-864b2463-4ddb-409c-ba66-35809981f421
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819150456 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters
_wakeup.1819150456
Directory /workspace/29.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_both.3391463371
Short name T263
Test name
Test status
Simulation time 170776043667 ps
CPU time 66.52 seconds
Started Mar 21 12:44:23 PM PDT 24
Finished Mar 21 12:45:30 PM PDT 24
Peak memory 201688 kb
Host smart-0fc17ed2-bdde-4fd6-8930-0f7876f1a5c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391463371 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.3391463371
Directory /workspace/3.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/34.adc_ctrl_fsm_reset.3148089812
Short name T216
Test name
Test status
Simulation time 105166612612 ps
CPU time 461.35 seconds
Started Mar 21 12:46:17 PM PDT 24
Finished Mar 21 12:53:59 PM PDT 24
Peak memory 202028 kb
Host smart-0a84c2fc-595f-499c-8db3-8906e0723763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148089812 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.3148089812
Directory /workspace/34.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all.4256987518
Short name T214
Test name
Test status
Simulation time 237243275294 ps
CPU time 884.4 seconds
Started Mar 21 12:46:19 PM PDT 24
Finished Mar 21 01:01:04 PM PDT 24
Peak memory 202008 kb
Host smart-f2c1e6e0-58cb-4074-a9a9-dcaad7456578
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256987518 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all
.4256987518
Directory /workspace/34.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt.613083911
Short name T294
Test name
Test status
Simulation time 497621359381 ps
CPU time 199.12 seconds
Started Mar 21 12:46:19 PM PDT 24
Finished Mar 21 12:49:38 PM PDT 24
Peak memory 201760 kb
Host smart-2da5330d-9e8c-4abf-8099-efff0e055ce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613083911 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.613083911
Directory /workspace/35.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.1970045753
Short name T18
Test name
Test status
Simulation time 164362231904 ps
CPU time 148.71 seconds
Started Mar 21 12:46:19 PM PDT 24
Finished Mar 21 12:48:47 PM PDT 24
Peak memory 210476 kb
Host smart-944af0e8-bef2-4e51-8151-5bb2720a59f0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970045753 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all_with_rand_reset.1970045753
Directory /workspace/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_fsm_reset.289371979
Short name T327
Test name
Test status
Simulation time 108961569499 ps
CPU time 459.01 seconds
Started Mar 21 12:47:52 PM PDT 24
Finished Mar 21 12:55:31 PM PDT 24
Peak memory 202008 kb
Host smart-7db4c319-72f9-41af-b4c2-f2017e45a964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289371979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.289371979
Directory /workspace/47.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_both.1189043269
Short name T223
Test name
Test status
Simulation time 354386311787 ps
CPU time 220.2 seconds
Started Mar 21 12:44:21 PM PDT 24
Finished Mar 21 12:48:01 PM PDT 24
Peak memory 201800 kb
Host smart-b43530cd-1287-4ab2-ba70-8ccd9d3e85be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189043269 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.1189043269
Directory /workspace/5.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup.386363149
Short name T273
Test name
Test status
Simulation time 169745565822 ps
CPU time 201.49 seconds
Started Mar 21 12:44:21 PM PDT 24
Finished Mar 21 12:47:42 PM PDT 24
Peak memory 201796 kb
Host smart-fb6efbec-344f-4679-a518-c14488e1299c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386363149 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_w
akeup.386363149
Directory /workspace/7.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.314083329
Short name T111
Test name
Test status
Simulation time 1209949522 ps
CPU time 3.14 seconds
Started Mar 21 12:37:41 PM PDT 24
Finished Mar 21 12:37:45 PM PDT 24
Peak memory 201796 kb
Host smart-59c51303-6cf4-4372-893c-b99ba85c52da
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314083329 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_alias
ing.314083329
Directory /workspace/0.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.1614251713
Short name T117
Test name
Test status
Simulation time 43965308510 ps
CPU time 54.96 seconds
Started Mar 21 12:37:40 PM PDT 24
Finished Mar 21 12:38:35 PM PDT 24
Peak memory 201916 kb
Host smart-382b0c0f-dce1-4f8d-8a7e-5df5d2907c76
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614251713 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_
bash.1614251713
Directory /workspace/0.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.3863210867
Short name T898
Test name
Test status
Simulation time 1493155659 ps
CPU time 4.17 seconds
Started Mar 21 12:37:48 PM PDT 24
Finished Mar 21 12:37:52 PM PDT 24
Peak memory 201604 kb
Host smart-02820518-1f4f-4074-bd86-219856887948
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863210867 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_r
eset.3863210867
Directory /workspace/0.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.3056152178
Short name T801
Test name
Test status
Simulation time 591581322 ps
CPU time 1.04 seconds
Started Mar 21 12:37:36 PM PDT 24
Finished Mar 21 12:37:37 PM PDT 24
Peak memory 201668 kb
Host smart-aee1ddd2-cecf-4354-a498-137c45bc9506
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056152178 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.adc_ctrl_csr_mem_rw_with_rand_reset.3056152178
Directory /workspace/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.2352574086
Short name T803
Test name
Test status
Simulation time 418388291 ps
CPU time 1.74 seconds
Started Mar 21 12:37:48 PM PDT 24
Finished Mar 21 12:37:50 PM PDT 24
Peak memory 201596 kb
Host smart-ad02b48b-a7e8-4ace-a91f-0e5a9f9a2c8b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352574086 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.2352574086
Directory /workspace/0.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.924861711
Short name T889
Test name
Test status
Simulation time 5339321987 ps
CPU time 6.79 seconds
Started Mar 21 12:37:29 PM PDT 24
Finished Mar 21 12:37:36 PM PDT 24
Peak memory 201936 kb
Host smart-c4f1a5fa-596e-4a30-abb6-bcd4b8c2c4c7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924861711 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ct
rl_same_csr_outstanding.924861711
Directory /workspace/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.4136529083
Short name T839
Test name
Test status
Simulation time 955380983 ps
CPU time 1.8 seconds
Started Mar 21 12:37:32 PM PDT 24
Finished Mar 21 12:37:36 PM PDT 24
Peak memory 201784 kb
Host smart-35859220-4930-4cce-ac56-4cde52aecc42
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136529083 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_alia
sing.4136529083
Directory /workspace/1.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.539638513
Short name T114
Test name
Test status
Simulation time 33382010569 ps
CPU time 34.36 seconds
Started Mar 21 12:37:32 PM PDT 24
Finished Mar 21 12:38:06 PM PDT 24
Peak memory 201888 kb
Host smart-8143a69d-593e-4374-80a4-760dce1a2a36
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539638513 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_b
ash.539638513
Directory /workspace/1.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.1207710650
Short name T829
Test name
Test status
Simulation time 1093648929 ps
CPU time 2.12 seconds
Started Mar 21 12:37:47 PM PDT 24
Finished Mar 21 12:37:49 PM PDT 24
Peak memory 201604 kb
Host smart-6906bb43-8202-4e3e-9e49-7df79d143005
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207710650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_r
eset.1207710650
Directory /workspace/1.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.3050106364
Short name T911
Test name
Test status
Simulation time 507212914 ps
CPU time 1.37 seconds
Started Mar 21 12:37:48 PM PDT 24
Finished Mar 21 12:37:50 PM PDT 24
Peak memory 201664 kb
Host smart-2e7f7258-1514-44b9-ba48-9c0842d652bc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050106364 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.adc_ctrl_csr_mem_rw_with_rand_reset.3050106364
Directory /workspace/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.1962265685
Short name T837
Test name
Test status
Simulation time 450327130 ps
CPU time 1.79 seconds
Started Mar 21 12:37:39 PM PDT 24
Finished Mar 21 12:37:41 PM PDT 24
Peak memory 201600 kb
Host smart-ac60c0c5-855a-437a-9607-7f2b46f5775a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962265685 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.1962265685
Directory /workspace/1.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.2259143034
Short name T851
Test name
Test status
Simulation time 344359768 ps
CPU time 1.38 seconds
Started Mar 21 12:37:51 PM PDT 24
Finished Mar 21 12:37:53 PM PDT 24
Peak memory 201604 kb
Host smart-dc66f455-85c9-456d-8cb7-108850c886fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259143034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.2259143034
Directory /workspace/1.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.4098078722
Short name T820
Test name
Test status
Simulation time 4633347549 ps
CPU time 13.28 seconds
Started Mar 21 12:37:39 PM PDT 24
Finished Mar 21 12:37:53 PM PDT 24
Peak memory 201892 kb
Host smart-5d96b88a-0479-4143-8871-c04c71a1c122
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098078722 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_c
trl_same_csr_outstanding.4098078722
Directory /workspace/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.1331626578
Short name T71
Test name
Test status
Simulation time 495484449 ps
CPU time 1.52 seconds
Started Mar 21 12:37:50 PM PDT 24
Finished Mar 21 12:37:51 PM PDT 24
Peak memory 201832 kb
Host smart-2f6a5907-c9ce-4d03-be44-5df83fbe4c46
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331626578 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.1331626578
Directory /workspace/1.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.691642099
Short name T321
Test name
Test status
Simulation time 8383022000 ps
CPU time 19.87 seconds
Started Mar 21 12:37:47 PM PDT 24
Finished Mar 21 12:38:07 PM PDT 24
Peak memory 201892 kb
Host smart-0d29b4d1-4ddc-4488-965e-3e687c5d27ca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691642099 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_int
g_err.691642099
Directory /workspace/1.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.454439745
Short name T880
Test name
Test status
Simulation time 516540794 ps
CPU time 1.17 seconds
Started Mar 21 12:37:49 PM PDT 24
Finished Mar 21 12:37:51 PM PDT 24
Peak memory 201776 kb
Host smart-75e491f1-bb7b-4dec-94ec-a7ef5ad47296
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454439745 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.adc_ctrl_csr_mem_rw_with_rand_reset.454439745
Directory /workspace/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.1186291993
Short name T112
Test name
Test status
Simulation time 419212080 ps
CPU time 1.74 seconds
Started Mar 21 12:37:48 PM PDT 24
Finished Mar 21 12:37:50 PM PDT 24
Peak memory 201628 kb
Host smart-51c63167-a32f-429c-9042-4685367bac35
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186291993 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.1186291993
Directory /workspace/10.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.720831112
Short name T795
Test name
Test status
Simulation time 392170566 ps
CPU time 1.56 seconds
Started Mar 21 12:37:35 PM PDT 24
Finished Mar 21 12:37:38 PM PDT 24
Peak memory 201572 kb
Host smart-abf2be90-c637-4d62-9d51-d0f854e89eb7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720831112 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.720831112
Directory /workspace/10.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.1551150687
Short name T121
Test name
Test status
Simulation time 5196610524 ps
CPU time 6 seconds
Started Mar 21 12:37:45 PM PDT 24
Finished Mar 21 12:37:51 PM PDT 24
Peak memory 201880 kb
Host smart-0a7d72c4-f5e2-4cd2-b61f-2250363c42d4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551150687 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_
ctrl_same_csr_outstanding.1551150687
Directory /workspace/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.256473227
Short name T72
Test name
Test status
Simulation time 388025128 ps
CPU time 2.7 seconds
Started Mar 21 12:37:43 PM PDT 24
Finished Mar 21 12:37:46 PM PDT 24
Peak memory 218200 kb
Host smart-a9da64a8-2fc0-40d4-b25f-8b95dc3f5608
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256473227 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.256473227
Directory /workspace/10.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.1096486349
Short name T320
Test name
Test status
Simulation time 7679209400 ps
CPU time 12.17 seconds
Started Mar 21 12:37:59 PM PDT 24
Finished Mar 21 12:38:11 PM PDT 24
Peak memory 202044 kb
Host smart-78072743-deca-40b4-92de-356dd13d8155
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096486349 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_i
ntg_err.1096486349
Directory /workspace/10.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.3077972431
Short name T66
Test name
Test status
Simulation time 552569881 ps
CPU time 2.36 seconds
Started Mar 21 12:37:50 PM PDT 24
Finished Mar 21 12:37:52 PM PDT 24
Peak memory 201672 kb
Host smart-b2d4391f-8750-4d0a-90cc-cfb1068a6bc7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077972431 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.adc_ctrl_csr_mem_rw_with_rand_reset.3077972431
Directory /workspace/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.1333758519
Short name T120
Test name
Test status
Simulation time 598124377 ps
CPU time 0.94 seconds
Started Mar 21 12:37:58 PM PDT 24
Finished Mar 21 12:37:59 PM PDT 24
Peak memory 201600 kb
Host smart-baf64cf7-3e98-4b30-8950-14cea01bbb9f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333758519 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.1333758519
Directory /workspace/11.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.2261877967
Short name T917
Test name
Test status
Simulation time 449370671 ps
CPU time 0.91 seconds
Started Mar 21 12:37:53 PM PDT 24
Finished Mar 21 12:37:54 PM PDT 24
Peak memory 201572 kb
Host smart-d74312fc-04b2-46f6-9448-c731265938fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261877967 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.2261877967
Directory /workspace/11.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.2009330954
Short name T879
Test name
Test status
Simulation time 4906845437 ps
CPU time 8.91 seconds
Started Mar 21 12:37:53 PM PDT 24
Finished Mar 21 12:38:02 PM PDT 24
Peak memory 201904 kb
Host smart-0705bc87-e3e5-4800-a8ea-cda72e8165d4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009330954 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_
ctrl_same_csr_outstanding.2009330954
Directory /workspace/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.3319788344
Short name T67
Test name
Test status
Simulation time 469886958 ps
CPU time 1.83 seconds
Started Mar 21 12:37:46 PM PDT 24
Finished Mar 21 12:37:48 PM PDT 24
Peak memory 201840 kb
Host smart-33c88f79-7105-44d5-bbc9-975d628c6fd3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319788344 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.3319788344
Directory /workspace/11.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.26794710
Short name T68
Test name
Test status
Simulation time 636121472 ps
CPU time 2.36 seconds
Started Mar 21 12:37:57 PM PDT 24
Finished Mar 21 12:38:00 PM PDT 24
Peak memory 201660 kb
Host smart-12470274-31e1-45b1-a8a7-055a75ba31b6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26794710 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 12.adc_ctrl_csr_mem_rw_with_rand_reset.26794710
Directory /workspace/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.4252912557
Short name T847
Test name
Test status
Simulation time 500326579 ps
CPU time 1.04 seconds
Started Mar 21 12:37:49 PM PDT 24
Finished Mar 21 12:37:50 PM PDT 24
Peak memory 201768 kb
Host smart-a0734ef7-4147-4b74-9b15-65fa08cfa8c7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252912557 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.4252912557
Directory /workspace/12.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.2006862514
Short name T894
Test name
Test status
Simulation time 557109551 ps
CPU time 0.95 seconds
Started Mar 21 12:37:50 PM PDT 24
Finished Mar 21 12:37:51 PM PDT 24
Peak memory 201588 kb
Host smart-ff95413a-8cd5-4f16-b513-452507b650df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006862514 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.2006862514
Directory /workspace/12.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.1655922617
Short name T857
Test name
Test status
Simulation time 2791823059 ps
CPU time 1.82 seconds
Started Mar 21 12:37:47 PM PDT 24
Finished Mar 21 12:37:49 PM PDT 24
Peak memory 201716 kb
Host smart-cb7c4432-2fa0-4818-b082-e34c0d226926
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655922617 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_
ctrl_same_csr_outstanding.1655922617
Directory /workspace/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.3585310167
Short name T850
Test name
Test status
Simulation time 423241025 ps
CPU time 2.24 seconds
Started Mar 21 12:37:49 PM PDT 24
Finished Mar 21 12:37:51 PM PDT 24
Peak memory 201856 kb
Host smart-a678879e-979a-4dd8-99d2-7e130bc487d6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585310167 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.3585310167
Directory /workspace/12.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.1307046092
Short name T872
Test name
Test status
Simulation time 8483327330 ps
CPU time 8.02 seconds
Started Mar 21 12:37:43 PM PDT 24
Finished Mar 21 12:37:51 PM PDT 24
Peak memory 201940 kb
Host smart-bb632d34-963d-4108-be04-90988a324125
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307046092 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_i
ntg_err.1307046092
Directory /workspace/12.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.1236615889
Short name T868
Test name
Test status
Simulation time 585628012 ps
CPU time 1.28 seconds
Started Mar 21 12:37:53 PM PDT 24
Finished Mar 21 12:37:55 PM PDT 24
Peak memory 201772 kb
Host smart-c0887696-8ec1-4e07-8563-d5bf50ee98e6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236615889 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.adc_ctrl_csr_mem_rw_with_rand_reset.1236615889
Directory /workspace/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.1567374997
Short name T841
Test name
Test status
Simulation time 475843993 ps
CPU time 1.82 seconds
Started Mar 21 12:38:04 PM PDT 24
Finished Mar 21 12:38:06 PM PDT 24
Peak memory 201596 kb
Host smart-408eefec-3feb-42e4-bae8-c4e745260077
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567374997 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.1567374997
Directory /workspace/13.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.304280993
Short name T886
Test name
Test status
Simulation time 408055693 ps
CPU time 1.66 seconds
Started Mar 21 12:37:54 PM PDT 24
Finished Mar 21 12:37:56 PM PDT 24
Peak memory 201616 kb
Host smart-c8de9e54-1a0c-4e4a-b2bc-bcd78de6df1b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304280993 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.304280993
Directory /workspace/13.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.704363848
Short name T856
Test name
Test status
Simulation time 2135015900 ps
CPU time 3.9 seconds
Started Mar 21 12:37:55 PM PDT 24
Finished Mar 21 12:37:59 PM PDT 24
Peak memory 201584 kb
Host smart-b34232e2-aec1-42c6-bad4-185346942813
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704363848 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_c
trl_same_csr_outstanding.704363848
Directory /workspace/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.663258863
Short name T913
Test name
Test status
Simulation time 994334363 ps
CPU time 2.75 seconds
Started Mar 21 12:38:01 PM PDT 24
Finished Mar 21 12:38:04 PM PDT 24
Peak memory 210024 kb
Host smart-4e927770-0b45-4b9c-b90f-361fb341c93b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663258863 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.663258863
Directory /workspace/13.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.1629385585
Short name T912
Test name
Test status
Simulation time 8049696644 ps
CPU time 22.18 seconds
Started Mar 21 12:37:52 PM PDT 24
Finished Mar 21 12:38:14 PM PDT 24
Peak memory 201904 kb
Host smart-a87b4ed9-5cbb-419b-ab25-570849b1b01c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629385585 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_i
ntg_err.1629385585
Directory /workspace/13.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.4083665909
Short name T802
Test name
Test status
Simulation time 485868243 ps
CPU time 1.9 seconds
Started Mar 21 12:37:56 PM PDT 24
Finished Mar 21 12:38:00 PM PDT 24
Peak memory 201636 kb
Host smart-3b31cb5d-92ef-4354-94a1-f234f5bf79a0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083665909 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.adc_ctrl_csr_mem_rw_with_rand_reset.4083665909
Directory /workspace/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.2268601980
Short name T110
Test name
Test status
Simulation time 499211720 ps
CPU time 1.42 seconds
Started Mar 21 12:37:49 PM PDT 24
Finished Mar 21 12:37:50 PM PDT 24
Peak memory 201768 kb
Host smart-65bc75dd-e583-4daf-a409-59aa111477c7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268601980 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.2268601980
Directory /workspace/14.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.3361684624
Short name T826
Test name
Test status
Simulation time 475820599 ps
CPU time 1.6 seconds
Started Mar 21 12:38:01 PM PDT 24
Finished Mar 21 12:38:07 PM PDT 24
Peak memory 201624 kb
Host smart-3a7a9581-38f4-4c1e-99d0-573e176724c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361684624 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.3361684624
Directory /workspace/14.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.1070375113
Short name T56
Test name
Test status
Simulation time 4618732089 ps
CPU time 2.12 seconds
Started Mar 21 12:37:50 PM PDT 24
Finished Mar 21 12:37:52 PM PDT 24
Peak memory 201912 kb
Host smart-b4b2d658-9864-4a92-9746-93d191428074
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070375113 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_
ctrl_same_csr_outstanding.1070375113
Directory /workspace/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.4251627645
Short name T65
Test name
Test status
Simulation time 583900836 ps
CPU time 2.65 seconds
Started Mar 21 12:38:02 PM PDT 24
Finished Mar 21 12:38:05 PM PDT 24
Peak memory 201780 kb
Host smart-724a77e7-e54f-445e-84b8-afa5f945c28c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251627645 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.4251627645
Directory /workspace/14.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.710886532
Short name T318
Test name
Test status
Simulation time 4237154903 ps
CPU time 4.32 seconds
Started Mar 21 12:37:49 PM PDT 24
Finished Mar 21 12:37:54 PM PDT 24
Peak memory 201876 kb
Host smart-d8b01566-2a49-487f-949c-33d1b39b908b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710886532 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_in
tg_err.710886532
Directory /workspace/14.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.3763377674
Short name T899
Test name
Test status
Simulation time 666507627 ps
CPU time 1.06 seconds
Started Mar 21 12:37:56 PM PDT 24
Finished Mar 21 12:37:59 PM PDT 24
Peak memory 201688 kb
Host smart-fba26272-0d5d-486d-9416-e35b0cf8d77b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763377674 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.adc_ctrl_csr_mem_rw_with_rand_reset.3763377674
Directory /workspace/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.588741485
Short name T118
Test name
Test status
Simulation time 499656121 ps
CPU time 1.85 seconds
Started Mar 21 12:37:48 PM PDT 24
Finished Mar 21 12:37:50 PM PDT 24
Peak memory 201628 kb
Host smart-442eb57b-c917-4b6e-9650-2b3e81a6a95e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588741485 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.588741485
Directory /workspace/15.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.441360725
Short name T846
Test name
Test status
Simulation time 388982409 ps
CPU time 0.9 seconds
Started Mar 21 12:37:49 PM PDT 24
Finished Mar 21 12:37:50 PM PDT 24
Peak memory 201880 kb
Host smart-6a3e5c17-5403-452d-bbe6-b2caeadac0ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441360725 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.441360725
Directory /workspace/15.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.621115334
Short name T907
Test name
Test status
Simulation time 2139687544 ps
CPU time 3 seconds
Started Mar 21 12:37:55 PM PDT 24
Finished Mar 21 12:37:58 PM PDT 24
Peak memory 201612 kb
Host smart-e51d9717-5fd0-4693-bffb-253ae977176c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621115334 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_c
trl_same_csr_outstanding.621115334
Directory /workspace/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.2540820677
Short name T58
Test name
Test status
Simulation time 4390225630 ps
CPU time 7.98 seconds
Started Mar 21 12:38:04 PM PDT 24
Finished Mar 21 12:38:12 PM PDT 24
Peak memory 201916 kb
Host smart-7d42e5bd-1faf-4f7a-8080-e343670eebff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540820677 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_i
ntg_err.2540820677
Directory /workspace/15.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.4224901588
Short name T845
Test name
Test status
Simulation time 376637074 ps
CPU time 1.02 seconds
Started Mar 21 12:37:48 PM PDT 24
Finished Mar 21 12:37:49 PM PDT 24
Peak memory 201672 kb
Host smart-64853a3d-14da-47c7-a737-30ac5bd38a11
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224901588 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.adc_ctrl_csr_mem_rw_with_rand_reset.4224901588
Directory /workspace/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.3012147201
Short name T855
Test name
Test status
Simulation time 523707399 ps
CPU time 1.91 seconds
Started Mar 21 12:38:01 PM PDT 24
Finished Mar 21 12:38:03 PM PDT 24
Peak memory 201608 kb
Host smart-ce0c6ce9-3440-4e40-9176-74d02c31a9a5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012147201 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.3012147201
Directory /workspace/16.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.2589230349
Short name T834
Test name
Test status
Simulation time 516870046 ps
CPU time 1.02 seconds
Started Mar 21 12:38:03 PM PDT 24
Finished Mar 21 12:38:04 PM PDT 24
Peak memory 201620 kb
Host smart-66e6d4d1-d985-44e4-8e1a-bfef24282614
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589230349 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.2589230349
Directory /workspace/16.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.3984256855
Short name T877
Test name
Test status
Simulation time 1921925365 ps
CPU time 4.58 seconds
Started Mar 21 12:38:01 PM PDT 24
Finished Mar 21 12:38:06 PM PDT 24
Peak memory 201692 kb
Host smart-45445ad0-2f03-47b1-81c1-d6bce3331f67
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984256855 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_
ctrl_same_csr_outstanding.3984256855
Directory /workspace/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.3022334538
Short name T864
Test name
Test status
Simulation time 459721612 ps
CPU time 3.67 seconds
Started Mar 21 12:38:06 PM PDT 24
Finished Mar 21 12:38:10 PM PDT 24
Peak memory 210108 kb
Host smart-a9376285-2055-4148-9327-3065dab49890
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022334538 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.3022334538
Directory /workspace/16.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.2190151157
Short name T861
Test name
Test status
Simulation time 8868860481 ps
CPU time 7.5 seconds
Started Mar 21 12:37:45 PM PDT 24
Finished Mar 21 12:37:53 PM PDT 24
Peak memory 201912 kb
Host smart-79fd961a-3a51-4fbc-aa5b-a55d2077a29d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190151157 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_i
ntg_err.2190151157
Directory /workspace/16.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.1987517582
Short name T85
Test name
Test status
Simulation time 530239112 ps
CPU time 1.3 seconds
Started Mar 21 12:37:59 PM PDT 24
Finished Mar 21 12:38:00 PM PDT 24
Peak memory 201632 kb
Host smart-feb0897c-5921-44ac-80c8-36e465e06c2b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987517582 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.adc_ctrl_csr_mem_rw_with_rand_reset.1987517582
Directory /workspace/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.868671599
Short name T123
Test name
Test status
Simulation time 368833120 ps
CPU time 1.16 seconds
Started Mar 21 12:37:58 PM PDT 24
Finished Mar 21 12:38:00 PM PDT 24
Peak memory 201600 kb
Host smart-1a6ad85d-2644-4e78-aec1-25ec30f013b8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868671599 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.868671599
Directory /workspace/17.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.1684830620
Short name T849
Test name
Test status
Simulation time 469044678 ps
CPU time 0.9 seconds
Started Mar 21 12:37:57 PM PDT 24
Finished Mar 21 12:37:59 PM PDT 24
Peak memory 201660 kb
Host smart-a447b17b-2182-4ccf-ba45-e0f6715d943f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684830620 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.1684830620
Directory /workspace/17.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.3673391933
Short name T853
Test name
Test status
Simulation time 2078011108 ps
CPU time 5.98 seconds
Started Mar 21 12:37:52 PM PDT 24
Finished Mar 21 12:37:58 PM PDT 24
Peak memory 201588 kb
Host smart-3d4abd9a-923a-4152-aef1-bcc7bc8ada80
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673391933 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_
ctrl_same_csr_outstanding.3673391933
Directory /workspace/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.3561195018
Short name T882
Test name
Test status
Simulation time 479853590 ps
CPU time 1.81 seconds
Started Mar 21 12:37:51 PM PDT 24
Finished Mar 21 12:37:53 PM PDT 24
Peak memory 201808 kb
Host smart-17a3f0d4-44a3-4154-95aa-471fe09d2c54
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561195018 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.3561195018
Directory /workspace/17.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.121787980
Short name T59
Test name
Test status
Simulation time 8293419389 ps
CPU time 12.03 seconds
Started Mar 21 12:37:53 PM PDT 24
Finished Mar 21 12:38:05 PM PDT 24
Peak memory 201952 kb
Host smart-84a36a9e-bb9e-48b3-ba16-91bc02032c18
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121787980 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_in
tg_err.121787980
Directory /workspace/17.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.1051179182
Short name T823
Test name
Test status
Simulation time 527892628 ps
CPU time 1.21 seconds
Started Mar 21 12:38:07 PM PDT 24
Finished Mar 21 12:38:08 PM PDT 24
Peak memory 201660 kb
Host smart-4beee099-28a5-49a6-b0d5-5c7018274998
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051179182 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.adc_ctrl_csr_mem_rw_with_rand_reset.1051179182
Directory /workspace/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.450263573
Short name T897
Test name
Test status
Simulation time 542299857 ps
CPU time 1.46 seconds
Started Mar 21 12:37:59 PM PDT 24
Finished Mar 21 12:38:00 PM PDT 24
Peak memory 201600 kb
Host smart-f4673daf-3106-4b12-9a5a-4da283d110d2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450263573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.450263573
Directory /workspace/18.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.2899313941
Short name T915
Test name
Test status
Simulation time 378947030 ps
CPU time 1.47 seconds
Started Mar 21 12:38:02 PM PDT 24
Finished Mar 21 12:38:03 PM PDT 24
Peak memory 201580 kb
Host smart-5024f5d1-c75d-4ed6-82f6-e55baf3bab05
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899313941 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.2899313941
Directory /workspace/18.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.1101609211
Short name T852
Test name
Test status
Simulation time 4689865690 ps
CPU time 3.95 seconds
Started Mar 21 12:37:51 PM PDT 24
Finished Mar 21 12:37:55 PM PDT 24
Peak memory 201944 kb
Host smart-708251db-0e3d-44b7-8c41-ef2bf5ffb846
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101609211 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_
ctrl_same_csr_outstanding.1101609211
Directory /workspace/18.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.521451448
Short name T891
Test name
Test status
Simulation time 489045774 ps
CPU time 2.41 seconds
Started Mar 21 12:37:59 PM PDT 24
Finished Mar 21 12:38:02 PM PDT 24
Peak memory 201936 kb
Host smart-cfbfecd0-97b9-4889-9ba4-4feb27e68136
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521451448 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.521451448
Directory /workspace/18.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.208838092
Short name T862
Test name
Test status
Simulation time 4120861484 ps
CPU time 3.06 seconds
Started Mar 21 12:37:56 PM PDT 24
Finished Mar 21 12:38:01 PM PDT 24
Peak memory 201868 kb
Host smart-4b781c8f-a371-4044-86e3-b06a461022c4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208838092 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_in
tg_err.208838092
Directory /workspace/18.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.4064670696
Short name T84
Test name
Test status
Simulation time 490951444 ps
CPU time 2.02 seconds
Started Mar 21 12:38:08 PM PDT 24
Finished Mar 21 12:38:10 PM PDT 24
Peak memory 201632 kb
Host smart-8a43536a-06f4-43e5-981a-0d7acd5c2867
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064670696 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.adc_ctrl_csr_mem_rw_with_rand_reset.4064670696
Directory /workspace/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.3968667461
Short name T113
Test name
Test status
Simulation time 518062203 ps
CPU time 1.92 seconds
Started Mar 21 12:37:49 PM PDT 24
Finished Mar 21 12:37:51 PM PDT 24
Peak memory 201704 kb
Host smart-10e2e8da-87e7-4b7b-9d9b-aaa0fd83b53a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968667461 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.3968667461
Directory /workspace/19.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.1687105023
Short name T813
Test name
Test status
Simulation time 474207543 ps
CPU time 1.72 seconds
Started Mar 21 12:37:48 PM PDT 24
Finished Mar 21 12:37:50 PM PDT 24
Peak memory 201512 kb
Host smart-77ed6b7c-4369-43ab-92d9-6aceebe893a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687105023 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.1687105023
Directory /workspace/19.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.1208469360
Short name T816
Test name
Test status
Simulation time 2203279578 ps
CPU time 9.05 seconds
Started Mar 21 12:38:10 PM PDT 24
Finished Mar 21 12:38:19 PM PDT 24
Peak memory 201788 kb
Host smart-b75e0179-56d6-49d5-b4cc-fb0d60bd5c30
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208469360 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_
ctrl_same_csr_outstanding.1208469360
Directory /workspace/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.2791060431
Short name T871
Test name
Test status
Simulation time 370572306 ps
CPU time 1.97 seconds
Started Mar 21 12:37:47 PM PDT 24
Finished Mar 21 12:37:49 PM PDT 24
Peak memory 201972 kb
Host smart-c35b9775-aae2-40f1-b987-14dc98266718
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791060431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.2791060431
Directory /workspace/19.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.3773736041
Short name T895
Test name
Test status
Simulation time 4372175977 ps
CPU time 11.86 seconds
Started Mar 21 12:37:56 PM PDT 24
Finished Mar 21 12:38:10 PM PDT 24
Peak memory 201860 kb
Host smart-ee1f7192-c796-41c4-8abb-ff485a11732a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773736041 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_i
ntg_err.3773736041
Directory /workspace/19.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.1545409988
Short name T116
Test name
Test status
Simulation time 864872443 ps
CPU time 2.92 seconds
Started Mar 21 12:37:56 PM PDT 24
Finished Mar 21 12:38:01 PM PDT 24
Peak memory 201792 kb
Host smart-a1301b1d-7a61-4c20-9599-b4f4276722fa
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545409988 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_alia
sing.1545409988
Directory /workspace/2.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.720603342
Short name T902
Test name
Test status
Simulation time 27979643791 ps
CPU time 25.98 seconds
Started Mar 21 12:37:35 PM PDT 24
Finished Mar 21 12:38:02 PM PDT 24
Peak memory 201916 kb
Host smart-bc67233f-131b-40ae-a3a5-dd41e26daab3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720603342 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_b
ash.720603342
Directory /workspace/2.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.3025733387
Short name T811
Test name
Test status
Simulation time 874584643 ps
CPU time 2.89 seconds
Started Mar 21 12:37:41 PM PDT 24
Finished Mar 21 12:37:44 PM PDT 24
Peak memory 201604 kb
Host smart-f95ba7ee-a9d4-469f-a49b-935841f5be47
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025733387 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_r
eset.3025733387
Directory /workspace/2.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.1906318348
Short name T860
Test name
Test status
Simulation time 731368025 ps
CPU time 1.41 seconds
Started Mar 21 12:37:48 PM PDT 24
Finished Mar 21 12:37:50 PM PDT 24
Peak memory 201668 kb
Host smart-f864b382-1ded-488e-80d9-1ce4d34803f3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906318348 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.adc_ctrl_csr_mem_rw_with_rand_reset.1906318348
Directory /workspace/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.1238310798
Short name T115
Test name
Test status
Simulation time 458194869 ps
CPU time 1.93 seconds
Started Mar 21 12:37:47 PM PDT 24
Finished Mar 21 12:37:49 PM PDT 24
Peak memory 201628 kb
Host smart-9fb91bba-c558-4ee9-9d97-c755dc84fd2f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238310798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.1238310798
Directory /workspace/2.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.2599167778
Short name T822
Test name
Test status
Simulation time 285761906 ps
CPU time 1.27 seconds
Started Mar 21 12:37:47 PM PDT 24
Finished Mar 21 12:37:49 PM PDT 24
Peak memory 201624 kb
Host smart-a6986519-7e37-484b-99ed-b88a85571614
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599167778 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.2599167778
Directory /workspace/2.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.3213824573
Short name T122
Test name
Test status
Simulation time 2794313190 ps
CPU time 7.34 seconds
Started Mar 21 12:37:45 PM PDT 24
Finished Mar 21 12:37:53 PM PDT 24
Peak memory 201728 kb
Host smart-c463fab2-0c20-4724-8936-915c11170cf9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213824573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_c
trl_same_csr_outstanding.3213824573
Directory /workspace/2.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.206087331
Short name T884
Test name
Test status
Simulation time 678160285 ps
CPU time 2.35 seconds
Started Mar 21 12:37:37 PM PDT 24
Finished Mar 21 12:37:39 PM PDT 24
Peak memory 201920 kb
Host smart-60fea288-1d96-4310-aff8-4a608e2bc314
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206087331 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.206087331
Directory /workspace/2.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.1688945323
Short name T322
Test name
Test status
Simulation time 8477199850 ps
CPU time 8.11 seconds
Started Mar 21 12:37:50 PM PDT 24
Finished Mar 21 12:37:58 PM PDT 24
Peak memory 201968 kb
Host smart-93409681-09ef-48e8-99ac-c809355e272f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688945323 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_in
tg_err.1688945323
Directory /workspace/2.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.159943007
Short name T828
Test name
Test status
Simulation time 303167612 ps
CPU time 1.4 seconds
Started Mar 21 12:37:52 PM PDT 24
Finished Mar 21 12:37:53 PM PDT 24
Peak memory 201880 kb
Host smart-0b039c0a-4709-49b6-9fce-382d36b9fa6d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159943007 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.159943007
Directory /workspace/20.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.4006319160
Short name T918
Test name
Test status
Simulation time 376630938 ps
CPU time 1.5 seconds
Started Mar 21 12:38:04 PM PDT 24
Finished Mar 21 12:38:05 PM PDT 24
Peak memory 201656 kb
Host smart-e0b5b6ca-758e-44e3-96d7-8fa38fe7294d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006319160 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.4006319160
Directory /workspace/21.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.1011690743
Short name T800
Test name
Test status
Simulation time 419516614 ps
CPU time 0.88 seconds
Started Mar 21 12:37:58 PM PDT 24
Finished Mar 21 12:37:59 PM PDT 24
Peak memory 201576 kb
Host smart-fb6b546c-b43a-4b72-9a06-0141a5fffdbc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011690743 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.1011690743
Directory /workspace/22.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.1606979818
Short name T859
Test name
Test status
Simulation time 495163158 ps
CPU time 1.61 seconds
Started Mar 21 12:37:58 PM PDT 24
Finished Mar 21 12:38:00 PM PDT 24
Peak memory 201560 kb
Host smart-3460ea8f-aa81-4de2-a1be-48fa2e714f22
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606979818 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.1606979818
Directory /workspace/23.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.3700601673
Short name T900
Test name
Test status
Simulation time 481043432 ps
CPU time 1.7 seconds
Started Mar 21 12:37:50 PM PDT 24
Finished Mar 21 12:37:51 PM PDT 24
Peak memory 201596 kb
Host smart-378fd0f2-c6ad-4b99-8aca-5c84b6704c69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700601673 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.3700601673
Directory /workspace/24.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.3050194686
Short name T812
Test name
Test status
Simulation time 311564135 ps
CPU time 1.31 seconds
Started Mar 21 12:37:59 PM PDT 24
Finished Mar 21 12:38:01 PM PDT 24
Peak memory 201584 kb
Host smart-bd6570fc-4cff-467f-a109-0712e9bee4fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050194686 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.3050194686
Directory /workspace/25.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.72095862
Short name T870
Test name
Test status
Simulation time 477939887 ps
CPU time 1.1 seconds
Started Mar 21 12:37:56 PM PDT 24
Finished Mar 21 12:37:59 PM PDT 24
Peak memory 201692 kb
Host smart-11a07bd1-d7e4-4e1e-ac3c-a30ab0b6a8a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72095862 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.72095862
Directory /workspace/26.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.3378620959
Short name T799
Test name
Test status
Simulation time 432477311 ps
CPU time 0.75 seconds
Started Mar 21 12:37:58 PM PDT 24
Finished Mar 21 12:37:59 PM PDT 24
Peak memory 201580 kb
Host smart-200edb66-dbc9-4f92-ae9c-20685a4ff903
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378620959 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.3378620959
Directory /workspace/27.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.650603284
Short name T794
Test name
Test status
Simulation time 316664928 ps
CPU time 1.36 seconds
Started Mar 21 12:37:45 PM PDT 24
Finished Mar 21 12:37:46 PM PDT 24
Peak memory 201596 kb
Host smart-1afb4f3b-8239-4fcc-b2d9-0955dac885a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650603284 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.650603284
Directory /workspace/28.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.2519074074
Short name T873
Test name
Test status
Simulation time 522489668 ps
CPU time 0.86 seconds
Started Mar 21 12:37:49 PM PDT 24
Finished Mar 21 12:37:50 PM PDT 24
Peak memory 201588 kb
Host smart-7e97d4d9-e576-4946-8853-0c0dd0180320
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519074074 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.2519074074
Directory /workspace/29.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.2484642751
Short name T819
Test name
Test status
Simulation time 1328956266 ps
CPU time 2.96 seconds
Started Mar 21 12:37:46 PM PDT 24
Finished Mar 21 12:37:49 PM PDT 24
Peak memory 201788 kb
Host smart-ca8a3efe-70e6-414f-8234-8b9cfe48a7a3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484642751 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_alia
sing.2484642751
Directory /workspace/3.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.2208450320
Short name T908
Test name
Test status
Simulation time 762459765 ps
CPU time 2.53 seconds
Started Mar 21 12:37:57 PM PDT 24
Finished Mar 21 12:38:00 PM PDT 24
Peak memory 201580 kb
Host smart-2836a116-9c0b-4d9d-84ee-52aff1b1b110
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208450320 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_r
eset.2208450320
Directory /workspace/3.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.1489110971
Short name T833
Test name
Test status
Simulation time 525934262 ps
CPU time 1.92 seconds
Started Mar 21 12:37:52 PM PDT 24
Finished Mar 21 12:37:54 PM PDT 24
Peak memory 201768 kb
Host smart-e42f770f-0ba1-4cdf-908c-32ea4a903c69
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489110971 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.adc_ctrl_csr_mem_rw_with_rand_reset.1489110971
Directory /workspace/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.3077089367
Short name T844
Test name
Test status
Simulation time 559163101 ps
CPU time 2.2 seconds
Started Mar 21 12:37:52 PM PDT 24
Finished Mar 21 12:37:54 PM PDT 24
Peak memory 201716 kb
Host smart-0ef414eb-3a84-459d-80bd-f4ad28a49ef0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077089367 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.3077089367
Directory /workspace/3.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.833987767
Short name T887
Test name
Test status
Simulation time 501560154 ps
CPU time 1.21 seconds
Started Mar 21 12:37:39 PM PDT 24
Finished Mar 21 12:37:40 PM PDT 24
Peak memory 201576 kb
Host smart-bbe97d8a-bd88-4bb5-b294-701488bbc60a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833987767 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.833987767
Directory /workspace/3.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.2955720587
Short name T876
Test name
Test status
Simulation time 4640735046 ps
CPU time 11.13 seconds
Started Mar 21 12:37:51 PM PDT 24
Finished Mar 21 12:38:02 PM PDT 24
Peak memory 202032 kb
Host smart-638967ea-f44b-47c3-89cb-b6427ec3fe1e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955720587 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_c
trl_same_csr_outstanding.2955720587
Directory /workspace/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.1389867240
Short name T890
Test name
Test status
Simulation time 354591204 ps
CPU time 2.54 seconds
Started Mar 21 12:37:49 PM PDT 24
Finished Mar 21 12:37:52 PM PDT 24
Peak memory 210040 kb
Host smart-3dfcab9a-a196-4992-aaef-c314e1b129c8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389867240 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.1389867240
Directory /workspace/3.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.2120215215
Short name T881
Test name
Test status
Simulation time 4346364757 ps
CPU time 10.8 seconds
Started Mar 21 12:37:44 PM PDT 24
Finished Mar 21 12:37:55 PM PDT 24
Peak memory 201928 kb
Host smart-741c0040-b1df-4efd-a82d-a359751bf144
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120215215 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_in
tg_err.2120215215
Directory /workspace/3.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.4044428414
Short name T836
Test name
Test status
Simulation time 307400054 ps
CPU time 1.38 seconds
Started Mar 21 12:38:00 PM PDT 24
Finished Mar 21 12:38:02 PM PDT 24
Peak memory 201592 kb
Host smart-a355e2fe-6c86-4249-b3b2-4ddee3a1aa9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044428414 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.4044428414
Directory /workspace/30.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.1021884001
Short name T810
Test name
Test status
Simulation time 504325596 ps
CPU time 1.93 seconds
Started Mar 21 12:37:47 PM PDT 24
Finished Mar 21 12:37:49 PM PDT 24
Peak memory 201584 kb
Host smart-68707d31-33ea-44e4-b52d-3fbfc14c5af9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021884001 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.1021884001
Directory /workspace/31.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.3328153458
Short name T896
Test name
Test status
Simulation time 381175964 ps
CPU time 0.75 seconds
Started Mar 21 12:37:58 PM PDT 24
Finished Mar 21 12:37:59 PM PDT 24
Peak memory 201556 kb
Host smart-e2c366ff-d020-42eb-ad61-f3af171a1e1f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328153458 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.3328153458
Directory /workspace/32.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.2742665769
Short name T818
Test name
Test status
Simulation time 422572921 ps
CPU time 1.54 seconds
Started Mar 21 12:38:16 PM PDT 24
Finished Mar 21 12:38:18 PM PDT 24
Peak memory 201596 kb
Host smart-bb30d82f-4ad7-4350-9080-20774f7dfd3b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742665769 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.2742665769
Directory /workspace/33.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.1557863285
Short name T798
Test name
Test status
Simulation time 319067960 ps
CPU time 1.01 seconds
Started Mar 21 12:37:50 PM PDT 24
Finished Mar 21 12:37:51 PM PDT 24
Peak memory 201620 kb
Host smart-e7a8db9a-cc18-49c9-807a-40c966c2b498
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557863285 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.1557863285
Directory /workspace/34.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.2356533123
Short name T838
Test name
Test status
Simulation time 392298277 ps
CPU time 1.54 seconds
Started Mar 21 12:37:48 PM PDT 24
Finished Mar 21 12:37:50 PM PDT 24
Peak memory 201588 kb
Host smart-83b7d677-87d8-409e-a7b0-c810e2f2901a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356533123 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.2356533123
Directory /workspace/35.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.2177818283
Short name T863
Test name
Test status
Simulation time 460941011 ps
CPU time 1.81 seconds
Started Mar 21 12:38:01 PM PDT 24
Finished Mar 21 12:38:03 PM PDT 24
Peak memory 201580 kb
Host smart-e73cf758-17ec-4826-8322-12de3814d891
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177818283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.2177818283
Directory /workspace/36.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.3807678309
Short name T793
Test name
Test status
Simulation time 428277019 ps
CPU time 1.71 seconds
Started Mar 21 12:37:57 PM PDT 24
Finished Mar 21 12:38:00 PM PDT 24
Peak memory 201520 kb
Host smart-c19ac6f1-e11b-4a71-be8f-5a8140c3d9a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807678309 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.3807678309
Directory /workspace/37.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.2729536640
Short name T893
Test name
Test status
Simulation time 470955174 ps
CPU time 1.78 seconds
Started Mar 21 12:37:59 PM PDT 24
Finished Mar 21 12:38:00 PM PDT 24
Peak memory 201572 kb
Host smart-fc7daa63-2efa-4ac2-ba7a-3f3dc52012e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729536640 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.2729536640
Directory /workspace/38.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.2254400711
Short name T817
Test name
Test status
Simulation time 458318721 ps
CPU time 1.66 seconds
Started Mar 21 12:37:50 PM PDT 24
Finished Mar 21 12:37:52 PM PDT 24
Peak memory 201620 kb
Host smart-46c6c5e7-c6fe-41f8-b647-12ee8285de09
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254400711 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.2254400711
Directory /workspace/39.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.879040468
Short name T905
Test name
Test status
Simulation time 974516774 ps
CPU time 3.87 seconds
Started Mar 21 12:37:41 PM PDT 24
Finished Mar 21 12:37:45 PM PDT 24
Peak memory 201808 kb
Host smart-15d65ebf-c7f8-434d-a0a2-a15c7cf80231
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879040468 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_alias
ing.879040468
Directory /workspace/4.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.3873067073
Short name T119
Test name
Test status
Simulation time 49972372683 ps
CPU time 93.45 seconds
Started Mar 21 12:37:51 PM PDT 24
Finished Mar 21 12:39:24 PM PDT 24
Peak memory 201924 kb
Host smart-11ceb399-74fa-4dad-80b8-d9d2d6759f98
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873067073 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_
bash.3873067073
Directory /workspace/4.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.3764098324
Short name T814
Test name
Test status
Simulation time 1254771832 ps
CPU time 3.51 seconds
Started Mar 21 12:37:48 PM PDT 24
Finished Mar 21 12:37:51 PM PDT 24
Peak memory 201596 kb
Host smart-5a55ba6d-50e1-4038-b37d-8101a0ad213b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764098324 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_r
eset.3764098324
Directory /workspace/4.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.504040451
Short name T865
Test name
Test status
Simulation time 603468351 ps
CPU time 1.33 seconds
Started Mar 21 12:37:43 PM PDT 24
Finished Mar 21 12:37:44 PM PDT 24
Peak memory 201692 kb
Host smart-2a44700a-0441-470b-b7c1-7ec04ecc19e5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504040451 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.adc_ctrl_csr_mem_rw_with_rand_reset.504040451
Directory /workspace/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.3070596683
Short name T108
Test name
Test status
Simulation time 484470598 ps
CPU time 1.07 seconds
Started Mar 21 12:37:43 PM PDT 24
Finished Mar 21 12:37:44 PM PDT 24
Peak memory 201588 kb
Host smart-a5a59904-5c3b-4c3f-a9fa-0b3901615457
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070596683 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.3070596683
Directory /workspace/4.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.1640075931
Short name T874
Test name
Test status
Simulation time 431907208 ps
CPU time 0.88 seconds
Started Mar 21 12:37:58 PM PDT 24
Finished Mar 21 12:37:59 PM PDT 24
Peak memory 201576 kb
Host smart-06b3e9b5-7afe-466c-bae4-afcdf9b7b215
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640075931 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.1640075931
Directory /workspace/4.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.3156440705
Short name T909
Test name
Test status
Simulation time 4842120332 ps
CPU time 11.06 seconds
Started Mar 21 12:37:56 PM PDT 24
Finished Mar 21 12:38:09 PM PDT 24
Peak memory 201900 kb
Host smart-ba281106-8fef-4156-b071-30963496c4d7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156440705 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_c
trl_same_csr_outstanding.3156440705
Directory /workspace/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.4072406733
Short name T878
Test name
Test status
Simulation time 482694415 ps
CPU time 2.9 seconds
Started Mar 21 12:37:52 PM PDT 24
Finished Mar 21 12:37:55 PM PDT 24
Peak memory 218348 kb
Host smart-a724e3cf-b241-4b31-b0c6-5e88adb0e537
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072406733 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.4072406733
Directory /workspace/4.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.759954199
Short name T840
Test name
Test status
Simulation time 4428436843 ps
CPU time 7.97 seconds
Started Mar 21 12:37:29 PM PDT 24
Finished Mar 21 12:37:40 PM PDT 24
Peak memory 201104 kb
Host smart-b0749722-5961-4a11-8834-51f1c3135021
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759954199 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_int
g_err.759954199
Directory /workspace/4.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.3311266293
Short name T808
Test name
Test status
Simulation time 467197689 ps
CPU time 1.22 seconds
Started Mar 21 12:38:37 PM PDT 24
Finished Mar 21 12:38:39 PM PDT 24
Peak memory 201688 kb
Host smart-0210b7f9-94f7-495d-8480-902aebf08945
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311266293 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.3311266293
Directory /workspace/40.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.30226784
Short name T848
Test name
Test status
Simulation time 446912645 ps
CPU time 0.95 seconds
Started Mar 21 12:37:55 PM PDT 24
Finished Mar 21 12:37:56 PM PDT 24
Peak memory 201600 kb
Host smart-cce40d63-0b82-438f-b6fb-3699692b0a4d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30226784 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.30226784
Directory /workspace/41.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.2600418061
Short name T805
Test name
Test status
Simulation time 371283498 ps
CPU time 1.06 seconds
Started Mar 21 12:38:00 PM PDT 24
Finished Mar 21 12:38:01 PM PDT 24
Peak memory 201576 kb
Host smart-bbd5d722-769f-4ec2-9bf8-23bf0abd2385
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600418061 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.2600418061
Directory /workspace/42.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.731119575
Short name T843
Test name
Test status
Simulation time 386811379 ps
CPU time 1.66 seconds
Started Mar 21 12:37:48 PM PDT 24
Finished Mar 21 12:37:50 PM PDT 24
Peak memory 201688 kb
Host smart-20a7ee6e-8474-452a-b0ff-98412b5defe3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731119575 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.731119575
Directory /workspace/43.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.1018090036
Short name T797
Test name
Test status
Simulation time 497034960 ps
CPU time 0.93 seconds
Started Mar 21 12:38:08 PM PDT 24
Finished Mar 21 12:38:09 PM PDT 24
Peak memory 201580 kb
Host smart-3305f480-0a26-4f19-b75e-b8c7b13f0104
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018090036 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.1018090036
Directory /workspace/44.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.415029382
Short name T869
Test name
Test status
Simulation time 446448340 ps
CPU time 1.6 seconds
Started Mar 21 12:38:21 PM PDT 24
Finished Mar 21 12:38:23 PM PDT 24
Peak memory 201584 kb
Host smart-92a7cad8-a5b8-40b2-a61f-5caf340e1da6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415029382 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.415029382
Directory /workspace/45.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.3258875636
Short name T815
Test name
Test status
Simulation time 423098318 ps
CPU time 1.06 seconds
Started Mar 21 12:37:58 PM PDT 24
Finished Mar 21 12:38:00 PM PDT 24
Peak memory 201572 kb
Host smart-c20893cc-e042-42a2-a3cc-5f94a55b8304
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258875636 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.3258875636
Directory /workspace/46.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.105139337
Short name T804
Test name
Test status
Simulation time 410545423 ps
CPU time 1.55 seconds
Started Mar 21 12:37:48 PM PDT 24
Finished Mar 21 12:37:49 PM PDT 24
Peak memory 201692 kb
Host smart-5b57effb-b393-4443-a483-d4b3e1974d92
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105139337 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.105139337
Directory /workspace/47.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.1531330457
Short name T842
Test name
Test status
Simulation time 496393447 ps
CPU time 0.94 seconds
Started Mar 21 12:37:50 PM PDT 24
Finished Mar 21 12:37:51 PM PDT 24
Peak memory 201596 kb
Host smart-1629bfc4-da3d-43a0-8298-db2aaace8983
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531330457 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.1531330457
Directory /workspace/48.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.3444907521
Short name T806
Test name
Test status
Simulation time 449455311 ps
CPU time 1.65 seconds
Started Mar 21 12:38:02 PM PDT 24
Finished Mar 21 12:38:04 PM PDT 24
Peak memory 201584 kb
Host smart-ef58f92c-63f9-481e-9a9d-e3a4c66b6ee9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444907521 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.3444907521
Directory /workspace/49.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.3079263089
Short name T892
Test name
Test status
Simulation time 515130338 ps
CPU time 1.96 seconds
Started Mar 21 12:38:00 PM PDT 24
Finished Mar 21 12:38:02 PM PDT 24
Peak memory 201668 kb
Host smart-bfdfe529-bfa1-4078-929c-aa99b8c31f9c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079263089 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.adc_ctrl_csr_mem_rw_with_rand_reset.3079263089
Directory /workspace/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.2678810366
Short name T916
Test name
Test status
Simulation time 371410832 ps
CPU time 1.01 seconds
Started Mar 21 12:37:37 PM PDT 24
Finished Mar 21 12:37:38 PM PDT 24
Peak memory 201608 kb
Host smart-3d43c1c5-963d-4f87-92f0-441afe64c99c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678810366 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.2678810366
Directory /workspace/5.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.1206686249
Short name T906
Test name
Test status
Simulation time 358709052 ps
CPU time 0.86 seconds
Started Mar 21 12:37:49 PM PDT 24
Finished Mar 21 12:37:50 PM PDT 24
Peak memory 201596 kb
Host smart-bdb7f817-9b91-4a92-a96a-9b9f191917f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206686249 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.1206686249
Directory /workspace/5.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.2758476490
Short name T883
Test name
Test status
Simulation time 2358123374 ps
CPU time 3.39 seconds
Started Mar 21 12:37:39 PM PDT 24
Finished Mar 21 12:37:42 PM PDT 24
Peak memory 201732 kb
Host smart-d8d4231f-ddca-43ce-b450-26392048a514
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758476490 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_c
trl_same_csr_outstanding.2758476490
Directory /workspace/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.3121281378
Short name T903
Test name
Test status
Simulation time 515289646 ps
CPU time 3.22 seconds
Started Mar 21 12:37:46 PM PDT 24
Finished Mar 21 12:37:49 PM PDT 24
Peak memory 201828 kb
Host smart-1dc5bc2d-d10a-4cca-b2cf-5f51a8d94ca7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121281378 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.3121281378
Directory /workspace/5.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.1652651276
Short name T57
Test name
Test status
Simulation time 4468312458 ps
CPU time 4.18 seconds
Started Mar 21 12:37:47 PM PDT 24
Finished Mar 21 12:37:51 PM PDT 24
Peak memory 201896 kb
Host smart-8633b46a-5aaa-47ca-b799-8a236bab3ea5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652651276 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_in
tg_err.1652651276
Directory /workspace/5.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.2855870145
Short name T901
Test name
Test status
Simulation time 393892946 ps
CPU time 1.86 seconds
Started Mar 21 12:37:47 PM PDT 24
Finished Mar 21 12:37:49 PM PDT 24
Peak memory 201672 kb
Host smart-9e6c971b-2be5-469f-9ac3-83259db9f02b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855870145 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.adc_ctrl_csr_mem_rw_with_rand_reset.2855870145
Directory /workspace/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.522153336
Short name T867
Test name
Test status
Simulation time 421074211 ps
CPU time 1.8 seconds
Started Mar 21 12:37:55 PM PDT 24
Finished Mar 21 12:37:57 PM PDT 24
Peak memory 201600 kb
Host smart-8c31000e-f256-4430-b3d5-69fcd8ca7821
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522153336 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.522153336
Directory /workspace/6.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.4252321946
Short name T914
Test name
Test status
Simulation time 497119576 ps
CPU time 1.01 seconds
Started Mar 21 12:37:44 PM PDT 24
Finished Mar 21 12:37:45 PM PDT 24
Peak memory 201588 kb
Host smart-e9d46101-6fce-4e87-9d5c-8cb3da130568
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252321946 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.4252321946
Directory /workspace/6.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.415005044
Short name T821
Test name
Test status
Simulation time 4825903962 ps
CPU time 11.82 seconds
Started Mar 21 12:37:46 PM PDT 24
Finished Mar 21 12:37:58 PM PDT 24
Peak memory 201924 kb
Host smart-d55562ea-235c-4fde-a6b3-0ee23852d76d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415005044 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ct
rl_same_csr_outstanding.415005044
Directory /workspace/6.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.1331935800
Short name T875
Test name
Test status
Simulation time 503267051 ps
CPU time 2.96 seconds
Started Mar 21 12:37:42 PM PDT 24
Finished Mar 21 12:37:45 PM PDT 24
Peak memory 201828 kb
Host smart-396403eb-571d-40b5-98ea-6c8fd71277c5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331935800 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.1331935800
Directory /workspace/6.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.461705488
Short name T854
Test name
Test status
Simulation time 8679798859 ps
CPU time 23.76 seconds
Started Mar 21 12:37:43 PM PDT 24
Finished Mar 21 12:38:07 PM PDT 24
Peak memory 201936 kb
Host smart-33947a2c-c32a-4c6c-a3de-d311d42b417a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461705488 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_int
g_err.461705488
Directory /workspace/6.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.2518090220
Short name T831
Test name
Test status
Simulation time 528970374 ps
CPU time 1.2 seconds
Started Mar 21 12:37:45 PM PDT 24
Finished Mar 21 12:37:46 PM PDT 24
Peak memory 201656 kb
Host smart-08ca1593-1440-4b83-a831-45546ae95198
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518090220 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.adc_ctrl_csr_mem_rw_with_rand_reset.2518090220
Directory /workspace/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.276333515
Short name T830
Test name
Test status
Simulation time 318812385 ps
CPU time 1.17 seconds
Started Mar 21 12:37:34 PM PDT 24
Finished Mar 21 12:37:37 PM PDT 24
Peak memory 200784 kb
Host smart-676105d0-9ece-4050-bc92-f345192c2c60
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276333515 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.276333515
Directory /workspace/7.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.1713722959
Short name T866
Test name
Test status
Simulation time 511892352 ps
CPU time 1.26 seconds
Started Mar 21 12:37:50 PM PDT 24
Finished Mar 21 12:37:51 PM PDT 24
Peak memory 201596 kb
Host smart-d59bbcef-fec6-4dc7-a25f-7a32457f3df1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713722959 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.1713722959
Directory /workspace/7.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.1021690279
Short name T825
Test name
Test status
Simulation time 4360219293 ps
CPU time 3.46 seconds
Started Mar 21 12:37:40 PM PDT 24
Finished Mar 21 12:37:43 PM PDT 24
Peak memory 201956 kb
Host smart-79ba23b4-7e24-491f-9cd5-a13bb7436657
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021690279 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_c
trl_same_csr_outstanding.1021690279
Directory /workspace/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.454985015
Short name T70
Test name
Test status
Simulation time 675117204 ps
CPU time 1.74 seconds
Started Mar 21 12:37:40 PM PDT 24
Finished Mar 21 12:37:42 PM PDT 24
Peak memory 201868 kb
Host smart-c0c36ce9-5a5d-4294-838e-136555aeb513
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454985015 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.454985015
Directory /workspace/7.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.1584784614
Short name T835
Test name
Test status
Simulation time 4567411091 ps
CPU time 3.99 seconds
Started Mar 21 12:37:39 PM PDT 24
Finished Mar 21 12:37:43 PM PDT 24
Peak memory 201928 kb
Host smart-06ff533f-a020-400b-8b85-c829aa0e71e7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584784614 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_in
tg_err.1584784614
Directory /workspace/7.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.568729014
Short name T824
Test name
Test status
Simulation time 435217252 ps
CPU time 1.33 seconds
Started Mar 21 12:37:57 PM PDT 24
Finished Mar 21 12:37:59 PM PDT 24
Peak memory 201640 kb
Host smart-a38ae435-bbcd-45e0-8bb0-680bb701ee1d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568729014 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.adc_ctrl_csr_mem_rw_with_rand_reset.568729014
Directory /workspace/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.3685684051
Short name T832
Test name
Test status
Simulation time 425997401 ps
CPU time 1.67 seconds
Started Mar 21 12:37:43 PM PDT 24
Finished Mar 21 12:37:45 PM PDT 24
Peak memory 201608 kb
Host smart-687a23e3-5018-4375-b78e-98d17d2e78fa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685684051 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.3685684051
Directory /workspace/8.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.3469694242
Short name T809
Test name
Test status
Simulation time 518543207 ps
CPU time 1.78 seconds
Started Mar 21 12:37:54 PM PDT 24
Finished Mar 21 12:37:56 PM PDT 24
Peak memory 201576 kb
Host smart-10ff640b-ae95-44ba-9370-a9f87c0cfec7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469694242 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.3469694242
Directory /workspace/8.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.2656832947
Short name T54
Test name
Test status
Simulation time 2473218937 ps
CPU time 8.8 seconds
Started Mar 21 12:37:59 PM PDT 24
Finished Mar 21 12:38:08 PM PDT 24
Peak memory 201688 kb
Host smart-dd4f7674-5a10-425b-8dfa-9e687fd5a699
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656832947 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_c
trl_same_csr_outstanding.2656832947
Directory /workspace/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.1947115085
Short name T910
Test name
Test status
Simulation time 381904041 ps
CPU time 2.67 seconds
Started Mar 21 12:37:47 PM PDT 24
Finished Mar 21 12:37:50 PM PDT 24
Peak memory 201884 kb
Host smart-68dbda9c-e944-4cc9-b51e-657ba69d08d5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947115085 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.1947115085
Directory /workspace/8.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.74458978
Short name T885
Test name
Test status
Simulation time 8099901631 ps
CPU time 20.72 seconds
Started Mar 21 12:37:46 PM PDT 24
Finished Mar 21 12:38:07 PM PDT 24
Peak memory 201936 kb
Host smart-071a5396-e94d-4329-846f-fec0dc917764
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74458978 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_intg
_err.74458978
Directory /workspace/8.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.1114775074
Short name T858
Test name
Test status
Simulation time 586315844 ps
CPU time 2.19 seconds
Started Mar 21 12:37:38 PM PDT 24
Finished Mar 21 12:37:41 PM PDT 24
Peak memory 201688 kb
Host smart-e3a27353-577b-4698-a75a-68579bd14292
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114775074 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.adc_ctrl_csr_mem_rw_with_rand_reset.1114775074
Directory /workspace/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.1093145091
Short name T109
Test name
Test status
Simulation time 551757062 ps
CPU time 1.42 seconds
Started Mar 21 12:37:43 PM PDT 24
Finished Mar 21 12:37:45 PM PDT 24
Peak memory 201608 kb
Host smart-c0ff05f0-6706-420f-b92a-e94584fb0277
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093145091 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.1093145091
Directory /workspace/9.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.2687143631
Short name T796
Test name
Test status
Simulation time 505165082 ps
CPU time 1.88 seconds
Started Mar 21 12:37:45 PM PDT 24
Finished Mar 21 12:37:47 PM PDT 24
Peak memory 201560 kb
Host smart-2ed56b52-5500-40f3-ad73-fcbeca2653f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687143631 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.2687143631
Directory /workspace/9.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.4205857049
Short name T904
Test name
Test status
Simulation time 4457963328 ps
CPU time 10.63 seconds
Started Mar 21 12:37:48 PM PDT 24
Finished Mar 21 12:37:59 PM PDT 24
Peak memory 201904 kb
Host smart-cec66e99-7caa-4a9e-b42e-c803f1d4678a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205857049 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_c
trl_same_csr_outstanding.4205857049
Directory /workspace/9.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.201311025
Short name T888
Test name
Test status
Simulation time 552475489 ps
CPU time 3.72 seconds
Started Mar 21 12:37:47 PM PDT 24
Finished Mar 21 12:37:51 PM PDT 24
Peak memory 217860 kb
Host smart-f97877e9-20be-4f46-83f5-5141f7754631
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201311025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.201311025
Directory /workspace/9.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.adc_ctrl_alert_test.3325904691
Short name T728
Test name
Test status
Simulation time 438828041 ps
CPU time 1.64 seconds
Started Mar 21 12:44:09 PM PDT 24
Finished Mar 21 12:44:10 PM PDT 24
Peak memory 201412 kb
Host smart-3215026d-78a8-4d92-a5c7-2ec2dba19860
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325904691 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.3325904691
Directory /workspace/0.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.adc_ctrl_clock_gating.2942451137
Short name T196
Test name
Test status
Simulation time 160841952906 ps
CPU time 318.19 seconds
Started Mar 21 12:44:12 PM PDT 24
Finished Mar 21 12:49:31 PM PDT 24
Peak memory 201864 kb
Host smart-4ef677e9-b59b-4b46-ace2-155990ed929a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942451137 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gati
ng.2942451137
Directory /workspace/0.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt_fixed.1488851136
Short name T716
Test name
Test status
Simulation time 326058574869 ps
CPU time 764.43 seconds
Started Mar 21 12:44:07 PM PDT 24
Finished Mar 21 12:56:51 PM PDT 24
Peak memory 201768 kb
Host smart-51ce9652-eab5-4d7b-b40d-3f50f6d848dd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488851136 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrup
t_fixed.1488851136
Directory /workspace/0.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled.2546516658
Short name T565
Test name
Test status
Simulation time 161461507853 ps
CPU time 185.4 seconds
Started Mar 21 12:44:11 PM PDT 24
Finished Mar 21 12:47:17 PM PDT 24
Peak memory 201696 kb
Host smart-e486e821-c7de-44b1-9c88-2be13e303b4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546516658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.2546516658
Directory /workspace/0.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled_fixed.823309265
Short name T417
Test name
Test status
Simulation time 163761037473 ps
CPU time 181.86 seconds
Started Mar 21 12:44:12 PM PDT 24
Finished Mar 21 12:47:14 PM PDT 24
Peak memory 201704 kb
Host smart-768fa183-2085-45af-a9df-03e17314719a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=823309265 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixed
.823309265
Directory /workspace/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup.4214390917
Short name T267
Test name
Test status
Simulation time 203046093321 ps
CPU time 29.68 seconds
Started Mar 21 12:44:08 PM PDT 24
Finished Mar 21 12:44:38 PM PDT 24
Peak memory 201900 kb
Host smart-dd81b581-65d4-4eb7-a032-38184a47e30a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214390917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_
wakeup.4214390917
Directory /workspace/0.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup_fixed.81183846
Short name T694
Test name
Test status
Simulation time 388672413731 ps
CPU time 856.24 seconds
Started Mar 21 12:44:12 PM PDT 24
Finished Mar 21 12:58:29 PM PDT 24
Peak memory 201780 kb
Host smart-c1eac66d-6397-4c40-8dc8-081ca3717964
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81183846 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.ad
c_ctrl_filters_wakeup_fixed.81183846
Directory /workspace/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_fsm_reset.3664305804
Short name T394
Test name
Test status
Simulation time 87384421859 ps
CPU time 310.17 seconds
Started Mar 21 12:44:08 PM PDT 24
Finished Mar 21 12:49:18 PM PDT 24
Peak memory 202036 kb
Host smart-ad771265-0c62-4cf9-a1a1-7e336d59cd83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664305804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.3664305804
Directory /workspace/0.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_lowpower_counter.2587032194
Short name T45
Test name
Test status
Simulation time 45178565633 ps
CPU time 9.78 seconds
Started Mar 21 12:44:07 PM PDT 24
Finished Mar 21 12:44:17 PM PDT 24
Peak memory 201444 kb
Host smart-f2706147-2fa3-42cc-be62-bf6cd5fb7487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587032194 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.2587032194
Directory /workspace/0.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_poweron_counter.677055124
Short name T684
Test name
Test status
Simulation time 3692805097 ps
CPU time 4.82 seconds
Started Mar 21 12:44:08 PM PDT 24
Finished Mar 21 12:44:13 PM PDT 24
Peak memory 201416 kb
Host smart-35fb8d8a-eab3-4fe3-9e23-f834fd430486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677055124 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.677055124
Directory /workspace/0.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_smoke.3385660313
Short name T700
Test name
Test status
Simulation time 5853125745 ps
CPU time 15.2 seconds
Started Mar 21 12:44:09 PM PDT 24
Finished Mar 21 12:44:24 PM PDT 24
Peak memory 201620 kb
Host smart-24e83e05-e157-4b1a-8915-ef28fc642862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385660313 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.3385660313
Directory /workspace/0.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all.1056933297
Short name T317
Test name
Test status
Simulation time 241129969965 ps
CPU time 91.67 seconds
Started Mar 21 12:44:08 PM PDT 24
Finished Mar 21 12:45:40 PM PDT 24
Peak memory 202260 kb
Host smart-433f0563-c99c-4930-aea0-6514371a8358
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056933297 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.
1056933297
Directory /workspace/0.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.adc_ctrl_clock_gating.1008369175
Short name T134
Test name
Test status
Simulation time 329117033459 ps
CPU time 404.43 seconds
Started Mar 21 12:44:09 PM PDT 24
Finished Mar 21 12:50:53 PM PDT 24
Peak memory 201876 kb
Host smart-f1e0078a-5be0-4aeb-8ff0-7e4d16263d92
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008369175 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gati
ng.1008369175
Directory /workspace/1.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_both.3803202112
Short name T270
Test name
Test status
Simulation time 331620131701 ps
CPU time 747.92 seconds
Started Mar 21 12:44:06 PM PDT 24
Finished Mar 21 12:56:35 PM PDT 24
Peak memory 201760 kb
Host smart-1fec1efb-5135-4d8b-a625-9124181f8c98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803202112 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.3803202112
Directory /workspace/1.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt_fixed.613016487
Short name T577
Test name
Test status
Simulation time 320907380316 ps
CPU time 218.36 seconds
Started Mar 21 12:44:07 PM PDT 24
Finished Mar 21 12:47:46 PM PDT 24
Peak memory 201632 kb
Host smart-a144b5c9-84ad-45ef-8df0-31f96143b518
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=613016487 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt
_fixed.613016487
Directory /workspace/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled.2802081138
Short name T642
Test name
Test status
Simulation time 164326320077 ps
CPU time 92.98 seconds
Started Mar 21 12:44:09 PM PDT 24
Finished Mar 21 12:45:42 PM PDT 24
Peak memory 201740 kb
Host smart-0416a7be-61ee-4065-a078-bd83f710b64d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802081138 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.2802081138
Directory /workspace/1.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled_fixed.421198627
Short name T570
Test name
Test status
Simulation time 331008662115 ps
CPU time 775.91 seconds
Started Mar 21 12:44:08 PM PDT 24
Finished Mar 21 12:57:04 PM PDT 24
Peak memory 201692 kb
Host smart-50390523-f9d2-4723-890f-fdde579e796e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=421198627 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixed
.421198627
Directory /workspace/1.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup.360992595
Short name T446
Test name
Test status
Simulation time 166478220642 ps
CPU time 207.64 seconds
Started Mar 21 12:44:08 PM PDT 24
Finished Mar 21 12:47:36 PM PDT 24
Peak memory 201728 kb
Host smart-50a8780d-4b61-42fe-a61f-33c1df25b57d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360992595 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_w
akeup.360992595
Directory /workspace/1.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup_fixed.497608898
Short name T448
Test name
Test status
Simulation time 196465590574 ps
CPU time 79.16 seconds
Started Mar 21 12:44:08 PM PDT 24
Finished Mar 21 12:45:28 PM PDT 24
Peak memory 201700 kb
Host smart-0bad318a-3942-47be-bba0-11af27dd1dab
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497608898 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.a
dc_ctrl_filters_wakeup_fixed.497608898
Directory /workspace/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_fsm_reset.3111923413
Short name T210
Test name
Test status
Simulation time 82828166161 ps
CPU time 326.04 seconds
Started Mar 21 12:44:05 PM PDT 24
Finished Mar 21 12:49:31 PM PDT 24
Peak memory 202068 kb
Host smart-7d3c42e4-e393-4f1d-a765-123f55bd68cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111923413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.3111923413
Directory /workspace/1.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_lowpower_counter.1436896149
Short name T333
Test name
Test status
Simulation time 35731682183 ps
CPU time 22.62 seconds
Started Mar 21 12:44:12 PM PDT 24
Finished Mar 21 12:44:35 PM PDT 24
Peak memory 201528 kb
Host smart-7dd34a68-6ae5-45ff-8d4c-357c6a012149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436896149 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.1436896149
Directory /workspace/1.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_poweron_counter.1176115469
Short name T473
Test name
Test status
Simulation time 4037398851 ps
CPU time 6.13 seconds
Started Mar 21 12:44:12 PM PDT 24
Finished Mar 21 12:44:18 PM PDT 24
Peak memory 201452 kb
Host smart-80827f35-de81-41ae-9c6d-919e8ecdfba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176115469 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.1176115469
Directory /workspace/1.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_sec_cm.1962656734
Short name T62
Test name
Test status
Simulation time 7748872134 ps
CPU time 9.92 seconds
Started Mar 21 12:44:14 PM PDT 24
Finished Mar 21 12:44:24 PM PDT 24
Peak memory 218412 kb
Host smart-dd74f84c-23fd-4ff5-8f01-bacc19358a63
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962656734 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.1962656734
Directory /workspace/1.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.adc_ctrl_smoke.1387351848
Short name T470
Test name
Test status
Simulation time 5977105070 ps
CPU time 1.97 seconds
Started Mar 21 12:44:06 PM PDT 24
Finished Mar 21 12:44:08 PM PDT 24
Peak memory 201524 kb
Host smart-93d18485-a38d-4db6-9f41-127b7b3813da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387351848 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.1387351848
Directory /workspace/1.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all.4221918087
Short name T443
Test name
Test status
Simulation time 743115127123 ps
CPU time 868.56 seconds
Started Mar 21 12:44:10 PM PDT 24
Finished Mar 21 12:58:39 PM PDT 24
Peak memory 201688 kb
Host smart-5f849673-c8a0-416f-bda8-c0066e150213
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221918087 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.
4221918087
Directory /workspace/1.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.2028584505
Short name T23
Test name
Test status
Simulation time 175349661893 ps
CPU time 147.23 seconds
Started Mar 21 12:44:08 PM PDT 24
Finished Mar 21 12:46:35 PM PDT 24
Peak memory 210324 kb
Host smart-1851a257-40c7-407f-82c3-9a086e81e7a1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028584505 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all_with_rand_reset.2028584505
Directory /workspace/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_alert_test.3200033105
Short name T359
Test name
Test status
Simulation time 403891780 ps
CPU time 0.86 seconds
Started Mar 21 12:44:35 PM PDT 24
Finished Mar 21 12:44:37 PM PDT 24
Peak memory 201428 kb
Host smart-4da2a832-b892-4d6d-9ebe-94c23a468a2e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200033105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.3200033105
Directory /workspace/10.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.adc_ctrl_clock_gating.1120504937
Short name T139
Test name
Test status
Simulation time 523344684438 ps
CPU time 299.16 seconds
Started Mar 21 12:44:34 PM PDT 24
Finished Mar 21 12:49:33 PM PDT 24
Peak memory 201736 kb
Host smart-1ed5f239-8733-4f96-997a-fc68e10c80e8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120504937 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gat
ing.1120504937
Directory /workspace/10.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_both.189080746
Short name T614
Test name
Test status
Simulation time 177408388954 ps
CPU time 394.2 seconds
Started Mar 21 12:44:34 PM PDT 24
Finished Mar 21 12:51:08 PM PDT 24
Peak memory 201752 kb
Host smart-b61f2a21-4df2-47e2-9f6d-ef61bd5c1761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189080746 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.189080746
Directory /workspace/10.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt.1320457305
Short name T177
Test name
Test status
Simulation time 327078538473 ps
CPU time 205.9 seconds
Started Mar 21 12:44:34 PM PDT 24
Finished Mar 21 12:48:00 PM PDT 24
Peak memory 201724 kb
Host smart-8669ed72-8ee3-4df7-9db0-cee3f88ab63b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320457305 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.1320457305
Directory /workspace/10.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled.2121508648
Short name T311
Test name
Test status
Simulation time 494311804578 ps
CPU time 268.55 seconds
Started Mar 21 12:44:38 PM PDT 24
Finished Mar 21 12:49:07 PM PDT 24
Peak memory 201772 kb
Host smart-77020ad9-9b8a-420b-9d55-018820abc749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121508648 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.2121508648
Directory /workspace/10.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled_fixed.1672372145
Short name T671
Test name
Test status
Simulation time 490152076391 ps
CPU time 863.19 seconds
Started Mar 21 12:44:34 PM PDT 24
Finished Mar 21 12:58:58 PM PDT 24
Peak memory 201696 kb
Host smart-d390229d-6745-4434-83f3-c00a34da6786
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672372145 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fix
ed.1672372145
Directory /workspace/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup_fixed.1451491376
Short name T681
Test name
Test status
Simulation time 616033787950 ps
CPU time 1333.98 seconds
Started Mar 21 12:44:39 PM PDT 24
Finished Mar 21 01:06:53 PM PDT 24
Peak memory 201660 kb
Host smart-8a4eb624-e515-4699-bb8b-09a1be8cac63
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451491376 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10
.adc_ctrl_filters_wakeup_fixed.1451491376
Directory /workspace/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_fsm_reset.834534056
Short name T409
Test name
Test status
Simulation time 69022040950 ps
CPU time 222.88 seconds
Started Mar 21 12:44:35 PM PDT 24
Finished Mar 21 12:48:18 PM PDT 24
Peak memory 202036 kb
Host smart-f60c047f-bb9f-456a-94cf-b029d54022b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834534056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.834534056
Directory /workspace/10.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_lowpower_counter.1490751663
Short name T133
Test name
Test status
Simulation time 31140499376 ps
CPU time 18.24 seconds
Started Mar 21 12:44:35 PM PDT 24
Finished Mar 21 12:44:53 PM PDT 24
Peak memory 201336 kb
Host smart-d267b06b-bbe7-400b-9939-8dd11a869d55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490751663 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.1490751663
Directory /workspace/10.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_poweron_counter.3718266944
Short name T492
Test name
Test status
Simulation time 4574903063 ps
CPU time 11.3 seconds
Started Mar 21 12:44:37 PM PDT 24
Finished Mar 21 12:44:48 PM PDT 24
Peak memory 201480 kb
Host smart-5cf74e73-cdd4-4833-af8a-ac41aca4e35f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718266944 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.3718266944
Directory /workspace/10.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_smoke.2809320410
Short name T690
Test name
Test status
Simulation time 6100561452 ps
CPU time 3.45 seconds
Started Mar 21 12:44:34 PM PDT 24
Finished Mar 21 12:44:38 PM PDT 24
Peak memory 201548 kb
Host smart-a75f51bd-902f-4425-a42d-8ae92946032c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809320410 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.2809320410
Directory /workspace/10.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all.387845372
Short name T35
Test name
Test status
Simulation time 170169010885 ps
CPU time 59.68 seconds
Started Mar 21 12:44:32 PM PDT 24
Finished Mar 21 12:45:32 PM PDT 24
Peak memory 201784 kb
Host smart-2d6a6458-8459-470d-810c-1ef115e38e27
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387845372 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all.
387845372
Directory /workspace/10.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.2049986436
Short name T13
Test name
Test status
Simulation time 85954919055 ps
CPU time 114.91 seconds
Started Mar 21 12:44:37 PM PDT 24
Finished Mar 21 12:46:33 PM PDT 24
Peak memory 217844 kb
Host smart-64f0b44e-7292-4570-afbe-dc9084f1662c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049986436 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all_with_rand_reset.2049986436
Directory /workspace/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_alert_test.743825954
Short name T658
Test name
Test status
Simulation time 488615126 ps
CPU time 0.9 seconds
Started Mar 21 12:44:34 PM PDT 24
Finished Mar 21 12:44:36 PM PDT 24
Peak memory 201472 kb
Host smart-3cb9c7ec-5244-49d0-99a2-0e79ea13eabc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743825954 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.743825954
Directory /workspace/11.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.497406753
Short name T713
Test name
Test status
Simulation time 323947088705 ps
CPU time 186.89 seconds
Started Mar 21 12:44:39 PM PDT 24
Finished Mar 21 12:47:46 PM PDT 24
Peak memory 201632 kb
Host smart-da516ba2-b4d2-41f9-b599-b395039c3a37
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=497406753 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrup
t_fixed.497406753
Directory /workspace/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled.186092011
Short name T206
Test name
Test status
Simulation time 340097421594 ps
CPU time 212.06 seconds
Started Mar 21 12:44:33 PM PDT 24
Finished Mar 21 12:48:05 PM PDT 24
Peak memory 201724 kb
Host smart-ca8e12a3-dd5c-40f4-8a64-d8b4c771278a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186092011 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.186092011
Directory /workspace/11.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled_fixed.2500295822
Short name T422
Test name
Test status
Simulation time 329664211022 ps
CPU time 150.13 seconds
Started Mar 21 12:44:35 PM PDT 24
Finished Mar 21 12:47:05 PM PDT 24
Peak memory 201676 kb
Host smart-2ebb78f9-704c-4d79-8c79-0b7cd16bcf20
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500295822 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fix
ed.2500295822
Directory /workspace/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.2292136887
Short name T353
Test name
Test status
Simulation time 200637113149 ps
CPU time 455.23 seconds
Started Mar 21 12:44:39 PM PDT 24
Finished Mar 21 12:52:14 PM PDT 24
Peak memory 201676 kb
Host smart-c98eed92-bc5d-4686-98ec-014121a15c86
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292136887 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11
.adc_ctrl_filters_wakeup_fixed.2292136887
Directory /workspace/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_fsm_reset.3490313603
Short name T525
Test name
Test status
Simulation time 96603259659 ps
CPU time 451.37 seconds
Started Mar 21 12:44:34 PM PDT 24
Finished Mar 21 12:52:05 PM PDT 24
Peak memory 202176 kb
Host smart-35996a96-1d1b-463c-86f8-001fe4738ca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490313603 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.3490313603
Directory /workspace/11.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_lowpower_counter.3493203112
Short name T616
Test name
Test status
Simulation time 33079886971 ps
CPU time 19.09 seconds
Started Mar 21 12:44:34 PM PDT 24
Finished Mar 21 12:44:54 PM PDT 24
Peak memory 201356 kb
Host smart-3bd43c80-19ca-4066-b522-4c5d30b7d8ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493203112 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.3493203112
Directory /workspace/11.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_poweron_counter.1966751470
Short name T388
Test name
Test status
Simulation time 4360066483 ps
CPU time 9.95 seconds
Started Mar 21 12:44:35 PM PDT 24
Finished Mar 21 12:44:45 PM PDT 24
Peak memory 201504 kb
Host smart-51e04994-7e85-4d6f-a136-44bd0878d1b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966751470 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.1966751470
Directory /workspace/11.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_smoke.1624344832
Short name T399
Test name
Test status
Simulation time 5758969111 ps
CPU time 7.21 seconds
Started Mar 21 12:44:39 PM PDT 24
Finished Mar 21 12:44:47 PM PDT 24
Peak memory 201544 kb
Host smart-23cd7c20-5186-4447-a7e2-4620b6fc9d43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624344832 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.1624344832
Directory /workspace/11.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all.41184087
Short name T641
Test name
Test status
Simulation time 720216781584 ps
CPU time 1722.71 seconds
Started Mar 21 12:44:36 PM PDT 24
Finished Mar 21 01:13:19 PM PDT 24
Peak memory 201668 kb
Host smart-cf7e51f4-1ac4-4d4c-b435-d793af8368c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41184087 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all.41184087
Directory /workspace/11.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.adc_ctrl_alert_test.3861285527
Short name T755
Test name
Test status
Simulation time 535300456 ps
CPU time 1.34 seconds
Started Mar 21 12:44:38 PM PDT 24
Finished Mar 21 12:44:40 PM PDT 24
Peak memory 201428 kb
Host smart-851b291b-5bdd-4963-ab8a-399e86d37c1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861285527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.3861285527
Directory /workspace/12.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.adc_ctrl_clock_gating.2197288810
Short name T785
Test name
Test status
Simulation time 509585639556 ps
CPU time 365.57 seconds
Started Mar 21 12:44:39 PM PDT 24
Finished Mar 21 12:50:45 PM PDT 24
Peak memory 201748 kb
Host smart-7e91fe0e-05f8-492b-a976-a5042f5fcdc6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197288810 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gat
ing.2197288810
Directory /workspace/12.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_both.2241936199
Short name T693
Test name
Test status
Simulation time 167596002552 ps
CPU time 382.73 seconds
Started Mar 21 12:44:36 PM PDT 24
Finished Mar 21 12:50:59 PM PDT 24
Peak memory 201712 kb
Host smart-ddb5dc22-b163-49ec-b9df-282ac8baf0ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241936199 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.2241936199
Directory /workspace/12.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.441467842
Short name T461
Test name
Test status
Simulation time 487189274432 ps
CPU time 571.75 seconds
Started Mar 21 12:44:35 PM PDT 24
Finished Mar 21 12:54:07 PM PDT 24
Peak memory 201756 kb
Host smart-7a2f94f0-2c0e-4835-b911-f455c0fc36f4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=441467842 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrup
t_fixed.441467842
Directory /workspace/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled.415270438
Short name T625
Test name
Test status
Simulation time 165835141522 ps
CPU time 384.69 seconds
Started Mar 21 12:44:34 PM PDT 24
Finished Mar 21 12:50:59 PM PDT 24
Peak memory 201864 kb
Host smart-3a897d5e-8f0a-4d37-b2af-15c2f89bba09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415270438 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.415270438
Directory /workspace/12.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.4288292403
Short name T351
Test name
Test status
Simulation time 484636578274 ps
CPU time 312.37 seconds
Started Mar 21 12:44:32 PM PDT 24
Finished Mar 21 12:49:45 PM PDT 24
Peak memory 201844 kb
Host smart-124e0968-c287-4c36-b7a6-d609b3dd5764
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288292403 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fix
ed.4288292403
Directory /workspace/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup.1227109958
Short name T286
Test name
Test status
Simulation time 204480827350 ps
CPU time 462.67 seconds
Started Mar 21 12:44:35 PM PDT 24
Finished Mar 21 12:52:18 PM PDT 24
Peak memory 201612 kb
Host smart-818e3a6d-b468-4202-aa48-8b3790faf983
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227109958 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters
_wakeup.1227109958
Directory /workspace/12.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup_fixed.1310967239
Short name T81
Test name
Test status
Simulation time 206427239171 ps
CPU time 429.26 seconds
Started Mar 21 12:44:35 PM PDT 24
Finished Mar 21 12:51:45 PM PDT 24
Peak memory 201720 kb
Host smart-a9e49a92-a3f2-4d34-9e6a-ffca330ba503
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310967239 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12
.adc_ctrl_filters_wakeup_fixed.1310967239
Directory /workspace/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_fsm_reset.689562331
Short name T195
Test name
Test status
Simulation time 114387790556 ps
CPU time 454.08 seconds
Started Mar 21 12:44:36 PM PDT 24
Finished Mar 21 12:52:10 PM PDT 24
Peak memory 202012 kb
Host smart-8665a834-fd4a-4603-8f2b-a6e2cdd5c7e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689562331 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.689562331
Directory /workspace/12.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_lowpower_counter.3225856935
Short name T747
Test name
Test status
Simulation time 45519698941 ps
CPU time 25.68 seconds
Started Mar 21 12:44:36 PM PDT 24
Finished Mar 21 12:45:02 PM PDT 24
Peak memory 201680 kb
Host smart-bcb589c6-9003-475d-ae7a-5eb61f241820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225856935 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.3225856935
Directory /workspace/12.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_poweron_counter.1201436000
Short name T657
Test name
Test status
Simulation time 2960491430 ps
CPU time 2.54 seconds
Started Mar 21 12:44:38 PM PDT 24
Finished Mar 21 12:44:41 PM PDT 24
Peak memory 201428 kb
Host smart-5cfe56de-4740-4dda-b1d6-32fbca9020dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201436000 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.1201436000
Directory /workspace/12.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_smoke.4088154861
Short name T440
Test name
Test status
Simulation time 5915453663 ps
CPU time 3.94 seconds
Started Mar 21 12:44:34 PM PDT 24
Finished Mar 21 12:44:38 PM PDT 24
Peak memory 201620 kb
Host smart-50dd251d-d991-4c87-aa3e-9f548a504652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088154861 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.4088154861
Directory /workspace/12.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all.3798348055
Short name T745
Test name
Test status
Simulation time 171753245254 ps
CPU time 105.09 seconds
Started Mar 21 12:44:33 PM PDT 24
Finished Mar 21 12:46:19 PM PDT 24
Peak memory 201856 kb
Host smart-e69f468c-72e1-4625-9a98-f4ade14fcb78
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798348055 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all
.3798348055
Directory /workspace/12.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.2759607088
Short name T230
Test name
Test status
Simulation time 44176854924 ps
CPU time 59.04 seconds
Started Mar 21 12:44:36 PM PDT 24
Finished Mar 21 12:45:35 PM PDT 24
Peak memory 210112 kb
Host smart-d55e23ca-d695-41fa-9eb8-092f6a41a9da
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759607088 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all_with_rand_reset.2759607088
Directory /workspace/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_alert_test.3382699383
Short name T93
Test name
Test status
Simulation time 355262564 ps
CPU time 1.41 seconds
Started Mar 21 12:44:44 PM PDT 24
Finished Mar 21 12:44:46 PM PDT 24
Peak memory 201428 kb
Host smart-227a97d2-d736-4b2e-abf4-7b5a92255209
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382699383 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.3382699383
Directory /workspace/13.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.adc_ctrl_clock_gating.3320199603
Short name T14
Test name
Test status
Simulation time 558893834753 ps
CPU time 520.87 seconds
Started Mar 21 12:44:34 PM PDT 24
Finished Mar 21 12:53:15 PM PDT 24
Peak memory 201816 kb
Host smart-fbb46292-af6f-4d63-a304-dc702001aa8d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320199603 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gat
ing.3320199603
Directory /workspace/13.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_both.51682673
Short name T552
Test name
Test status
Simulation time 166945398331 ps
CPU time 389.49 seconds
Started Mar 21 12:44:36 PM PDT 24
Finished Mar 21 12:51:05 PM PDT 24
Peak memory 201616 kb
Host smart-01ef1a75-5470-40e4-a4ae-2fa83e73dc45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51682673 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.51682673
Directory /workspace/13.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt.2650181610
Short name T251
Test name
Test status
Simulation time 158589129613 ps
CPU time 184.6 seconds
Started Mar 21 12:44:36 PM PDT 24
Finished Mar 21 12:47:41 PM PDT 24
Peak memory 201876 kb
Host smart-abbfc87b-5dbb-42ef-b4b0-834b78c1ed69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650181610 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.2650181610
Directory /workspace/13.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt_fixed.2074575542
Short name T608
Test name
Test status
Simulation time 173538416870 ps
CPU time 109.86 seconds
Started Mar 21 12:44:32 PM PDT 24
Finished Mar 21 12:46:23 PM PDT 24
Peak memory 201776 kb
Host smart-4ce6bf98-254e-4c73-a60d-490280b6f8b4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074575542 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interru
pt_fixed.2074575542
Directory /workspace/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled.3467187418
Short name T518
Test name
Test status
Simulation time 164497089331 ps
CPU time 202.48 seconds
Started Mar 21 12:44:35 PM PDT 24
Finished Mar 21 12:47:58 PM PDT 24
Peak memory 201764 kb
Host smart-8e208a80-4d91-4dae-9f9f-b86848b99219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467187418 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.3467187418
Directory /workspace/13.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled_fixed.323633731
Short name T567
Test name
Test status
Simulation time 331264251745 ps
CPU time 782.47 seconds
Started Mar 21 12:44:36 PM PDT 24
Finished Mar 21 12:57:39 PM PDT 24
Peak memory 201676 kb
Host smart-95d3009f-eddd-4a8d-af93-a88d288565a3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=323633731 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fixe
d.323633731
Directory /workspace/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup.2514750293
Short name T748
Test name
Test status
Simulation time 175153406125 ps
CPU time 139.25 seconds
Started Mar 21 12:44:36 PM PDT 24
Finished Mar 21 12:46:55 PM PDT 24
Peak memory 201816 kb
Host smart-d9589b87-8318-4144-b61f-c81d97a5c033
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514750293 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters
_wakeup.2514750293
Directory /workspace/13.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup_fixed.3403717905
Short name T742
Test name
Test status
Simulation time 627811070135 ps
CPU time 1482.88 seconds
Started Mar 21 12:44:36 PM PDT 24
Finished Mar 21 01:09:20 PM PDT 24
Peak memory 201724 kb
Host smart-fd851219-e2c8-417e-9ed8-a47402b454a0
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403717905 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13
.adc_ctrl_filters_wakeup_fixed.3403717905
Directory /workspace/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_fsm_reset.1033009424
Short name T501
Test name
Test status
Simulation time 66367757966 ps
CPU time 233.62 seconds
Started Mar 21 12:44:50 PM PDT 24
Finished Mar 21 12:48:44 PM PDT 24
Peak memory 202180 kb
Host smart-b8cc89a4-9c42-45fb-8a20-270e4be16b0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033009424 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.1033009424
Directory /workspace/13.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_lowpower_counter.2757537200
Short name T368
Test name
Test status
Simulation time 27246781514 ps
CPU time 65.62 seconds
Started Mar 21 12:44:46 PM PDT 24
Finished Mar 21 12:45:52 PM PDT 24
Peak memory 201500 kb
Host smart-fddac092-b536-4bb6-9f63-721b5bde3ef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757537200 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.2757537200
Directory /workspace/13.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_poweron_counter.4072626170
Short name T412
Test name
Test status
Simulation time 4452570957 ps
CPU time 2.48 seconds
Started Mar 21 12:44:36 PM PDT 24
Finished Mar 21 12:44:39 PM PDT 24
Peak memory 201680 kb
Host smart-70e09a03-2ffe-4fd3-a215-5d0480fbeb30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072626170 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.4072626170
Directory /workspace/13.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_smoke.337286492
Short name T556
Test name
Test status
Simulation time 5896041627 ps
CPU time 4.33 seconds
Started Mar 21 12:44:35 PM PDT 24
Finished Mar 21 12:44:39 PM PDT 24
Peak memory 201552 kb
Host smart-c0b80981-7b2e-452a-84e3-57b51dd18ffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337286492 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.337286492
Directory /workspace/13.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all.1951379692
Short name T213
Test name
Test status
Simulation time 280620588638 ps
CPU time 1023.72 seconds
Started Mar 21 12:44:50 PM PDT 24
Finished Mar 21 01:01:54 PM PDT 24
Peak memory 202036 kb
Host smart-b8266f0a-69d8-43d2-90f0-4b64bc375492
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951379692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all
.1951379692
Directory /workspace/13.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.2073994918
Short name T38
Test name
Test status
Simulation time 153608547880 ps
CPU time 150.87 seconds
Started Mar 21 12:44:48 PM PDT 24
Finished Mar 21 12:47:19 PM PDT 24
Peak memory 210472 kb
Host smart-dccd468c-8959-4113-a8bd-44caa382c878
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073994918 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all_with_rand_reset.2073994918
Directory /workspace/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_alert_test.1657268667
Short name T575
Test name
Test status
Simulation time 445896194 ps
CPU time 0.88 seconds
Started Mar 21 12:44:51 PM PDT 24
Finished Mar 21 12:44:52 PM PDT 24
Peak memory 201416 kb
Host smart-9479b3ff-4a01-416d-8b8f-b5af4b992f3a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657268667 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.1657268667
Directory /workspace/14.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt.88376713
Short name T442
Test name
Test status
Simulation time 326427463475 ps
CPU time 785.56 seconds
Started Mar 21 12:44:45 PM PDT 24
Finished Mar 21 12:57:52 PM PDT 24
Peak memory 201796 kb
Host smart-8b2a839a-b4c0-4ad1-aa7f-329b1311c004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88376713 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.88376713
Directory /workspace/14.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt_fixed.3354216644
Short name T510
Test name
Test status
Simulation time 324289302702 ps
CPU time 365.93 seconds
Started Mar 21 12:44:49 PM PDT 24
Finished Mar 21 12:50:55 PM PDT 24
Peak memory 201704 kb
Host smart-d299b715-8ab5-423a-9527-c024a255ccfb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354216644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interru
pt_fixed.3354216644
Directory /workspace/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled.1867421294
Short name T248
Test name
Test status
Simulation time 327662400482 ps
CPU time 728.25 seconds
Started Mar 21 12:44:50 PM PDT 24
Finished Mar 21 12:56:59 PM PDT 24
Peak memory 201868 kb
Host smart-131c2880-c025-45c3-9c12-97a9222d1470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867421294 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.1867421294
Directory /workspace/14.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled_fixed.2175634172
Short name T379
Test name
Test status
Simulation time 165734096770 ps
CPU time 96.21 seconds
Started Mar 21 12:44:47 PM PDT 24
Finished Mar 21 12:46:24 PM PDT 24
Peak memory 201708 kb
Host smart-0225526f-7692-4903-8e01-5514b5176d5f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175634172 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fix
ed.2175634172
Directory /workspace/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup.2825196006
Short name T200
Test name
Test status
Simulation time 388798795191 ps
CPU time 102 seconds
Started Mar 21 12:44:49 PM PDT 24
Finished Mar 21 12:46:31 PM PDT 24
Peak memory 201720 kb
Host smart-9ec9e5ab-4552-4e8e-bf2b-04b272204bb2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825196006 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters
_wakeup.2825196006
Directory /workspace/14.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup_fixed.1161802760
Short name T438
Test name
Test status
Simulation time 403925910023 ps
CPU time 221.82 seconds
Started Mar 21 12:44:46 PM PDT 24
Finished Mar 21 12:48:29 PM PDT 24
Peak memory 201696 kb
Host smart-f3bf1090-231f-4251-a84d-6f1fcd6f6dca
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161802760 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14
.adc_ctrl_filters_wakeup_fixed.1161802760
Directory /workspace/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_lowpower_counter.1676751989
Short name T485
Test name
Test status
Simulation time 40218624584 ps
CPU time 92.96 seconds
Started Mar 21 12:44:47 PM PDT 24
Finished Mar 21 12:46:21 PM PDT 24
Peak memory 201532 kb
Host smart-682d9cbc-b60b-4ebc-ba9f-933b968e68dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676751989 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.1676751989
Directory /workspace/14.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_poweron_counter.1720048730
Short name T647
Test name
Test status
Simulation time 2890560001 ps
CPU time 7.97 seconds
Started Mar 21 12:44:53 PM PDT 24
Finished Mar 21 12:45:01 PM PDT 24
Peak memory 201472 kb
Host smart-9543f82e-3c6f-4b21-84dc-35ec365fc7ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720048730 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.1720048730
Directory /workspace/14.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_smoke.2911164743
Short name T335
Test name
Test status
Simulation time 6245305796 ps
CPU time 1.6 seconds
Started Mar 21 12:44:52 PM PDT 24
Finished Mar 21 12:44:54 PM PDT 24
Peak memory 201524 kb
Host smart-c5c5839e-b95b-493c-bed1-15dcd07f3d40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911164743 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.2911164743
Directory /workspace/14.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all.3140606303
Short name T89
Test name
Test status
Simulation time 79250943207 ps
CPU time 176.5 seconds
Started Mar 21 12:44:48 PM PDT 24
Finished Mar 21 12:47:45 PM PDT 24
Peak memory 201676 kb
Host smart-67c6d14b-9831-48e9-b749-bc20ffcff9a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140606303 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all
.3140606303
Directory /workspace/14.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.441706857
Short name T775
Test name
Test status
Simulation time 295612586703 ps
CPU time 427.04 seconds
Started Mar 21 12:44:45 PM PDT 24
Finished Mar 21 12:51:53 PM PDT 24
Peak memory 210428 kb
Host smart-57606e18-ab5b-4b3d-a46d-598bb76419bb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441706857 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all_with_rand_reset.441706857
Directory /workspace/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_alert_test.2969131996
Short name T571
Test name
Test status
Simulation time 346669105 ps
CPU time 0.78 seconds
Started Mar 21 12:44:52 PM PDT 24
Finished Mar 21 12:44:53 PM PDT 24
Peak memory 201408 kb
Host smart-aa248180-78a9-499d-b24f-ef16fc016fff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969131996 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.2969131996
Directory /workspace/15.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.adc_ctrl_clock_gating.1839837471
Short name T87
Test name
Test status
Simulation time 175337809984 ps
CPU time 105.71 seconds
Started Mar 21 12:44:47 PM PDT 24
Finished Mar 21 12:46:33 PM PDT 24
Peak memory 201744 kb
Host smart-2b893a0c-a590-4f28-9d9c-7505955d4476
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839837471 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gat
ing.1839837471
Directory /workspace/15.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt.3656569841
Short name T88
Test name
Test status
Simulation time 160093781857 ps
CPU time 400.91 seconds
Started Mar 21 12:44:47 PM PDT 24
Finished Mar 21 12:51:29 PM PDT 24
Peak memory 201732 kb
Host smart-e9cc965f-16f6-41f3-befb-9516195c8c0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656569841 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.3656569841
Directory /workspace/15.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt_fixed.2893393415
Short name T348
Test name
Test status
Simulation time 165771869524 ps
CPU time 401.17 seconds
Started Mar 21 12:44:46 PM PDT 24
Finished Mar 21 12:51:29 PM PDT 24
Peak memory 201684 kb
Host smart-a2f4e155-b404-4537-9cf2-5e21d9de0b36
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893393415 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interru
pt_fixed.2893393415
Directory /workspace/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled.2828418036
Short name T547
Test name
Test status
Simulation time 162502988077 ps
CPU time 316.41 seconds
Started Mar 21 12:44:46 PM PDT 24
Finished Mar 21 12:50:03 PM PDT 24
Peak memory 201712 kb
Host smart-c11869c1-abe6-4c1c-bfe5-547f50fe9301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828418036 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.2828418036
Directory /workspace/15.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled_fixed.3814896606
Short name T789
Test name
Test status
Simulation time 491990788332 ps
CPU time 311.2 seconds
Started Mar 21 12:44:49 PM PDT 24
Finished Mar 21 12:50:00 PM PDT 24
Peak memory 201716 kb
Host smart-9d4a5481-b4b2-41a7-9dcf-71db02783c56
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814896606 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fix
ed.3814896606
Directory /workspace/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup_fixed.3666299959
Short name T773
Test name
Test status
Simulation time 597798803050 ps
CPU time 741.8 seconds
Started Mar 21 12:44:48 PM PDT 24
Finished Mar 21 12:57:10 PM PDT 24
Peak memory 201672 kb
Host smart-72fea3a0-1241-4027-99dd-ff99168a920b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666299959 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.adc_ctrl_filters_wakeup_fixed.3666299959
Directory /workspace/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_fsm_reset.1831190794
Short name T605
Test name
Test status
Simulation time 106092846684 ps
CPU time 540.62 seconds
Started Mar 21 12:44:46 PM PDT 24
Finished Mar 21 12:53:48 PM PDT 24
Peak memory 202000 kb
Host smart-707c116c-a0fb-4d43-87ea-da11fa2cdf09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831190794 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.1831190794
Directory /workspace/15.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_lowpower_counter.1080971436
Short name T602
Test name
Test status
Simulation time 45229802406 ps
CPU time 53.12 seconds
Started Mar 21 12:44:51 PM PDT 24
Finished Mar 21 12:45:44 PM PDT 24
Peak memory 201588 kb
Host smart-e1ec2a01-8737-4a8a-97e6-6ef2f9ee1aec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080971436 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.1080971436
Directory /workspace/15.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_poweron_counter.3320862782
Short name T332
Test name
Test status
Simulation time 4530307715 ps
CPU time 11.63 seconds
Started Mar 21 12:44:44 PM PDT 24
Finished Mar 21 12:44:56 PM PDT 24
Peak memory 201512 kb
Host smart-c5f23080-84c7-4587-a9e9-fb73cd566cce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320862782 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.3320862782
Directory /workspace/15.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_smoke.634930184
Short name T548
Test name
Test status
Simulation time 5662194214 ps
CPU time 15.96 seconds
Started Mar 21 12:44:47 PM PDT 24
Finished Mar 21 12:45:04 PM PDT 24
Peak memory 201532 kb
Host smart-99249a04-db93-4247-8788-1664dfa1912c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634930184 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.634930184
Directory /workspace/15.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all.4080882980
Short name T295
Test name
Test status
Simulation time 165017055393 ps
CPU time 92.6 seconds
Started Mar 21 12:44:52 PM PDT 24
Finished Mar 21 12:46:24 PM PDT 24
Peak memory 201884 kb
Host smart-f6a18962-37eb-4efd-b0b4-fdfd8adb1d37
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080882980 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all
.4080882980
Directory /workspace/15.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.adc_ctrl_alert_test.2562681581
Short name T462
Test name
Test status
Simulation time 423065461 ps
CPU time 0.86 seconds
Started Mar 21 12:44:52 PM PDT 24
Finished Mar 21 12:44:53 PM PDT 24
Peak memory 201408 kb
Host smart-e80e4cf0-e5d6-4b6f-a93c-474b11d61af2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562681581 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.2562681581
Directory /workspace/16.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.adc_ctrl_clock_gating.3175921461
Short name T34
Test name
Test status
Simulation time 174545431248 ps
CPU time 103.03 seconds
Started Mar 21 12:44:46 PM PDT 24
Finished Mar 21 12:46:29 PM PDT 24
Peak memory 201740 kb
Host smart-cbbe0e67-a97b-4ed9-a39d-0a7ce397c2c4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175921461 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gat
ing.3175921461
Directory /workspace/16.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt.2396448212
Short name T637
Test name
Test status
Simulation time 490334196895 ps
CPU time 86.27 seconds
Started Mar 21 12:44:48 PM PDT 24
Finished Mar 21 12:46:14 PM PDT 24
Peak memory 201800 kb
Host smart-6efd9a89-d100-4ae5-9386-d0195de96353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396448212 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.2396448212
Directory /workspace/16.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt_fixed.4137653320
Short name T136
Test name
Test status
Simulation time 330837561423 ps
CPU time 105.28 seconds
Started Mar 21 12:44:48 PM PDT 24
Finished Mar 21 12:46:33 PM PDT 24
Peak memory 201796 kb
Host smart-3583d392-36ce-433a-b878-32c29a3a5ae0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137653320 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interru
pt_fixed.4137653320
Directory /workspace/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled.4036972829
Short name T282
Test name
Test status
Simulation time 334155880287 ps
CPU time 848.05 seconds
Started Mar 21 12:44:47 PM PDT 24
Finished Mar 21 12:58:56 PM PDT 24
Peak memory 201804 kb
Host smart-cb21c698-ea1a-451e-a694-10b211aafb27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036972829 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.4036972829
Directory /workspace/16.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled_fixed.3288761502
Short name T158
Test name
Test status
Simulation time 164698539546 ps
CPU time 341.61 seconds
Started Mar 21 12:44:46 PM PDT 24
Finished Mar 21 12:50:29 PM PDT 24
Peak memory 201780 kb
Host smart-991a2da4-bbcb-4042-a05e-576a7ce63e9a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288761502 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fix
ed.3288761502
Directory /workspace/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup.2474928282
Short name T751
Test name
Test status
Simulation time 531706705072 ps
CPU time 312.98 seconds
Started Mar 21 12:44:52 PM PDT 24
Finished Mar 21 12:50:06 PM PDT 24
Peak memory 201800 kb
Host smart-083ee221-79ae-4be7-b284-78732584fa22
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474928282 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters
_wakeup.2474928282
Directory /workspace/16.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup_fixed.3198285702
Short name T411
Test name
Test status
Simulation time 401178877548 ps
CPU time 882.49 seconds
Started Mar 21 12:44:51 PM PDT 24
Finished Mar 21 12:59:33 PM PDT 24
Peak memory 201888 kb
Host smart-e4b21a52-27e8-472c-b927-b061536373da
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198285702 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16
.adc_ctrl_filters_wakeup_fixed.3198285702
Directory /workspace/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_lowpower_counter.4103380383
Short name T623
Test name
Test status
Simulation time 44550763813 ps
CPU time 95.94 seconds
Started Mar 21 12:44:47 PM PDT 24
Finished Mar 21 12:46:24 PM PDT 24
Peak memory 201532 kb
Host smart-bcc6eb3f-08ec-4bef-944b-67cdcf3cc86b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103380383 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.4103380383
Directory /workspace/16.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_poweron_counter.1999729787
Short name T718
Test name
Test status
Simulation time 3796824801 ps
CPU time 9.76 seconds
Started Mar 21 12:44:52 PM PDT 24
Finished Mar 21 12:45:02 PM PDT 24
Peak memory 201452 kb
Host smart-9d8339b9-6135-4cb6-890b-31a954355de2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999729787 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.1999729787
Directory /workspace/16.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_smoke.2772663727
Short name T402
Test name
Test status
Simulation time 5826143051 ps
CPU time 14.9 seconds
Started Mar 21 12:44:49 PM PDT 24
Finished Mar 21 12:45:04 PM PDT 24
Peak memory 201628 kb
Host smart-7e915053-2492-44dd-88dc-df69e48335ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772663727 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.2772663727
Directory /workspace/16.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all.3823335702
Short name T563
Test name
Test status
Simulation time 300617800693 ps
CPU time 393.36 seconds
Started Mar 21 12:44:50 PM PDT 24
Finished Mar 21 12:51:23 PM PDT 24
Peak memory 202040 kb
Host smart-61ad2b1f-72ab-494e-b91d-fa2c66a95df7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823335702 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all
.3823335702
Directory /workspace/16.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.938924854
Short name T253
Test name
Test status
Simulation time 79713357641 ps
CPU time 99.05 seconds
Started Mar 21 12:44:48 PM PDT 24
Finished Mar 21 12:46:27 PM PDT 24
Peak memory 210332 kb
Host smart-33984b88-46aa-4d5c-b4b9-045c7bc38349
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938924854 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all_with_rand_reset.938924854
Directory /workspace/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_alert_test.3330315593
Short name T347
Test name
Test status
Simulation time 343701208 ps
CPU time 0.97 seconds
Started Mar 21 12:44:52 PM PDT 24
Finished Mar 21 12:44:53 PM PDT 24
Peak memory 201516 kb
Host smart-9033dd31-83e6-4430-825a-fe929c9a4091
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330315593 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.3330315593
Directory /workspace/17.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.adc_ctrl_clock_gating.1631870647
Short name T790
Test name
Test status
Simulation time 204755234860 ps
CPU time 236.17 seconds
Started Mar 21 12:44:45 PM PDT 24
Finished Mar 21 12:48:41 PM PDT 24
Peak memory 202252 kb
Host smart-5edbf187-6ace-460e-b2e8-c7f2724bcd03
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631870647 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gat
ing.1631870647
Directory /workspace/17.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_both.3933489149
Short name T653
Test name
Test status
Simulation time 526584719464 ps
CPU time 1249.97 seconds
Started Mar 21 12:44:48 PM PDT 24
Finished Mar 21 01:05:39 PM PDT 24
Peak memory 201680 kb
Host smart-3d1d3174-eca3-4454-802c-b37a68bda962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933489149 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.3933489149
Directory /workspace/17.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt.2277341499
Short name T764
Test name
Test status
Simulation time 320247840732 ps
CPU time 178.19 seconds
Started Mar 21 12:44:47 PM PDT 24
Finished Mar 21 12:47:46 PM PDT 24
Peak memory 201760 kb
Host smart-a42e12c0-d6b7-42d0-9ad4-d8f0dd94dfb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277341499 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.2277341499
Directory /workspace/17.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.3402830443
Short name T479
Test name
Test status
Simulation time 162064909258 ps
CPU time 73.07 seconds
Started Mar 21 12:44:50 PM PDT 24
Finished Mar 21 12:46:04 PM PDT 24
Peak memory 201764 kb
Host smart-faab08f3-7e18-4a57-8013-602d08087ddc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402830443 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interru
pt_fixed.3402830443
Directory /workspace/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled.1386326723
Short name T509
Test name
Test status
Simulation time 163079503704 ps
CPU time 406.11 seconds
Started Mar 21 12:44:47 PM PDT 24
Finished Mar 21 12:51:34 PM PDT 24
Peak memory 201720 kb
Host smart-cbc9d56d-0f41-43ed-bf55-2905aa3dbf40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386326723 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.1386326723
Directory /workspace/17.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled_fixed.439858923
Short name T420
Test name
Test status
Simulation time 327201579301 ps
CPU time 747.75 seconds
Started Mar 21 12:44:46 PM PDT 24
Finished Mar 21 12:57:15 PM PDT 24
Peak memory 201696 kb
Host smart-a77326fc-4e8c-4da4-9f4c-c22642a98934
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=439858923 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fixe
d.439858923
Directory /workspace/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup.4037789084
Short name T457
Test name
Test status
Simulation time 369186100053 ps
CPU time 438.9 seconds
Started Mar 21 12:44:52 PM PDT 24
Finished Mar 21 12:52:11 PM PDT 24
Peak memory 201732 kb
Host smart-16de2b6b-07e9-46cd-88f4-5ce9ccda5d43
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037789084 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters
_wakeup.4037789084
Directory /workspace/17.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup_fixed.2468430356
Short name T481
Test name
Test status
Simulation time 618602201919 ps
CPU time 726.76 seconds
Started Mar 21 12:44:49 PM PDT 24
Finished Mar 21 12:56:56 PM PDT 24
Peak memory 201716 kb
Host smart-03d7f078-6e47-439f-8883-07a2458e9224
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468430356 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17
.adc_ctrl_filters_wakeup_fixed.2468430356
Directory /workspace/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_fsm_reset.2144828238
Short name T692
Test name
Test status
Simulation time 113963630320 ps
CPU time 401.87 seconds
Started Mar 21 12:44:51 PM PDT 24
Finished Mar 21 12:51:33 PM PDT 24
Peak memory 202176 kb
Host smart-ec837d38-9d0e-48d2-a33a-8aec13601c55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144828238 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.2144828238
Directory /workspace/17.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_lowpower_counter.920533556
Short name T371
Test name
Test status
Simulation time 35096613580 ps
CPU time 24.53 seconds
Started Mar 21 12:44:52 PM PDT 24
Finished Mar 21 12:45:17 PM PDT 24
Peak memory 201508 kb
Host smart-523bcf52-9249-4106-92ff-bb6d897cd972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920533556 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.920533556
Directory /workspace/17.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_poweron_counter.2311148315
Short name T341
Test name
Test status
Simulation time 4858100932 ps
CPU time 5.29 seconds
Started Mar 21 12:44:49 PM PDT 24
Finished Mar 21 12:44:54 PM PDT 24
Peak memory 201536 kb
Host smart-d60a6485-bf98-4e3a-a187-a22eb2d0ecbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311148315 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.2311148315
Directory /workspace/17.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_smoke.1922769547
Short name T459
Test name
Test status
Simulation time 5735118682 ps
CPU time 6.95 seconds
Started Mar 21 12:44:53 PM PDT 24
Finished Mar 21 12:45:00 PM PDT 24
Peak memory 201548 kb
Host smart-d51e98ca-565b-4828-bc6b-238b2e53f07e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922769547 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.1922769547
Directory /workspace/17.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all.2296164976
Short name T301
Test name
Test status
Simulation time 455551951632 ps
CPU time 1101.44 seconds
Started Mar 21 12:44:46 PM PDT 24
Finished Mar 21 01:03:08 PM PDT 24
Peak memory 202172 kb
Host smart-9b7942cd-6a3c-434e-91e9-3414a280626b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296164976 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all
.2296164976
Directory /workspace/17.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.1806845912
Short name T722
Test name
Test status
Simulation time 32815116883 ps
CPU time 39.18 seconds
Started Mar 21 12:44:46 PM PDT 24
Finished Mar 21 12:45:26 PM PDT 24
Peak memory 210136 kb
Host smart-2c21e81d-5432-4c86-ae61-f1d86e1828c0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806845912 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all_with_rand_reset.1806845912
Directory /workspace/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_alert_test.4035538390
Short name T29
Test name
Test status
Simulation time 294732965 ps
CPU time 1.36 seconds
Started Mar 21 12:44:57 PM PDT 24
Finished Mar 21 12:44:58 PM PDT 24
Peak memory 201436 kb
Host smart-95e033f4-6a60-4c8c-97c1-0c34c04a4cce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035538390 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.4035538390
Directory /workspace/18.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.adc_ctrl_clock_gating.2777314396
Short name T204
Test name
Test status
Simulation time 514338046037 ps
CPU time 129.88 seconds
Started Mar 21 12:44:56 PM PDT 24
Finished Mar 21 12:47:06 PM PDT 24
Peak memory 201732 kb
Host smart-090f268e-314d-405d-8aaf-53ed78b35581
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777314396 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gat
ing.2777314396
Directory /workspace/18.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_both.2299107781
Short name T154
Test name
Test status
Simulation time 506093187395 ps
CPU time 210.94 seconds
Started Mar 21 12:44:51 PM PDT 24
Finished Mar 21 12:48:22 PM PDT 24
Peak memory 201784 kb
Host smart-6a66146c-0b36-4d9c-8d1f-9756e5505fd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299107781 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.2299107781
Directory /workspace/18.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt.1138315865
Short name T187
Test name
Test status
Simulation time 486008751238 ps
CPU time 121.65 seconds
Started Mar 21 12:44:55 PM PDT 24
Finished Mar 21 12:46:57 PM PDT 24
Peak memory 201724 kb
Host smart-33d177a0-6283-4e4a-9fd2-a385cffb713e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138315865 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.1138315865
Directory /workspace/18.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt_fixed.912553305
Short name T615
Test name
Test status
Simulation time 484696849575 ps
CPU time 334.9 seconds
Started Mar 21 12:44:55 PM PDT 24
Finished Mar 21 12:50:30 PM PDT 24
Peak memory 201660 kb
Host smart-5b359797-2184-4fd1-8c82-d5ab25015e57
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=912553305 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrup
t_fixed.912553305
Directory /workspace/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled.3412232961
Short name T182
Test name
Test status
Simulation time 324670460218 ps
CPU time 364.6 seconds
Started Mar 21 12:44:55 PM PDT 24
Finished Mar 21 12:51:00 PM PDT 24
Peak memory 201728 kb
Host smart-bb178316-7a42-4501-9dec-dd393c7b311f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412232961 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.3412232961
Directory /workspace/18.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled_fixed.1928315539
Short name T424
Test name
Test status
Simulation time 165135779390 ps
CPU time 93.64 seconds
Started Mar 21 12:44:54 PM PDT 24
Finished Mar 21 12:46:28 PM PDT 24
Peak memory 201656 kb
Host smart-0ba5c4ab-1447-46d2-b5b9-474d34974e74
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928315539 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fix
ed.1928315539
Directory /workspace/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup.701480286
Short name T191
Test name
Test status
Simulation time 382814807161 ps
CPU time 866.99 seconds
Started Mar 21 12:44:55 PM PDT 24
Finished Mar 21 12:59:22 PM PDT 24
Peak memory 201668 kb
Host smart-59e84321-2fae-4c45-89dd-f1aa0fdc3d14
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701480286 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_
wakeup.701480286
Directory /workspace/18.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.1529816666
Short name T586
Test name
Test status
Simulation time 599597021121 ps
CPU time 320.47 seconds
Started Mar 21 12:44:52 PM PDT 24
Finished Mar 21 12:50:13 PM PDT 24
Peak memory 201728 kb
Host smart-c6b9319a-fbb4-433d-a993-1c6d5484465a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529816666 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18
.adc_ctrl_filters_wakeup_fixed.1529816666
Directory /workspace/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_fsm_reset.2060569001
Short name T466
Test name
Test status
Simulation time 94084375268 ps
CPU time 473.78 seconds
Started Mar 21 12:44:46 PM PDT 24
Finished Mar 21 12:52:41 PM PDT 24
Peak memory 202144 kb
Host smart-8a5ac904-6fea-4a92-bcae-189cf8f8ca56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060569001 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.2060569001
Directory /workspace/18.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_lowpower_counter.4215088051
Short name T507
Test name
Test status
Simulation time 29641030681 ps
CPU time 37.81 seconds
Started Mar 21 12:44:56 PM PDT 24
Finished Mar 21 12:45:34 PM PDT 24
Peak memory 201512 kb
Host smart-7a2f5a70-b0d7-4866-82ca-b2e5cfbcb321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215088051 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.4215088051
Directory /workspace/18.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_poweron_counter.1585201264
Short name T723
Test name
Test status
Simulation time 4580133461 ps
CPU time 3.58 seconds
Started Mar 21 12:44:55 PM PDT 24
Finished Mar 21 12:44:59 PM PDT 24
Peak memory 201624 kb
Host smart-646222eb-a62a-4c02-963a-ebe141ff006b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585201264 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.1585201264
Directory /workspace/18.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_smoke.2657880248
Short name T676
Test name
Test status
Simulation time 5851517676 ps
CPU time 15.92 seconds
Started Mar 21 12:44:52 PM PDT 24
Finished Mar 21 12:45:08 PM PDT 24
Peak memory 201632 kb
Host smart-9d704778-2cd7-47f4-a08f-6ff3670b2125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657880248 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.2657880248
Directory /workspace/18.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all.2960284629
Short name T1
Test name
Test status
Simulation time 108425902614 ps
CPU time 454.28 seconds
Started Mar 21 12:44:57 PM PDT 24
Finished Mar 21 12:52:31 PM PDT 24
Peak memory 202020 kb
Host smart-14dbf8ad-62df-453d-88e1-91f8bcc8f3ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960284629 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all
.2960284629
Directory /workspace/18.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.2142014899
Short name T94
Test name
Test status
Simulation time 207357539849 ps
CPU time 126.1 seconds
Started Mar 21 12:44:55 PM PDT 24
Finished Mar 21 12:47:01 PM PDT 24
Peak memory 201984 kb
Host smart-e3597a68-886f-4b64-8c78-2e43014cfd93
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142014899 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all_with_rand_reset.2142014899
Directory /workspace/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_alert_test.3196012298
Short name T607
Test name
Test status
Simulation time 403867250 ps
CPU time 0.84 seconds
Started Mar 21 12:44:56 PM PDT 24
Finished Mar 21 12:44:57 PM PDT 24
Peak memory 201500 kb
Host smart-744fe1e2-652f-487d-9538-287e16fd1c1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196012298 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.3196012298
Directory /workspace/19.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.adc_ctrl_clock_gating.4124404592
Short name T484
Test name
Test status
Simulation time 247110677144 ps
CPU time 208.27 seconds
Started Mar 21 12:44:55 PM PDT 24
Finished Mar 21 12:48:23 PM PDT 24
Peak memory 201804 kb
Host smart-8785406d-3603-48e2-be8c-9b0895f8593f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124404592 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gat
ing.4124404592
Directory /workspace/19.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt.3496557574
Short name T619
Test name
Test status
Simulation time 162671072872 ps
CPU time 196.96 seconds
Started Mar 21 12:44:58 PM PDT 24
Finished Mar 21 12:48:16 PM PDT 24
Peak memory 201724 kb
Host smart-317254f5-b1c8-4cfc-98ba-6d7720cb88aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496557574 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.3496557574
Directory /workspace/19.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt_fixed.491012069
Short name T369
Test name
Test status
Simulation time 327665030918 ps
CPU time 780.03 seconds
Started Mar 21 12:44:55 PM PDT 24
Finished Mar 21 12:57:55 PM PDT 24
Peak memory 201664 kb
Host smart-5ed6d218-eff2-476f-8ba5-ca4e5cf60a94
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=491012069 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrup
t_fixed.491012069
Directory /workspace/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled.442974554
Short name T749
Test name
Test status
Simulation time 330931400016 ps
CPU time 796.86 seconds
Started Mar 21 12:44:55 PM PDT 24
Finished Mar 21 12:58:12 PM PDT 24
Peak memory 201684 kb
Host smart-68eea07f-916c-4b9d-b755-95f145fe9d07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442974554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.442974554
Directory /workspace/19.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled_fixed.937023200
Short name T170
Test name
Test status
Simulation time 166380442122 ps
CPU time 392.45 seconds
Started Mar 21 12:44:51 PM PDT 24
Finished Mar 21 12:51:24 PM PDT 24
Peak memory 201844 kb
Host smart-450815c2-cba4-41cf-b1db-b05dc410d312
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=937023200 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fixe
d.937023200
Directory /workspace/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup.3954933461
Short name T299
Test name
Test status
Simulation time 382755580368 ps
CPU time 233.27 seconds
Started Mar 21 12:44:49 PM PDT 24
Finished Mar 21 12:48:43 PM PDT 24
Peak memory 201768 kb
Host smart-1aa808d7-7c73-4dbf-9d7b-f75c930c50df
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954933461 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters
_wakeup.3954933461
Directory /workspace/19.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup_fixed.2916138323
Short name T169
Test name
Test status
Simulation time 407648108916 ps
CPU time 138.66 seconds
Started Mar 21 12:44:57 PM PDT 24
Finished Mar 21 12:47:15 PM PDT 24
Peak memory 201800 kb
Host smart-b09f8e44-31dd-4412-8381-1f8a29c07f22
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916138323 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19
.adc_ctrl_filters_wakeup_fixed.2916138323
Directory /workspace/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_fsm_reset.224912541
Short name T682
Test name
Test status
Simulation time 112907078927 ps
CPU time 457.98 seconds
Started Mar 21 12:44:54 PM PDT 24
Finished Mar 21 12:52:32 PM PDT 24
Peak memory 202184 kb
Host smart-aa530ee9-d2eb-41b1-9db5-6c5e98bd0e49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224912541 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.224912541
Directory /workspace/19.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_lowpower_counter.3397478603
Short name T537
Test name
Test status
Simulation time 42815643776 ps
CPU time 24.74 seconds
Started Mar 21 12:44:57 PM PDT 24
Finished Mar 21 12:45:22 PM PDT 24
Peak memory 201540 kb
Host smart-a64632b3-0904-48dc-b896-1b587ad5bee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397478603 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.3397478603
Directory /workspace/19.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_poweron_counter.1604380134
Short name T786
Test name
Test status
Simulation time 3907495678 ps
CPU time 3.05 seconds
Started Mar 21 12:44:51 PM PDT 24
Finished Mar 21 12:44:54 PM PDT 24
Peak memory 201448 kb
Host smart-17f2bf88-b42f-45ff-b088-ea730dc7c199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604380134 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.1604380134
Directory /workspace/19.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_smoke.1610212076
Short name T551
Test name
Test status
Simulation time 5693678647 ps
CPU time 4.25 seconds
Started Mar 21 12:44:50 PM PDT 24
Finished Mar 21 12:44:55 PM PDT 24
Peak memory 201508 kb
Host smart-bc45cd89-363f-4992-865e-f3c6e18e248c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610212076 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.1610212076
Directory /workspace/19.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.705563921
Short name T17
Test name
Test status
Simulation time 42459470086 ps
CPU time 99.41 seconds
Started Mar 21 12:45:03 PM PDT 24
Finished Mar 21 12:46:43 PM PDT 24
Peak memory 210428 kb
Host smart-610c02bf-3a74-40b0-8af9-ce01e40c3710
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705563921 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all_with_rand_reset.705563921
Directory /workspace/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_alert_test.1913366714
Short name T375
Test name
Test status
Simulation time 346399848 ps
CPU time 0.74 seconds
Started Mar 21 12:44:23 PM PDT 24
Finished Mar 21 12:44:24 PM PDT 24
Peak memory 201384 kb
Host smart-08a6a610-c9e9-4806-9262-32ee723ddd99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913366714 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.1913366714
Directory /workspace/2.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.adc_ctrl_clock_gating.1224108355
Short name T167
Test name
Test status
Simulation time 160743314629 ps
CPU time 349.8 seconds
Started Mar 21 12:44:09 PM PDT 24
Finished Mar 21 12:49:58 PM PDT 24
Peak memory 201676 kb
Host smart-a392d539-af94-4c5d-8714-dade77a34e02
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224108355 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gati
ng.1224108355
Directory /workspace/2.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_both.1097288425
Short name T425
Test name
Test status
Simulation time 162312612701 ps
CPU time 110.97 seconds
Started Mar 21 12:44:07 PM PDT 24
Finished Mar 21 12:45:58 PM PDT 24
Peak memory 201760 kb
Host smart-49978ef2-2faa-40ec-845e-eaecdab49779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097288425 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.1097288425
Directory /workspace/2.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt.3818417676
Short name T307
Test name
Test status
Simulation time 329088447793 ps
CPU time 203.41 seconds
Started Mar 21 12:44:07 PM PDT 24
Finished Mar 21 12:47:31 PM PDT 24
Peak memory 201716 kb
Host smart-9a67d0e9-ea76-44f6-b0d1-8bd9cfe3588d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818417676 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.3818417676
Directory /workspace/2.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt_fixed.3349576791
Short name T43
Test name
Test status
Simulation time 326462143909 ps
CPU time 726.98 seconds
Started Mar 21 12:44:09 PM PDT 24
Finished Mar 21 12:56:16 PM PDT 24
Peak memory 202160 kb
Host smart-c6a0a98f-f9a0-46cf-a8fc-1f6df52d8c70
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349576791 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrup
t_fixed.3349576791
Directory /workspace/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled.2181773647
Short name T465
Test name
Test status
Simulation time 171005660032 ps
CPU time 418.04 seconds
Started Mar 21 12:44:23 PM PDT 24
Finished Mar 21 12:51:21 PM PDT 24
Peak memory 201744 kb
Host smart-696f18d4-5455-48ad-898c-ebdbb5d13099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181773647 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.2181773647
Directory /workspace/2.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled_fixed.1171141475
Short name T528
Test name
Test status
Simulation time 329281510072 ps
CPU time 366.14 seconds
Started Mar 21 12:44:08 PM PDT 24
Finished Mar 21 12:50:15 PM PDT 24
Peak memory 201784 kb
Host smart-ff8c87f4-81d3-4fb0-bbdb-d5dca82819cc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171141475 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixe
d.1171141475
Directory /workspace/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup.2036278418
Short name T418
Test name
Test status
Simulation time 220656105508 ps
CPU time 528.68 seconds
Started Mar 21 12:44:23 PM PDT 24
Finished Mar 21 12:53:12 PM PDT 24
Peak memory 201692 kb
Host smart-135336fb-9705-48a1-8bcd-8ae38fc69a2b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036278418 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_
wakeup.2036278418
Directory /workspace/2.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup_fixed.3161155044
Short name T743
Test name
Test status
Simulation time 611078619807 ps
CPU time 337.92 seconds
Started Mar 21 12:44:24 PM PDT 24
Finished Mar 21 12:50:02 PM PDT 24
Peak memory 201668 kb
Host smart-a4cfcbdd-d00a-404f-b4f7-c73304276f47
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161155044 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.
adc_ctrl_filters_wakeup_fixed.3161155044
Directory /workspace/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_fsm_reset.1202100279
Short name T561
Test name
Test status
Simulation time 66708463836 ps
CPU time 328.8 seconds
Started Mar 21 12:44:08 PM PDT 24
Finished Mar 21 12:49:37 PM PDT 24
Peak memory 202540 kb
Host smart-f560e4a1-7d57-4482-befd-495f00225c75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202100279 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.1202100279
Directory /workspace/2.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_lowpower_counter.313521551
Short name T366
Test name
Test status
Simulation time 43022973028 ps
CPU time 52.52 seconds
Started Mar 21 12:44:10 PM PDT 24
Finished Mar 21 12:45:02 PM PDT 24
Peak memory 201532 kb
Host smart-d19b39d3-b9d2-418d-a3be-909a92136a8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313521551 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.313521551
Directory /workspace/2.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_poweron_counter.2621673837
Short name T601
Test name
Test status
Simulation time 3626482878 ps
CPU time 8.95 seconds
Started Mar 21 12:44:23 PM PDT 24
Finished Mar 21 12:44:32 PM PDT 24
Peak memory 201416 kb
Host smart-d0e180ee-f0de-4203-8edc-a066a02c0da0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621673837 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.2621673837
Directory /workspace/2.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_sec_cm.123653214
Short name T74
Test name
Test status
Simulation time 4399943861 ps
CPU time 11.62 seconds
Started Mar 21 12:44:10 PM PDT 24
Finished Mar 21 12:44:22 PM PDT 24
Peak memory 217316 kb
Host smart-2c2bc631-3a3a-4251-9975-5899518a9d0b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123653214 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.123653214
Directory /workspace/2.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.adc_ctrl_smoke.2919559057
Short name T686
Test name
Test status
Simulation time 6071941571 ps
CPU time 14.72 seconds
Started Mar 21 12:44:13 PM PDT 24
Finished Mar 21 12:44:28 PM PDT 24
Peak memory 201388 kb
Host smart-c1ae1fa2-2c11-4102-b48a-5947a8874fdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919559057 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.2919559057
Directory /workspace/2.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all.755641819
Short name T596
Test name
Test status
Simulation time 95842210625 ps
CPU time 342.13 seconds
Started Mar 21 12:44:08 PM PDT 24
Finished Mar 21 12:49:50 PM PDT 24
Peak memory 210264 kb
Host smart-477c698e-154a-4561-ae2b-77e38adbaefb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755641819 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.755641819
Directory /workspace/2.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.3659468224
Short name T22
Test name
Test status
Simulation time 377584641390 ps
CPU time 481.22 seconds
Started Mar 21 12:44:08 PM PDT 24
Finished Mar 21 12:52:09 PM PDT 24
Peak memory 218212 kb
Host smart-193c8102-a15d-4395-aff2-a1765a9110f3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659468224 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all_with_rand_reset.3659468224
Directory /workspace/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_alert_test.3164888302
Short name T640
Test name
Test status
Simulation time 500323130 ps
CPU time 0.91 seconds
Started Mar 21 12:45:14 PM PDT 24
Finished Mar 21 12:45:15 PM PDT 24
Peak memory 201392 kb
Host smart-947bdbdb-8447-4248-9982-706dc0e80965
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164888302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.3164888302
Directory /workspace/20.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.adc_ctrl_clock_gating.2051528793
Short name T79
Test name
Test status
Simulation time 333159801704 ps
CPU time 52.68 seconds
Started Mar 21 12:45:03 PM PDT 24
Finished Mar 21 12:45:56 PM PDT 24
Peak memory 201688 kb
Host smart-b8c5cec3-390e-412b-afe9-e3ddf154aa68
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051528793 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gat
ing.2051528793
Directory /workspace/20.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt.3336073357
Short name T310
Test name
Test status
Simulation time 496392993688 ps
CPU time 1115.78 seconds
Started Mar 21 12:44:56 PM PDT 24
Finished Mar 21 01:03:33 PM PDT 24
Peak memory 201872 kb
Host smart-32074a8d-6e6f-42b1-b1e7-22d60081abe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336073357 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.3336073357
Directory /workspace/20.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt_fixed.991105150
Short name T487
Test name
Test status
Simulation time 167139174754 ps
CPU time 92.2 seconds
Started Mar 21 12:45:03 PM PDT 24
Finished Mar 21 12:46:35 PM PDT 24
Peak memory 201676 kb
Host smart-4947d4a9-1c27-4b7a-b72e-2c6ff296f010
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=991105150 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrup
t_fixed.991105150
Directory /workspace/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled_fixed.1920307608
Short name T709
Test name
Test status
Simulation time 503829948878 ps
CPU time 322.62 seconds
Started Mar 21 12:44:57 PM PDT 24
Finished Mar 21 12:50:20 PM PDT 24
Peak memory 201784 kb
Host smart-5c0eff48-3156-471c-878b-b2495e524c87
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920307608 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fix
ed.1920307608
Directory /workspace/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup_fixed.1732010179
Short name T102
Test name
Test status
Simulation time 203977166571 ps
CPU time 387.64 seconds
Started Mar 21 12:44:59 PM PDT 24
Finished Mar 21 12:51:28 PM PDT 24
Peak memory 201704 kb
Host smart-ecfc927b-98bc-49c6-8088-f54df8f607a1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732010179 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20
.adc_ctrl_filters_wakeup_fixed.1732010179
Directory /workspace/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_fsm_reset.1692464240
Short name T209
Test name
Test status
Simulation time 65794853894 ps
CPU time 292.39 seconds
Started Mar 21 12:45:01 PM PDT 24
Finished Mar 21 12:49:54 PM PDT 24
Peak memory 202000 kb
Host smart-d3e965e4-bb0d-43a7-ab0b-60d3dd9c4b43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692464240 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.1692464240
Directory /workspace/20.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_lowpower_counter.2064307624
Short name T397
Test name
Test status
Simulation time 30912083214 ps
CPU time 19.29 seconds
Started Mar 21 12:44:58 PM PDT 24
Finished Mar 21 12:45:17 PM PDT 24
Peak memory 201512 kb
Host smart-63290014-0b65-4466-9ce5-50fc5c239979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064307624 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.2064307624
Directory /workspace/20.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_poweron_counter.2907181247
Short name T374
Test name
Test status
Simulation time 4718513687 ps
CPU time 2.78 seconds
Started Mar 21 12:44:59 PM PDT 24
Finished Mar 21 12:45:03 PM PDT 24
Peak memory 201528 kb
Host smart-9b828986-855e-4c70-9376-0c8f5d219e8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907181247 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.2907181247
Directory /workspace/20.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_smoke.1800722239
Short name T557
Test name
Test status
Simulation time 5765211165 ps
CPU time 7.49 seconds
Started Mar 21 12:45:03 PM PDT 24
Finished Mar 21 12:45:11 PM PDT 24
Peak memory 201508 kb
Host smart-02751a8f-9421-4cee-a3f8-ec0f6b8e2a1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800722239 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.1800722239
Directory /workspace/20.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all.2699274509
Short name T523
Test name
Test status
Simulation time 333502922274 ps
CPU time 809.19 seconds
Started Mar 21 12:45:12 PM PDT 24
Finished Mar 21 12:58:41 PM PDT 24
Peak memory 201676 kb
Host smart-6ec2c89f-70be-4082-af2e-480a9668b044
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699274509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all
.2699274509
Directory /workspace/20.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.3530814925
Short name T672
Test name
Test status
Simulation time 36135705323 ps
CPU time 81.8 seconds
Started Mar 21 12:45:04 PM PDT 24
Finished Mar 21 12:46:26 PM PDT 24
Peak memory 210092 kb
Host smart-ea91456e-5b31-4948-82cb-1ea3c43a95d2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530814925 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all_with_rand_reset.3530814925
Directory /workspace/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_alert_test.7264608
Short name T758
Test name
Test status
Simulation time 421952624 ps
CPU time 0.71 seconds
Started Mar 21 12:45:00 PM PDT 24
Finished Mar 21 12:45:02 PM PDT 24
Peak memory 201420 kb
Host smart-2d77973c-bc26-4876-9b75-008510b85741
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7264608 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.7264608
Directory /workspace/21.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.adc_ctrl_clock_gating.2080533779
Short name T232
Test name
Test status
Simulation time 165117455118 ps
CPU time 97.96 seconds
Started Mar 21 12:45:03 PM PDT 24
Finished Mar 21 12:46:41 PM PDT 24
Peak memory 201696 kb
Host smart-ec69fae8-2158-4afb-84c6-3918c907ad10
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080533779 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gat
ing.2080533779
Directory /workspace/21.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_both.2661837509
Short name T265
Test name
Test status
Simulation time 499263817060 ps
CPU time 479.64 seconds
Started Mar 21 12:45:14 PM PDT 24
Finished Mar 21 12:53:15 PM PDT 24
Peak memory 201668 kb
Host smart-e126a4b7-d3bc-487c-a593-4385db3569ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661837509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.2661837509
Directory /workspace/21.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt.1468087906
Short name T276
Test name
Test status
Simulation time 490607558443 ps
CPU time 188.32 seconds
Started Mar 21 12:45:03 PM PDT 24
Finished Mar 21 12:48:11 PM PDT 24
Peak memory 201732 kb
Host smart-bb0b7326-f43b-412d-89d6-b497fa23b7e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468087906 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.1468087906
Directory /workspace/21.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt_fixed.51330857
Short name T665
Test name
Test status
Simulation time 327077984531 ps
CPU time 361.09 seconds
Started Mar 21 12:45:14 PM PDT 24
Finished Mar 21 12:51:15 PM PDT 24
Peak memory 201632 kb
Host smart-e5eb5b4d-80a0-4024-94d2-9d8ca453c314
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=51330857 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt
_fixed.51330857
Directory /workspace/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled.21333133
Short name T606
Test name
Test status
Simulation time 327171208829 ps
CPU time 442.7 seconds
Started Mar 21 12:44:59 PM PDT 24
Finished Mar 21 12:52:22 PM PDT 24
Peak memory 201940 kb
Host smart-44b07e39-5e2e-46fc-9627-8c228b657e58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21333133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.21333133
Directory /workspace/21.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled_fixed.331816077
Short name T408
Test name
Test status
Simulation time 486684956235 ps
CPU time 1085.71 seconds
Started Mar 21 12:45:14 PM PDT 24
Finished Mar 21 01:03:21 PM PDT 24
Peak memory 201752 kb
Host smart-3f3cfd30-aea3-4d6c-9865-a8dbe0e16342
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=331816077 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fixe
d.331816077
Directory /workspace/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_fsm_reset.2824444984
Short name T215
Test name
Test status
Simulation time 91385311500 ps
CPU time 461.03 seconds
Started Mar 21 12:44:56 PM PDT 24
Finished Mar 21 12:52:37 PM PDT 24
Peak memory 202176 kb
Host smart-8aa3de11-516e-441e-8538-95074ca7658c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824444984 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.2824444984
Directory /workspace/21.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_lowpower_counter.2071907432
Short name T543
Test name
Test status
Simulation time 41592998998 ps
CPU time 48.32 seconds
Started Mar 21 12:45:03 PM PDT 24
Finished Mar 21 12:45:52 PM PDT 24
Peak memory 201620 kb
Host smart-a674f4a8-298c-4d34-a1dc-684451c90be4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071907432 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.2071907432
Directory /workspace/21.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_poweron_counter.3707320747
Short name T591
Test name
Test status
Simulation time 3794884185 ps
CPU time 5.13 seconds
Started Mar 21 12:45:14 PM PDT 24
Finished Mar 21 12:45:20 PM PDT 24
Peak memory 201412 kb
Host smart-53b5d3b9-d0ac-4e9f-99c9-ea0b8cca03e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707320747 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.3707320747
Directory /workspace/21.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_smoke.1317466039
Short name T334
Test name
Test status
Simulation time 5974335409 ps
CPU time 15.27 seconds
Started Mar 21 12:45:04 PM PDT 24
Finished Mar 21 12:45:19 PM PDT 24
Peak memory 201508 kb
Host smart-df72221e-b994-4516-aea2-b1b8245a3a5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317466039 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.1317466039
Directory /workspace/21.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.adc_ctrl_alert_test.960122998
Short name T663
Test name
Test status
Simulation time 487682731 ps
CPU time 0.9 seconds
Started Mar 21 12:45:04 PM PDT 24
Finished Mar 21 12:45:05 PM PDT 24
Peak memory 201392 kb
Host smart-ee66b9d3-b6a6-4378-b898-5ddb28c36294
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960122998 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.960122998
Directory /workspace/22.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_both.1473684476
Short name T650
Test name
Test status
Simulation time 367048574519 ps
CPU time 887.71 seconds
Started Mar 21 12:45:10 PM PDT 24
Finished Mar 21 12:59:58 PM PDT 24
Peak memory 201776 kb
Host smart-6a3add13-0c36-482f-84b4-4bdb608851da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473684476 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.1473684476
Directory /workspace/22.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt.1980190818
Short name T664
Test name
Test status
Simulation time 489905831881 ps
CPU time 1094.2 seconds
Started Mar 21 12:45:02 PM PDT 24
Finished Mar 21 01:03:16 PM PDT 24
Peak memory 201792 kb
Host smart-626ed23b-5d7e-4048-bf06-1984745af939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980190818 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.1980190818
Directory /workspace/22.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt_fixed.1057980921
Short name T721
Test name
Test status
Simulation time 166823937625 ps
CPU time 100.96 seconds
Started Mar 21 12:45:12 PM PDT 24
Finished Mar 21 12:46:53 PM PDT 24
Peak memory 201744 kb
Host smart-ceeffa79-b47b-47b6-969b-726ec3b2cc19
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057980921 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interru
pt_fixed.1057980921
Directory /workspace/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled.171413380
Short name T562
Test name
Test status
Simulation time 171597036172 ps
CPU time 102.47 seconds
Started Mar 21 12:45:15 PM PDT 24
Finished Mar 21 12:46:58 PM PDT 24
Peak memory 201692 kb
Host smart-7dcb6d28-bc42-4ed6-a158-b1f47fe2bee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171413380 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.171413380
Directory /workspace/22.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled_fixed.3427943664
Short name T380
Test name
Test status
Simulation time 330785992945 ps
CPU time 763.47 seconds
Started Mar 21 12:45:15 PM PDT 24
Finished Mar 21 12:57:59 PM PDT 24
Peak memory 200572 kb
Host smart-73ef4f55-0c01-48b8-b309-7ccd67af9026
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427943664 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fix
ed.3427943664
Directory /workspace/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup.4166027664
Short name T239
Test name
Test status
Simulation time 454930634113 ps
CPU time 270.63 seconds
Started Mar 21 12:44:57 PM PDT 24
Finished Mar 21 12:49:28 PM PDT 24
Peak memory 201920 kb
Host smart-982b2062-228b-4990-9ce2-ca0ef568855d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166027664 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters
_wakeup.4166027664
Directory /workspace/22.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup_fixed.27937319
Short name T475
Test name
Test status
Simulation time 597370165622 ps
CPU time 1488.18 seconds
Started Mar 21 12:44:58 PM PDT 24
Finished Mar 21 01:09:47 PM PDT 24
Peak memory 201700 kb
Host smart-b4b7b746-5a51-4294-8634-a9c507676c60
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27937319 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.a
dc_ctrl_filters_wakeup_fixed.27937319
Directory /workspace/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_lowpower_counter.2648241782
Short name T194
Test name
Test status
Simulation time 34752466236 ps
CPU time 34.14 seconds
Started Mar 21 12:45:10 PM PDT 24
Finished Mar 21 12:45:44 PM PDT 24
Peak memory 201488 kb
Host smart-749fd383-8f11-47f2-a744-c1f08b2357dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648241782 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.2648241782
Directory /workspace/22.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_poweron_counter.746217260
Short name T474
Test name
Test status
Simulation time 4824849769 ps
CPU time 1.71 seconds
Started Mar 21 12:45:01 PM PDT 24
Finished Mar 21 12:45:04 PM PDT 24
Peak memory 201544 kb
Host smart-8049467d-81b1-4029-8e34-8f8be7179fa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746217260 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.746217260
Directory /workspace/22.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_smoke.2266583058
Short name T472
Test name
Test status
Simulation time 5905561606 ps
CPU time 7.99 seconds
Started Mar 21 12:45:13 PM PDT 24
Finished Mar 21 12:45:22 PM PDT 24
Peak memory 201504 kb
Host smart-2037aa63-2110-488b-b9b7-5bb77aeee7a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266583058 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.2266583058
Directory /workspace/22.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all.2283742832
Short name T279
Test name
Test status
Simulation time 663382846485 ps
CPU time 804.55 seconds
Started Mar 21 12:44:58 PM PDT 24
Finished Mar 21 12:58:23 PM PDT 24
Peak memory 201636 kb
Host smart-8f2d7203-1c5d-4359-a06f-fab761be9229
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283742832 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all
.2283742832
Directory /workspace/22.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.3633075287
Short name T46
Test name
Test status
Simulation time 45004209707 ps
CPU time 109.02 seconds
Started Mar 21 12:44:59 PM PDT 24
Finished Mar 21 12:46:48 PM PDT 24
Peak memory 210432 kb
Host smart-93d95484-ba4b-4c23-b60a-675711a4f80c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633075287 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all_with_rand_reset.3633075287
Directory /workspace/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_alert_test.2429356136
Short name T572
Test name
Test status
Simulation time 321811746 ps
CPU time 1.07 seconds
Started Mar 21 12:45:13 PM PDT 24
Finished Mar 21 12:45:14 PM PDT 24
Peak memory 201636 kb
Host smart-3da6532a-3473-451c-a19a-196f83fd6c0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429356136 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.2429356136
Directory /workspace/23.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.adc_ctrl_clock_gating.2052365306
Short name T598
Test name
Test status
Simulation time 510561757057 ps
CPU time 1184.82 seconds
Started Mar 21 12:45:14 PM PDT 24
Finished Mar 21 01:04:59 PM PDT 24
Peak memory 201740 kb
Host smart-d05583f3-e8e0-4961-a682-740846387fd9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052365306 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gat
ing.2052365306
Directory /workspace/23.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_both.2687275666
Short name T128
Test name
Test status
Simulation time 186859316509 ps
CPU time 261.9 seconds
Started Mar 21 12:45:11 PM PDT 24
Finished Mar 21 12:49:33 PM PDT 24
Peak memory 201852 kb
Host smart-d2d7788b-cccb-4840-a096-c422eba0ba02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687275666 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.2687275666
Directory /workspace/23.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt.3452896990
Short name T489
Test name
Test status
Simulation time 334879928969 ps
CPU time 806.22 seconds
Started Mar 21 12:45:03 PM PDT 24
Finished Mar 21 12:58:30 PM PDT 24
Peak memory 201796 kb
Host smart-ef755dd9-d042-498a-99b9-32291f85195f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452896990 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.3452896990
Directory /workspace/23.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt_fixed.982305576
Short name T652
Test name
Test status
Simulation time 162771108438 ps
CPU time 42.57 seconds
Started Mar 21 12:45:00 PM PDT 24
Finished Mar 21 12:45:43 PM PDT 24
Peak memory 201696 kb
Host smart-93911eeb-4274-49f9-9e20-12cb70e907e4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=982305576 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrup
t_fixed.982305576
Directory /workspace/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled.1484684810
Short name T574
Test name
Test status
Simulation time 166290385656 ps
CPU time 30.06 seconds
Started Mar 21 12:45:14 PM PDT 24
Finished Mar 21 12:45:44 PM PDT 24
Peak memory 201612 kb
Host smart-af306a87-b2e3-4967-ac95-e77e29cca6da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484684810 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.1484684810
Directory /workspace/23.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled_fixed.1654794223
Short name T540
Test name
Test status
Simulation time 328469917674 ps
CPU time 54.79 seconds
Started Mar 21 12:45:01 PM PDT 24
Finished Mar 21 12:45:57 PM PDT 24
Peak memory 201700 kb
Host smart-d8da82ff-b877-45a4-acea-1d0d420c676d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654794223 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fix
ed.1654794223
Directory /workspace/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup.3245879946
Short name T314
Test name
Test status
Simulation time 650346155924 ps
CPU time 884.11 seconds
Started Mar 21 12:45:01 PM PDT 24
Finished Mar 21 12:59:45 PM PDT 24
Peak memory 201728 kb
Host smart-d475d801-2c73-4c5f-8bc8-f5b5c9f9f4d7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245879946 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters
_wakeup.3245879946
Directory /workspace/23.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup_fixed.1862700080
Short name T455
Test name
Test status
Simulation time 394723224629 ps
CPU time 477.42 seconds
Started Mar 21 12:45:11 PM PDT 24
Finished Mar 21 12:53:08 PM PDT 24
Peak memory 201768 kb
Host smart-113d551d-1e74-4d4a-83cd-16b2f38363dd
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862700080 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23
.adc_ctrl_filters_wakeup_fixed.1862700080
Directory /workspace/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_fsm_reset.2924919566
Short name T617
Test name
Test status
Simulation time 125321071630 ps
CPU time 530.88 seconds
Started Mar 21 12:45:12 PM PDT 24
Finished Mar 21 12:54:03 PM PDT 24
Peak memory 202020 kb
Host smart-8a169595-88c3-4eb0-ad60-6308a7f86710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924919566 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.2924919566
Directory /workspace/23.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_lowpower_counter.1902086204
Short name T372
Test name
Test status
Simulation time 33025973623 ps
CPU time 19.3 seconds
Started Mar 21 12:45:16 PM PDT 24
Finished Mar 21 12:45:36 PM PDT 24
Peak memory 201476 kb
Host smart-72a9d3d8-7790-42f8-9542-5f3508dac877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902086204 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.1902086204
Directory /workspace/23.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_poweron_counter.2203490444
Short name T662
Test name
Test status
Simulation time 3732784926 ps
CPU time 9.97 seconds
Started Mar 21 12:45:11 PM PDT 24
Finished Mar 21 12:45:21 PM PDT 24
Peak memory 201448 kb
Host smart-a3c864d3-53d5-4370-98d9-9ce743d1fb3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203490444 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.2203490444
Directory /workspace/23.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_smoke.447260877
Short name T685
Test name
Test status
Simulation time 5758843699 ps
CPU time 6.08 seconds
Started Mar 21 12:44:59 PM PDT 24
Finished Mar 21 12:45:05 PM PDT 24
Peak memory 201512 kb
Host smart-41134616-f104-46e9-8dc9-4cda6613d7af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447260877 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.447260877
Directory /workspace/23.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all.2324328543
Short name T308
Test name
Test status
Simulation time 285254418768 ps
CPU time 95.66 seconds
Started Mar 21 12:45:10 PM PDT 24
Finished Mar 21 12:46:46 PM PDT 24
Peak memory 201708 kb
Host smart-ac2ebfab-a682-417e-b6a2-53a0556648af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324328543 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all
.2324328543
Directory /workspace/23.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.1096040349
Short name T39
Test name
Test status
Simulation time 91272823793 ps
CPU time 244.94 seconds
Started Mar 21 12:45:17 PM PDT 24
Finished Mar 21 12:49:22 PM PDT 24
Peak memory 210636 kb
Host smart-27904e7c-054e-4718-bc95-a485a417a85f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096040349 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all_with_rand_reset.1096040349
Directory /workspace/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_alert_test.2367682660
Short name T361
Test name
Test status
Simulation time 401135757 ps
CPU time 1.05 seconds
Started Mar 21 12:45:11 PM PDT 24
Finished Mar 21 12:45:12 PM PDT 24
Peak memory 201432 kb
Host smart-baaf3b2c-1c24-4f0e-bcb1-c334d347993c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367682660 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.2367682660
Directory /workspace/24.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.adc_ctrl_clock_gating.2975615058
Short name T757
Test name
Test status
Simulation time 520159527198 ps
CPU time 519.33 seconds
Started Mar 21 12:45:13 PM PDT 24
Finished Mar 21 12:53:52 PM PDT 24
Peak memory 201780 kb
Host smart-672e5048-377b-4c4f-a9b6-e05473de7161
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975615058 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gat
ing.2975615058
Directory /workspace/24.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_both.650869678
Short name T593
Test name
Test status
Simulation time 599632938953 ps
CPU time 330.44 seconds
Started Mar 21 12:45:13 PM PDT 24
Finished Mar 21 12:50:43 PM PDT 24
Peak memory 201784 kb
Host smart-6c661591-6793-4b90-984e-f7d268e6fb13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650869678 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.650869678
Directory /workspace/24.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt.4007769237
Short name T283
Test name
Test status
Simulation time 166283952117 ps
CPU time 180.72 seconds
Started Mar 21 12:45:12 PM PDT 24
Finished Mar 21 12:48:13 PM PDT 24
Peak memory 201708 kb
Host smart-41be3be2-d7cc-4d17-8397-7eda27fe6c78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007769237 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.4007769237
Directory /workspace/24.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt_fixed.2820156128
Short name T659
Test name
Test status
Simulation time 487609263675 ps
CPU time 280.46 seconds
Started Mar 21 12:45:13 PM PDT 24
Finished Mar 21 12:49:53 PM PDT 24
Peak memory 201736 kb
Host smart-2a355dbd-7d28-45b6-9f8c-5690e63ec81a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820156128 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interru
pt_fixed.2820156128
Directory /workspace/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled.3485511125
Short name T458
Test name
Test status
Simulation time 484641049675 ps
CPU time 1085.29 seconds
Started Mar 21 12:45:10 PM PDT 24
Finished Mar 21 01:03:16 PM PDT 24
Peak memory 201720 kb
Host smart-b14a38cb-8957-4157-a067-411534a4f9ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485511125 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.3485511125
Directory /workspace/24.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.3126612865
Short name T447
Test name
Test status
Simulation time 162307849228 ps
CPU time 81.02 seconds
Started Mar 21 12:45:13 PM PDT 24
Finished Mar 21 12:46:35 PM PDT 24
Peak memory 201768 kb
Host smart-5006dc72-dc55-4760-86cd-fcd06fd7a0dc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126612865 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fix
ed.3126612865
Directory /workspace/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup.3884901311
Short name T730
Test name
Test status
Simulation time 536306990744 ps
CPU time 317.42 seconds
Started Mar 21 12:45:21 PM PDT 24
Finished Mar 21 12:50:39 PM PDT 24
Peak memory 201740 kb
Host smart-4359e557-9349-4658-86e4-f3f21a707edb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884901311 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters
_wakeup.3884901311
Directory /workspace/24.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup_fixed.383690211
Short name T421
Test name
Test status
Simulation time 600261528522 ps
CPU time 672.32 seconds
Started Mar 21 12:45:10 PM PDT 24
Finished Mar 21 12:56:23 PM PDT 24
Peak memory 201760 kb
Host smart-d95dee77-d5f8-4a3b-b872-0f9de3f2cfae
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383690211 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
adc_ctrl_filters_wakeup_fixed.383690211
Directory /workspace/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_fsm_reset.777940677
Short name T463
Test name
Test status
Simulation time 82584531536 ps
CPU time 386.83 seconds
Started Mar 21 12:45:13 PM PDT 24
Finished Mar 21 12:51:40 PM PDT 24
Peak memory 202096 kb
Host smart-8d584026-36f4-49de-a4b9-23bb4853f03d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777940677 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.777940677
Directory /workspace/24.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_lowpower_counter.3004927999
Short name T27
Test name
Test status
Simulation time 38258607237 ps
CPU time 78.34 seconds
Started Mar 21 12:45:10 PM PDT 24
Finished Mar 21 12:46:28 PM PDT 24
Peak memory 201592 kb
Host smart-2cf7c345-b084-48b5-b7b4-11af75d70004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004927999 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.3004927999
Directory /workspace/24.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_poweron_counter.837111213
Short name T7
Test name
Test status
Simulation time 4190159093 ps
CPU time 4 seconds
Started Mar 21 12:45:21 PM PDT 24
Finished Mar 21 12:45:25 PM PDT 24
Peak memory 201468 kb
Host smart-2e3f57bf-8f5f-43ae-80b7-ae1e4f8a9a43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837111213 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.837111213
Directory /workspace/24.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_smoke.574940681
Short name T719
Test name
Test status
Simulation time 5657763203 ps
CPU time 7.4 seconds
Started Mar 21 12:45:14 PM PDT 24
Finished Mar 21 12:45:21 PM PDT 24
Peak memory 201532 kb
Host smart-1c82088d-0aad-41b2-a1da-d1f40d687f9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574940681 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.574940681
Directory /workspace/24.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.2000989184
Short name T33
Test name
Test status
Simulation time 34225097794 ps
CPU time 100.54 seconds
Started Mar 21 12:45:09 PM PDT 24
Finished Mar 21 12:46:50 PM PDT 24
Peak memory 210516 kb
Host smart-d3acef03-9c1a-4fe4-a1c1-aca012a7eb40
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000989184 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all_with_rand_reset.2000989184
Directory /workspace/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_alert_test.1655760071
Short name T701
Test name
Test status
Simulation time 337710228 ps
CPU time 0.86 seconds
Started Mar 21 12:45:31 PM PDT 24
Finished Mar 21 12:45:32 PM PDT 24
Peak memory 201348 kb
Host smart-e0c39324-ac5d-47da-b232-b5839273a5af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655760071 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.1655760071
Directory /workspace/25.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.adc_ctrl_clock_gating.2169567988
Short name T633
Test name
Test status
Simulation time 165192915225 ps
CPU time 94.83 seconds
Started Mar 21 12:45:13 PM PDT 24
Finished Mar 21 12:46:48 PM PDT 24
Peak memory 201792 kb
Host smart-55f3c8c3-df15-4845-b746-512b33481711
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169567988 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gat
ing.2169567988
Directory /workspace/25.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt.424278314
Short name T727
Test name
Test status
Simulation time 481758978358 ps
CPU time 1143.63 seconds
Started Mar 21 12:45:14 PM PDT 24
Finished Mar 21 01:04:19 PM PDT 24
Peak memory 201788 kb
Host smart-1eea7352-63fe-4b17-a64c-3d44390a4183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424278314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.424278314
Directory /workspace/25.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt_fixed.1327839071
Short name T384
Test name
Test status
Simulation time 490881859045 ps
CPU time 575.17 seconds
Started Mar 21 12:45:21 PM PDT 24
Finished Mar 21 12:54:56 PM PDT 24
Peak memory 201712 kb
Host smart-f5e142ad-32a1-4ca3-b424-11fddea14788
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327839071 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interru
pt_fixed.1327839071
Directory /workspace/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled.1713167196
Short name T179
Test name
Test status
Simulation time 498624797759 ps
CPU time 238.59 seconds
Started Mar 21 12:45:13 PM PDT 24
Finished Mar 21 12:49:12 PM PDT 24
Peak memory 201796 kb
Host smart-5668ff2b-c12e-42d4-bc20-25a372c642df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713167196 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.1713167196
Directory /workspace/25.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled_fixed.3725317912
Short name T661
Test name
Test status
Simulation time 167730355661 ps
CPU time 48.06 seconds
Started Mar 21 12:45:13 PM PDT 24
Finished Mar 21 12:46:01 PM PDT 24
Peak memory 201800 kb
Host smart-62576d5a-3315-42d4-9a3b-d7c027cc923a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725317912 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fix
ed.3725317912
Directory /workspace/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup.827810512
Short name T103
Test name
Test status
Simulation time 387133827757 ps
CPU time 237.45 seconds
Started Mar 21 12:45:13 PM PDT 24
Finished Mar 21 12:49:10 PM PDT 24
Peak memory 202020 kb
Host smart-52406a11-6f05-4bb6-ab80-86d531724872
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827810512 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_
wakeup.827810512
Directory /workspace/25.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup_fixed.205061296
Short name T707
Test name
Test status
Simulation time 419324583433 ps
CPU time 246.83 seconds
Started Mar 21 12:45:13 PM PDT 24
Finished Mar 21 12:49:21 PM PDT 24
Peak memory 201728 kb
Host smart-7bbd4377-8013-4a05-9a62-00a65d5915d5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205061296 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
adc_ctrl_filters_wakeup_fixed.205061296
Directory /workspace/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_fsm_reset.2818414833
Short name T377
Test name
Test status
Simulation time 107369942499 ps
CPU time 552.23 seconds
Started Mar 21 12:45:14 PM PDT 24
Finished Mar 21 12:54:26 PM PDT 24
Peak memory 202012 kb
Host smart-7404f1ba-7c54-4d07-8405-04c92ee7bc96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818414833 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.2818414833
Directory /workspace/25.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_lowpower_counter.2545449901
Short name T553
Test name
Test status
Simulation time 22505911769 ps
CPU time 6.68 seconds
Started Mar 21 12:45:13 PM PDT 24
Finished Mar 21 12:45:20 PM PDT 24
Peak memory 201596 kb
Host smart-ba842209-9f0d-43f9-98c0-211047ce2905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545449901 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.2545449901
Directory /workspace/25.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_poweron_counter.3335887204
Short name T339
Test name
Test status
Simulation time 4793003743 ps
CPU time 3.09 seconds
Started Mar 21 12:45:12 PM PDT 24
Finished Mar 21 12:45:15 PM PDT 24
Peak memory 201500 kb
Host smart-1b054c12-ff0b-4066-8921-aad63cc8b61d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335887204 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.3335887204
Directory /workspace/25.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_smoke.3036189262
Short name T777
Test name
Test status
Simulation time 5570707978 ps
CPU time 13.82 seconds
Started Mar 21 12:45:12 PM PDT 24
Finished Mar 21 12:45:26 PM PDT 24
Peak memory 201608 kb
Host smart-6a51ba92-7aa1-4664-8bbb-a750b3e92456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036189262 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.3036189262
Directory /workspace/25.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all.2957144269
Short name T398
Test name
Test status
Simulation time 40989636159 ps
CPU time 89.42 seconds
Started Mar 21 12:45:30 PM PDT 24
Finished Mar 21 12:47:00 PM PDT 24
Peak memory 201624 kb
Host smart-24020f21-3a36-4bcb-b1e2-5d47542e3097
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957144269 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all
.2957144269
Directory /workspace/25.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.147899269
Short name T19
Test name
Test status
Simulation time 72376021679 ps
CPU time 160.24 seconds
Started Mar 21 12:45:31 PM PDT 24
Finished Mar 21 12:48:11 PM PDT 24
Peak memory 210420 kb
Host smart-82b88d58-1487-4507-a2a4-2b7ea6fae422
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147899269 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all_with_rand_reset.147899269
Directory /workspace/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_alert_test.1003290071
Short name T367
Test name
Test status
Simulation time 459562939 ps
CPU time 1.73 seconds
Started Mar 21 12:45:32 PM PDT 24
Finished Mar 21 12:45:34 PM PDT 24
Peak memory 201392 kb
Host smart-7da35466-31c5-466b-8109-8c8e6278e4b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003290071 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.1003290071
Directory /workspace/26.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.adc_ctrl_clock_gating.1156013700
Short name T147
Test name
Test status
Simulation time 186358719674 ps
CPU time 99.76 seconds
Started Mar 21 12:45:28 PM PDT 24
Finished Mar 21 12:47:08 PM PDT 24
Peak memory 201864 kb
Host smart-c31ca965-9912-4f6f-b722-3f1098b19b98
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156013700 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gat
ing.1156013700
Directory /workspace/26.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_both.355623060
Short name T278
Test name
Test status
Simulation time 167095525544 ps
CPU time 109.1 seconds
Started Mar 21 12:45:29 PM PDT 24
Finished Mar 21 12:47:18 PM PDT 24
Peak memory 201668 kb
Host smart-4dd86c87-0367-4bee-891d-4de31c539b1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355623060 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.355623060
Directory /workspace/26.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt.2810848211
Short name T468
Test name
Test status
Simulation time 162728724016 ps
CPU time 206.09 seconds
Started Mar 21 12:45:30 PM PDT 24
Finished Mar 21 12:48:57 PM PDT 24
Peak memory 201680 kb
Host smart-68e1cdcd-cb4b-4035-aaea-b0adb0cfa065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810848211 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.2810848211
Directory /workspace/26.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt_fixed.428583897
Short name T622
Test name
Test status
Simulation time 328613209106 ps
CPU time 82.18 seconds
Started Mar 21 12:45:31 PM PDT 24
Finished Mar 21 12:46:54 PM PDT 24
Peak memory 201768 kb
Host smart-f9638967-e90c-48e9-98ed-8e06695881d3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=428583897 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrup
t_fixed.428583897
Directory /workspace/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled_fixed.1278361908
Short name T174
Test name
Test status
Simulation time 332794338096 ps
CPU time 195.67 seconds
Started Mar 21 12:45:29 PM PDT 24
Finished Mar 21 12:48:45 PM PDT 24
Peak memory 201812 kb
Host smart-2723d304-3d73-44f8-85eb-e28eb24cc57c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278361908 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fix
ed.1278361908
Directory /workspace/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup_fixed.1937012900
Short name T508
Test name
Test status
Simulation time 609357837998 ps
CPU time 1377.61 seconds
Started Mar 21 12:45:31 PM PDT 24
Finished Mar 21 01:08:29 PM PDT 24
Peak memory 201612 kb
Host smart-25e6bfbf-b593-47ce-8994-c7b386ebdc06
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937012900 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26
.adc_ctrl_filters_wakeup_fixed.1937012900
Directory /workspace/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_fsm_reset.4105950037
Short name T324
Test name
Test status
Simulation time 76845399887 ps
CPU time 397.06 seconds
Started Mar 21 12:45:31 PM PDT 24
Finished Mar 21 12:52:09 PM PDT 24
Peak memory 201960 kb
Host smart-a2d90308-aa99-486c-9661-836ccfcf8729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105950037 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.4105950037
Directory /workspace/26.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_lowpower_counter.3252111404
Short name T356
Test name
Test status
Simulation time 42048715733 ps
CPU time 6.86 seconds
Started Mar 21 12:45:30 PM PDT 24
Finished Mar 21 12:45:37 PM PDT 24
Peak memory 201588 kb
Host smart-49dd7e95-f11e-4be3-8787-5a0728d8895c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252111404 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.3252111404
Directory /workspace/26.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_poweron_counter.3213454320
Short name T717
Test name
Test status
Simulation time 4333489850 ps
CPU time 11.12 seconds
Started Mar 21 12:45:34 PM PDT 24
Finished Mar 21 12:45:46 PM PDT 24
Peak memory 201528 kb
Host smart-ab9da933-bfe3-4367-bc8c-93cdead01f06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213454320 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.3213454320
Directory /workspace/26.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_smoke.367650055
Short name T201
Test name
Test status
Simulation time 5911344932 ps
CPU time 15.16 seconds
Started Mar 21 12:45:29 PM PDT 24
Finished Mar 21 12:45:44 PM PDT 24
Peak memory 201516 kb
Host smart-79062c4c-5516-488b-97f4-8bf23e4c3ebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367650055 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.367650055
Directory /workspace/26.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all.4247170693
Short name T159
Test name
Test status
Simulation time 329852596621 ps
CPU time 736.54 seconds
Started Mar 21 12:45:37 PM PDT 24
Finished Mar 21 12:57:54 PM PDT 24
Peak memory 201788 kb
Host smart-e3a413b4-5547-43ce-b6c2-635c9ebd810f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247170693 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all
.4247170693
Directory /workspace/26.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.1698278471
Short name T435
Test name
Test status
Simulation time 153286453266 ps
CPU time 406.56 seconds
Started Mar 21 12:45:30 PM PDT 24
Finished Mar 21 12:52:17 PM PDT 24
Peak memory 210496 kb
Host smart-d2fcfb7e-2750-4a18-9311-a587574c9235
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698278471 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all_with_rand_reset.1698278471
Directory /workspace/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_alert_test.3897187249
Short name T157
Test name
Test status
Simulation time 433948386 ps
CPU time 0.85 seconds
Started Mar 21 12:45:30 PM PDT 24
Finished Mar 21 12:45:31 PM PDT 24
Peak memory 201368 kb
Host smart-d32449eb-0197-446e-aea2-eb06f40d0a9b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897187249 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.3897187249
Directory /workspace/27.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.adc_ctrl_clock_gating.2716321346
Short name T306
Test name
Test status
Simulation time 335649207851 ps
CPU time 127.9 seconds
Started Mar 21 12:45:31 PM PDT 24
Finished Mar 21 12:47:39 PM PDT 24
Peak memory 201804 kb
Host smart-211f7a36-7b16-428c-939d-49eaa1b9d278
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716321346 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gat
ing.2716321346
Directory /workspace/27.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_both.2356027406
Short name T555
Test name
Test status
Simulation time 338945651085 ps
CPU time 709.2 seconds
Started Mar 21 12:45:31 PM PDT 24
Finished Mar 21 12:57:21 PM PDT 24
Peak memory 201708 kb
Host smart-c146c9b4-25be-4141-9f97-9ec70a5b5044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356027406 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.2356027406
Directory /workspace/27.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt_fixed.3231155282
Short name T589
Test name
Test status
Simulation time 325689873584 ps
CPU time 694.8 seconds
Started Mar 21 12:45:35 PM PDT 24
Finished Mar 21 12:57:09 PM PDT 24
Peak memory 201696 kb
Host smart-217e98e2-b1d9-41a6-a2eb-71a3bd92eb41
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231155282 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interru
pt_fixed.3231155282
Directory /workspace/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled.246777234
Short name T176
Test name
Test status
Simulation time 334153146707 ps
CPU time 192.34 seconds
Started Mar 21 12:45:30 PM PDT 24
Finished Mar 21 12:48:43 PM PDT 24
Peak memory 201800 kb
Host smart-91f7af8a-c616-4d54-9ba8-f512e59e6492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246777234 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.246777234
Directory /workspace/27.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled_fixed.3596484387
Short name T712
Test name
Test status
Simulation time 165397901358 ps
CPU time 102.9 seconds
Started Mar 21 12:45:31 PM PDT 24
Finished Mar 21 12:47:14 PM PDT 24
Peak memory 201784 kb
Host smart-06948633-2a56-4368-aac5-5354617c6501
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596484387 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fix
ed.3596484387
Directory /workspace/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup.486030556
Short name T269
Test name
Test status
Simulation time 167193309508 ps
CPU time 110.75 seconds
Started Mar 21 12:45:42 PM PDT 24
Finished Mar 21 12:47:32 PM PDT 24
Peak memory 201764 kb
Host smart-09c98eb1-6d26-4a1c-b651-5007f009b913
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486030556 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_
wakeup.486030556
Directory /workspace/27.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup_fixed.3045222656
Short name T539
Test name
Test status
Simulation time 402497261710 ps
CPU time 273.72 seconds
Started Mar 21 12:45:28 PM PDT 24
Finished Mar 21 12:50:02 PM PDT 24
Peak memory 201792 kb
Host smart-ae8d316c-3860-46ff-a8c7-349cb57d353b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045222656 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27
.adc_ctrl_filters_wakeup_fixed.3045222656
Directory /workspace/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_fsm_reset.822583026
Short name T763
Test name
Test status
Simulation time 79219009590 ps
CPU time 299.63 seconds
Started Mar 21 12:45:31 PM PDT 24
Finished Mar 21 12:50:31 PM PDT 24
Peak memory 202088 kb
Host smart-df940601-5276-4fac-ba5e-ce2c56e35e3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822583026 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.822583026
Directory /workspace/27.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_lowpower_counter.2496176900
Short name T476
Test name
Test status
Simulation time 37553462940 ps
CPU time 11.96 seconds
Started Mar 21 12:45:38 PM PDT 24
Finished Mar 21 12:45:50 PM PDT 24
Peak memory 201536 kb
Host smart-7909d424-5683-44ba-8576-72f2b92357f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496176900 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.2496176900
Directory /workspace/27.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_poweron_counter.2054087968
Short name T698
Test name
Test status
Simulation time 5083958219 ps
CPU time 6.79 seconds
Started Mar 21 12:45:31 PM PDT 24
Finished Mar 21 12:45:38 PM PDT 24
Peak memory 201456 kb
Host smart-8c992a54-e38d-40fa-946a-f1a47cf26b49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054087968 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.2054087968
Directory /workspace/27.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_smoke.3223391196
Short name T768
Test name
Test status
Simulation time 5788697275 ps
CPU time 12.7 seconds
Started Mar 21 12:45:44 PM PDT 24
Finished Mar 21 12:45:57 PM PDT 24
Peak memory 201588 kb
Host smart-bf3bbc50-63a4-478c-b15c-8d61c96fba1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223391196 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.3223391196
Directory /workspace/27.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all.3626154692
Short name T756
Test name
Test status
Simulation time 242057421700 ps
CPU time 380.49 seconds
Started Mar 21 12:45:37 PM PDT 24
Finished Mar 21 12:51:58 PM PDT 24
Peak memory 202020 kb
Host smart-b1424f11-47ae-4003-a1fd-2dc810774fd5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626154692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all
.3626154692
Directory /workspace/27.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.4060804229
Short name T32
Test name
Test status
Simulation time 72848979010 ps
CPU time 96.5 seconds
Started Mar 21 12:45:30 PM PDT 24
Finished Mar 21 12:47:07 PM PDT 24
Peak memory 202288 kb
Host smart-cf2bc130-fc49-4927-a4c3-a65f4aa3645c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060804229 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all_with_rand_reset.4060804229
Directory /workspace/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_alert_test.1132537741
Short name T423
Test name
Test status
Simulation time 486595337 ps
CPU time 1.69 seconds
Started Mar 21 12:45:43 PM PDT 24
Finished Mar 21 12:45:44 PM PDT 24
Peak memory 201412 kb
Host smart-cb311f17-28b3-4a76-8113-97d4641b9908
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132537741 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.1132537741
Directory /workspace/28.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.adc_ctrl_clock_gating.3928698525
Short name T250
Test name
Test status
Simulation time 191756061770 ps
CPU time 454.18 seconds
Started Mar 21 12:45:44 PM PDT 24
Finished Mar 21 12:53:18 PM PDT 24
Peak memory 201860 kb
Host smart-af8d7117-0d49-43c1-98f1-4990f38ab2c0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928698525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gat
ing.3928698525
Directory /workspace/28.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt.704686222
Short name T284
Test name
Test status
Simulation time 488783581252 ps
CPU time 332.07 seconds
Started Mar 21 12:45:46 PM PDT 24
Finished Mar 21 12:51:18 PM PDT 24
Peak memory 201712 kb
Host smart-3ac0bffb-3a71-4ba1-87b9-917010ba0664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704686222 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.704686222
Directory /workspace/28.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt_fixed.4246816793
Short name T364
Test name
Test status
Simulation time 168257802983 ps
CPU time 196.69 seconds
Started Mar 21 12:45:43 PM PDT 24
Finished Mar 21 12:49:00 PM PDT 24
Peak memory 201876 kb
Host smart-f1db751b-a732-40cd-96b3-dfd6043411cb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246816793 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interru
pt_fixed.4246816793
Directory /workspace/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled.973825078
Short name T782
Test name
Test status
Simulation time 327587047984 ps
CPU time 790.82 seconds
Started Mar 21 12:45:29 PM PDT 24
Finished Mar 21 12:58:40 PM PDT 24
Peak memory 201704 kb
Host smart-49c4264a-c30b-4d77-beef-70aa4763a5fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973825078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.973825078
Directory /workspace/28.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.3415325119
Short name T714
Test name
Test status
Simulation time 494603620425 ps
CPU time 1202.4 seconds
Started Mar 21 12:45:45 PM PDT 24
Finished Mar 21 01:05:47 PM PDT 24
Peak memory 201720 kb
Host smart-b51509ea-3952-413e-9a43-d6a3940f3871
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415325119 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fix
ed.3415325119
Directory /workspace/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup.2391662800
Short name T186
Test name
Test status
Simulation time 195870090666 ps
CPU time 116.62 seconds
Started Mar 21 12:45:44 PM PDT 24
Finished Mar 21 12:47:41 PM PDT 24
Peak memory 201788 kb
Host smart-df9b440c-258a-4ec4-871c-ee45f6c9dce7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391662800 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters
_wakeup.2391662800
Directory /workspace/28.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.1099031694
Short name T441
Test name
Test status
Simulation time 410448799914 ps
CPU time 968.43 seconds
Started Mar 21 12:45:46 PM PDT 24
Finished Mar 21 01:01:54 PM PDT 24
Peak memory 201796 kb
Host smart-670d06ae-be34-4494-a9c2-c448e412b22b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099031694 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28
.adc_ctrl_filters_wakeup_fixed.1099031694
Directory /workspace/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_fsm_reset.2074059077
Short name T471
Test name
Test status
Simulation time 83497239324 ps
CPU time 270.76 seconds
Started Mar 21 12:45:44 PM PDT 24
Finished Mar 21 12:50:15 PM PDT 24
Peak memory 202036 kb
Host smart-eccf19f0-839e-4cbc-b8af-a88fc137c545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074059077 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.2074059077
Directory /workspace/28.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_lowpower_counter.3846076607
Short name T569
Test name
Test status
Simulation time 28559854206 ps
CPU time 17.01 seconds
Started Mar 21 12:45:53 PM PDT 24
Finished Mar 21 12:46:10 PM PDT 24
Peak memory 201504 kb
Host smart-c3757704-2346-41ad-9307-9a5fbad5ebc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846076607 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.3846076607
Directory /workspace/28.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_poweron_counter.4191395538
Short name T668
Test name
Test status
Simulation time 4219597158 ps
CPU time 6.33 seconds
Started Mar 21 12:45:48 PM PDT 24
Finished Mar 21 12:45:55 PM PDT 24
Peak memory 201448 kb
Host smart-781cf581-4c3f-46bd-a8cb-ece4b3ab3055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191395538 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.4191395538
Directory /workspace/28.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_smoke.1304729817
Short name T560
Test name
Test status
Simulation time 5940752349 ps
CPU time 4.37 seconds
Started Mar 21 12:45:31 PM PDT 24
Finished Mar 21 12:45:36 PM PDT 24
Peak memory 201536 kb
Host smart-e32f8929-915b-40b5-8d67-cb7209deda5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304729817 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.1304729817
Directory /workspace/28.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all.1824347565
Short name T648
Test name
Test status
Simulation time 337535221456 ps
CPU time 400.05 seconds
Started Mar 21 12:45:47 PM PDT 24
Finished Mar 21 12:52:27 PM PDT 24
Peak memory 201800 kb
Host smart-e314b33a-97ad-47c1-9149-543fed6ecc03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824347565 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all
.1824347565
Directory /workspace/28.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.3222978873
Short name T656
Test name
Test status
Simulation time 117093035300 ps
CPU time 129.42 seconds
Started Mar 21 12:45:43 PM PDT 24
Finished Mar 21 12:47:53 PM PDT 24
Peak memory 210112 kb
Host smart-17a8e4ae-a181-4960-9333-2f09a350b722
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222978873 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all_with_rand_reset.3222978873
Directory /workspace/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_alert_test.4234331918
Short name T155
Test name
Test status
Simulation time 393101291 ps
CPU time 0.83 seconds
Started Mar 21 12:45:57 PM PDT 24
Finished Mar 21 12:45:58 PM PDT 24
Peak memory 201496 kb
Host smart-65ee5fcb-0fd7-467a-9f3b-d811e28ce75b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234331918 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.4234331918
Directory /workspace/29.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.adc_ctrl_clock_gating.690024226
Short name T300
Test name
Test status
Simulation time 183070039434 ps
CPU time 107.57 seconds
Started Mar 21 12:45:50 PM PDT 24
Finished Mar 21 12:47:38 PM PDT 24
Peak memory 201724 kb
Host smart-d73d3b8d-51be-4697-b3fb-fd539d0a2270
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690024226 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gati
ng.690024226
Directory /workspace/29.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_both.4072082804
Short name T235
Test name
Test status
Simulation time 348533486353 ps
CPU time 758.17 seconds
Started Mar 21 12:45:45 PM PDT 24
Finished Mar 21 12:58:24 PM PDT 24
Peak memory 201788 kb
Host smart-5e24e7d3-985f-42b9-805d-3fa8a48818ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072082804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.4072082804
Directory /workspace/29.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt.2313587873
Short name T100
Test name
Test status
Simulation time 329439206199 ps
CPU time 558.73 seconds
Started Mar 21 12:45:44 PM PDT 24
Finished Mar 21 12:55:03 PM PDT 24
Peak memory 201788 kb
Host smart-81416860-5e75-4cd4-8953-d14cf364913f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313587873 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.2313587873
Directory /workspace/29.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt_fixed.3497120363
Short name T566
Test name
Test status
Simulation time 163859044524 ps
CPU time 381.34 seconds
Started Mar 21 12:45:43 PM PDT 24
Finished Mar 21 12:52:05 PM PDT 24
Peak memory 201788 kb
Host smart-f1177a15-58b3-4f2e-a4e7-84d51dc78f0a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497120363 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interru
pt_fixed.3497120363
Directory /workspace/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled.306520847
Short name T95
Test name
Test status
Simulation time 492559308232 ps
CPU time 1088.34 seconds
Started Mar 21 12:45:45 PM PDT 24
Finished Mar 21 01:03:53 PM PDT 24
Peak memory 201792 kb
Host smart-7c169dcb-aed4-4b2d-8eaf-4958a1a842b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306520847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.306520847
Directory /workspace/29.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.3292519827
Short name T781
Test name
Test status
Simulation time 322438213176 ps
CPU time 691.65 seconds
Started Mar 21 12:45:43 PM PDT 24
Finished Mar 21 12:57:14 PM PDT 24
Peak memory 201912 kb
Host smart-4349d369-146f-46f1-9b0d-a985eb45712f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292519827 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fix
ed.3292519827
Directory /workspace/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup_fixed.127175318
Short name T405
Test name
Test status
Simulation time 197875012195 ps
CPU time 469.61 seconds
Started Mar 21 12:45:42 PM PDT 24
Finished Mar 21 12:53:32 PM PDT 24
Peak memory 201776 kb
Host smart-3fa03cf0-7572-4bd1-aa8a-8096ecf98eb8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127175318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
adc_ctrl_filters_wakeup_fixed.127175318
Directory /workspace/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_fsm_reset.1986648587
Short name T524
Test name
Test status
Simulation time 104538654165 ps
CPU time 393.95 seconds
Started Mar 21 12:45:44 PM PDT 24
Finished Mar 21 12:52:18 PM PDT 24
Peak memory 202020 kb
Host smart-e7a68913-3435-4aca-9248-0d0ff600bad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986648587 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.1986648587
Directory /workspace/29.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_lowpower_counter.3585426913
Short name T779
Test name
Test status
Simulation time 38419411567 ps
CPU time 10.43 seconds
Started Mar 21 12:45:45 PM PDT 24
Finished Mar 21 12:45:56 PM PDT 24
Peak memory 201488 kb
Host smart-714283b4-ce8c-4588-804f-c983d2b0d9f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585426913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.3585426913
Directory /workspace/29.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_poweron_counter.3481616863
Short name T599
Test name
Test status
Simulation time 4158652949 ps
CPU time 10.16 seconds
Started Mar 21 12:45:53 PM PDT 24
Finished Mar 21 12:46:03 PM PDT 24
Peak memory 201448 kb
Host smart-b6689bb9-e694-4462-a498-b12fc36c4e23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481616863 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.3481616863
Directory /workspace/29.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_smoke.2651243275
Short name T124
Test name
Test status
Simulation time 6092236786 ps
CPU time 6.96 seconds
Started Mar 21 12:45:42 PM PDT 24
Finished Mar 21 12:45:49 PM PDT 24
Peak memory 201520 kb
Host smart-8bf65b8b-eb54-44e3-a4a1-cd7ca2b648eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651243275 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.2651243275
Directory /workspace/29.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all.112014157
Short name T415
Test name
Test status
Simulation time 494492230796 ps
CPU time 1162.49 seconds
Started Mar 21 12:45:57 PM PDT 24
Finished Mar 21 01:05:19 PM PDT 24
Peak memory 201728 kb
Host smart-51444189-0772-4cab-a3ed-2ca8de8f13d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112014157 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all.
112014157
Directory /workspace/29.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.1502385197
Short name T21
Test name
Test status
Simulation time 428303699491 ps
CPU time 416.78 seconds
Started Mar 21 12:45:44 PM PDT 24
Finished Mar 21 12:52:41 PM PDT 24
Peak memory 218264 kb
Host smart-6fe10434-1de8-4811-82f5-c663ce2636f6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502385197 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all_with_rand_reset.1502385197
Directory /workspace/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_alert_test.153644252
Short name T767
Test name
Test status
Simulation time 587821406 ps
CPU time 0.73 seconds
Started Mar 21 12:44:18 PM PDT 24
Finished Mar 21 12:44:19 PM PDT 24
Peak memory 201500 kb
Host smart-ff385267-3104-41f3-a600-e19226ef9388
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153644252 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.153644252
Directory /workspace/3.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt.2490791630
Short name T432
Test name
Test status
Simulation time 163895070401 ps
CPU time 405.26 seconds
Started Mar 21 12:44:22 PM PDT 24
Finished Mar 21 12:51:08 PM PDT 24
Peak memory 201688 kb
Host smart-be5f8a8c-e580-4614-90f6-220d2ac668c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490791630 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.2490791630
Directory /workspace/3.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt_fixed.3829017994
Short name T726
Test name
Test status
Simulation time 162870112688 ps
CPU time 348.97 seconds
Started Mar 21 12:44:23 PM PDT 24
Finished Mar 21 12:50:12 PM PDT 24
Peak memory 201664 kb
Host smart-7ab21ccc-04e0-4e49-b280-33498e5b0e43
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829017994 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrup
t_fixed.3829017994
Directory /workspace/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled.3839540409
Short name T127
Test name
Test status
Simulation time 327587802648 ps
CPU time 182.71 seconds
Started Mar 21 12:44:09 PM PDT 24
Finished Mar 21 12:47:12 PM PDT 24
Peak memory 201800 kb
Host smart-7610f11d-5807-4394-9b45-e427b24fb1dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839540409 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.3839540409
Directory /workspace/3.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled_fixed.1505025697
Short name T504
Test name
Test status
Simulation time 484824416681 ps
CPU time 1163.39 seconds
Started Mar 21 12:44:09 PM PDT 24
Finished Mar 21 01:03:33 PM PDT 24
Peak memory 201792 kb
Host smart-fa1e4c28-bf9c-43bc-915f-8262e05bb15d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505025697 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixe
d.1505025697
Directory /workspace/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup.3377349213
Short name T291
Test name
Test status
Simulation time 343992444036 ps
CPU time 837.45 seconds
Started Mar 21 12:44:10 PM PDT 24
Finished Mar 21 12:58:07 PM PDT 24
Peak memory 201768 kb
Host smart-75d1cc68-a5c4-4356-bd63-104183b87884
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377349213 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_
wakeup.3377349213
Directory /workspace/3.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup_fixed.3570211477
Short name T450
Test name
Test status
Simulation time 198791299986 ps
CPU time 112.91 seconds
Started Mar 21 12:44:08 PM PDT 24
Finished Mar 21 12:46:01 PM PDT 24
Peak memory 201704 kb
Host smart-b89abde7-766c-4233-8202-26356ca081e1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570211477 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.
adc_ctrl_filters_wakeup_fixed.3570211477
Directory /workspace/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_fsm_reset.1125783045
Short name T609
Test name
Test status
Simulation time 132582367680 ps
CPU time 406.14 seconds
Started Mar 21 12:44:08 PM PDT 24
Finished Mar 21 12:50:54 PM PDT 24
Peak memory 202004 kb
Host smart-5ee66d38-5c88-4940-80bc-a29cc490b5ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125783045 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.1125783045
Directory /workspace/3.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_lowpower_counter.591263635
Short name T392
Test name
Test status
Simulation time 41713233259 ps
CPU time 32.08 seconds
Started Mar 21 12:44:09 PM PDT 24
Finished Mar 21 12:44:41 PM PDT 24
Peak memory 201492 kb
Host smart-43aa0ba4-739f-451f-9ae5-502f20161df2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591263635 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.591263635
Directory /workspace/3.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_poweron_counter.3464916250
Short name T357
Test name
Test status
Simulation time 5267527997 ps
CPU time 13.72 seconds
Started Mar 21 12:44:09 PM PDT 24
Finished Mar 21 12:44:23 PM PDT 24
Peak memory 201504 kb
Host smart-7dd15386-5bc1-4409-a280-289921dceee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464916250 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.3464916250
Directory /workspace/3.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_sec_cm.3945832641
Short name T64
Test name
Test status
Simulation time 4757672318 ps
CPU time 1.83 seconds
Started Mar 21 12:44:21 PM PDT 24
Finished Mar 21 12:44:23 PM PDT 24
Peak memory 217272 kb
Host smart-ff050a63-e034-4235-9af6-81092d7f459f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945832641 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.3945832641
Directory /workspace/3.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.adc_ctrl_smoke.2550483018
Short name T760
Test name
Test status
Simulation time 5817437833 ps
CPU time 4.58 seconds
Started Mar 21 12:44:09 PM PDT 24
Finished Mar 21 12:44:14 PM PDT 24
Peak memory 201528 kb
Host smart-cd1748d2-2e3c-450c-a73b-8c940362c524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550483018 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.2550483018
Directory /workspace/3.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.4148412937
Short name T25
Test name
Test status
Simulation time 264399715868 ps
CPU time 418.62 seconds
Started Mar 21 12:44:23 PM PDT 24
Finished Mar 21 12:51:22 PM PDT 24
Peak memory 210320 kb
Host smart-ed75148c-adf8-4f4c-b8d5-4cda3541386f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148412937 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all_with_rand_reset.4148412937
Directory /workspace/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_alert_test.2989994472
Short name T592
Test name
Test status
Simulation time 334556253 ps
CPU time 1.06 seconds
Started Mar 21 12:45:57 PM PDT 24
Finished Mar 21 12:45:58 PM PDT 24
Peak memory 201508 kb
Host smart-8ec95f65-351c-461c-bf57-e1e07540ca21
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989994472 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.2989994472
Directory /workspace/30.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.adc_ctrl_clock_gating.3381488606
Short name T288
Test name
Test status
Simulation time 521241399312 ps
CPU time 803 seconds
Started Mar 21 12:45:55 PM PDT 24
Finished Mar 21 12:59:18 PM PDT 24
Peak memory 201948 kb
Host smart-2d887fcf-569a-4a50-acb2-80d36c7c8bc9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381488606 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gat
ing.3381488606
Directory /workspace/30.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_both.4003078457
Short name T97
Test name
Test status
Simulation time 348917631689 ps
CPU time 841.22 seconds
Started Mar 21 12:46:22 PM PDT 24
Finished Mar 21 01:00:24 PM PDT 24
Peak memory 201788 kb
Host smart-d19008a0-b8d8-4351-a087-78fae13a1bb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003078457 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.4003078457
Directory /workspace/30.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt_fixed.3129951903
Short name T678
Test name
Test status
Simulation time 164276110273 ps
CPU time 370.28 seconds
Started Mar 21 12:46:00 PM PDT 24
Finished Mar 21 12:52:10 PM PDT 24
Peak memory 201676 kb
Host smart-6091fc16-3334-4514-a6cf-2bc50f456b66
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129951903 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interru
pt_fixed.3129951903
Directory /workspace/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled.707597435
Short name T153
Test name
Test status
Simulation time 488478396834 ps
CPU time 1122.96 seconds
Started Mar 21 12:45:55 PM PDT 24
Finished Mar 21 01:04:38 PM PDT 24
Peak memory 201872 kb
Host smart-57261050-3988-48a8-b797-5bef4e8f6d53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707597435 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.707597435
Directory /workspace/30.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled_fixed.2373313385
Short name T533
Test name
Test status
Simulation time 335421962107 ps
CPU time 47.58 seconds
Started Mar 21 12:45:55 PM PDT 24
Finished Mar 21 12:46:43 PM PDT 24
Peak memory 201804 kb
Host smart-2498716d-1212-4dd7-8f16-cea462cc9d70
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373313385 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fix
ed.2373313385
Directory /workspace/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup.1329915971
Short name T6
Test name
Test status
Simulation time 521526743006 ps
CPU time 255.01 seconds
Started Mar 21 12:45:57 PM PDT 24
Finished Mar 21 12:50:12 PM PDT 24
Peak memory 201720 kb
Host smart-001c1027-c84b-4558-8ac1-0a0885403683
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329915971 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters
_wakeup.1329915971
Directory /workspace/30.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup_fixed.1173237413
Short name T483
Test name
Test status
Simulation time 194321521799 ps
CPU time 471.89 seconds
Started Mar 21 12:45:58 PM PDT 24
Finished Mar 21 12:53:50 PM PDT 24
Peak memory 201696 kb
Host smart-b5eadcce-54c1-4e06-96d2-d14e052a8ea6
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173237413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30
.adc_ctrl_filters_wakeup_fixed.1173237413
Directory /workspace/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_fsm_reset.375338948
Short name T53
Test name
Test status
Simulation time 86960533382 ps
CPU time 453.94 seconds
Started Mar 21 12:46:01 PM PDT 24
Finished Mar 21 12:53:35 PM PDT 24
Peak memory 202104 kb
Host smart-23080471-ac65-4699-a4ed-d6d8a2118ef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375338948 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.375338948
Directory /workspace/30.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_lowpower_counter.584951827
Short name T620
Test name
Test status
Simulation time 43839380905 ps
CPU time 17.52 seconds
Started Mar 21 12:45:57 PM PDT 24
Finished Mar 21 12:46:14 PM PDT 24
Peak memory 201508 kb
Host smart-0073fc59-94e4-45ec-877d-725d9977d55d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584951827 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.584951827
Directory /workspace/30.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_poweron_counter.3816200325
Short name T469
Test name
Test status
Simulation time 3675114787 ps
CPU time 2.35 seconds
Started Mar 21 12:45:58 PM PDT 24
Finished Mar 21 12:46:00 PM PDT 24
Peak memory 201468 kb
Host smart-f0ac4569-f45e-423c-8511-438dc858c449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816200325 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.3816200325
Directory /workspace/30.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_smoke.2417405284
Short name T697
Test name
Test status
Simulation time 6028481016 ps
CPU time 7.9 seconds
Started Mar 21 12:45:55 PM PDT 24
Finished Mar 21 12:46:03 PM PDT 24
Peak memory 201548 kb
Host smart-c212568f-4e54-4744-ae65-9773353c1555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417405284 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.2417405284
Directory /workspace/30.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all.3248523726
Short name T541
Test name
Test status
Simulation time 529013379842 ps
CPU time 994.05 seconds
Started Mar 21 12:45:57 PM PDT 24
Finished Mar 21 01:02:31 PM PDT 24
Peak memory 201692 kb
Host smart-16bbb05f-96dd-4f4b-85c1-2e5b455663db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248523726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all
.3248523726
Directory /workspace/30.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.adc_ctrl_alert_test.3452051397
Short name T627
Test name
Test status
Simulation time 336490576 ps
CPU time 0.75 seconds
Started Mar 21 12:45:59 PM PDT 24
Finished Mar 21 12:46:00 PM PDT 24
Peak memory 201404 kb
Host smart-6a2a56f7-62c2-4152-8859-0f4f4391eced
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452051397 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.3452051397
Directory /workspace/31.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.adc_ctrl_clock_gating.3667264265
Short name T628
Test name
Test status
Simulation time 359811645951 ps
CPU time 242 seconds
Started Mar 21 12:47:36 PM PDT 24
Finished Mar 21 12:51:38 PM PDT 24
Peak memory 201632 kb
Host smart-a4042f62-6da0-45f5-bdfe-91d45ddfe6fc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667264265 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gat
ing.3667264265
Directory /workspace/31.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_both.2061047624
Short name T737
Test name
Test status
Simulation time 547992457518 ps
CPU time 1268.32 seconds
Started Mar 21 12:45:58 PM PDT 24
Finished Mar 21 01:07:07 PM PDT 24
Peak memory 201716 kb
Host smart-c89c4af9-4466-403e-a75f-ff6ef3c11d27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061047624 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.2061047624
Directory /workspace/31.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt.815394099
Short name T788
Test name
Test status
Simulation time 495253829399 ps
CPU time 1208.05 seconds
Started Mar 21 12:46:02 PM PDT 24
Finished Mar 21 01:06:10 PM PDT 24
Peak memory 201880 kb
Host smart-ffcf195c-881d-4018-84a8-c394c48c1f4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815394099 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.815394099
Directory /workspace/31.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt_fixed.1512407812
Short name T588
Test name
Test status
Simulation time 490940302779 ps
CPU time 1177.24 seconds
Started Mar 21 12:45:57 PM PDT 24
Finished Mar 21 01:05:35 PM PDT 24
Peak memory 201696 kb
Host smart-3b54673b-39b1-4b1b-a781-1f73f03fe79a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512407812 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interru
pt_fixed.1512407812
Directory /workspace/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled.2531484814
Short name T305
Test name
Test status
Simulation time 163117625298 ps
CPU time 104.95 seconds
Started Mar 21 12:45:55 PM PDT 24
Finished Mar 21 12:47:40 PM PDT 24
Peak memory 201704 kb
Host smart-0c1e2f5d-467a-42cc-bae0-e140f32073d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531484814 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.2531484814
Directory /workspace/31.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled_fixed.2942708724
Short name T626
Test name
Test status
Simulation time 486597355489 ps
CPU time 555.5 seconds
Started Mar 21 12:45:56 PM PDT 24
Finished Mar 21 12:55:11 PM PDT 24
Peak memory 201724 kb
Host smart-9951abab-6c4f-4def-b5ae-8313beb0e785
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942708724 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fix
ed.2942708724
Directory /workspace/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup.309963774
Short name T515
Test name
Test status
Simulation time 164298725101 ps
CPU time 101.51 seconds
Started Mar 21 12:45:57 PM PDT 24
Finished Mar 21 12:47:38 PM PDT 24
Peak memory 201796 kb
Host smart-6371be70-9000-4afc-84d1-58083edfe069
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309963774 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_
wakeup.309963774
Directory /workspace/31.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup_fixed.2939775132
Short name T241
Test name
Test status
Simulation time 600296479763 ps
CPU time 1506.18 seconds
Started Mar 21 12:47:23 PM PDT 24
Finished Mar 21 01:12:31 PM PDT 24
Peak memory 199572 kb
Host smart-39cc98af-f81d-4645-b734-0b56317e325b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939775132 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31
.adc_ctrl_filters_wakeup_fixed.2939775132
Directory /workspace/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_lowpower_counter.2199633669
Short name T772
Test name
Test status
Simulation time 24358737906 ps
CPU time 15.67 seconds
Started Mar 21 12:46:01 PM PDT 24
Finished Mar 21 12:46:17 PM PDT 24
Peak memory 201516 kb
Host smart-2ecba7a8-c953-4533-8f7f-f65373fcaab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199633669 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.2199633669
Directory /workspace/31.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_poweron_counter.279819260
Short name T603
Test name
Test status
Simulation time 4602720374 ps
CPU time 2.33 seconds
Started Mar 21 12:47:23 PM PDT 24
Finished Mar 21 12:47:27 PM PDT 24
Peak memory 199520 kb
Host smart-4b0c4ceb-5d86-4332-a211-c524ff530aca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279819260 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.279819260
Directory /workspace/31.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_smoke.2076673785
Short name T403
Test name
Test status
Simulation time 5956094536 ps
CPU time 15.12 seconds
Started Mar 21 12:47:37 PM PDT 24
Finished Mar 21 12:47:52 PM PDT 24
Peak memory 201472 kb
Host smart-0461dc9e-8269-49bd-a2d6-00bcf8d70665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076673785 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.2076673785
Directory /workspace/31.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all.3490386553
Short name T345
Test name
Test status
Simulation time 1064354488 ps
CPU time 1.31 seconds
Started Mar 21 12:45:57 PM PDT 24
Finished Mar 21 12:45:58 PM PDT 24
Peak memory 201520 kb
Host smart-864ed029-8ae2-43a1-94c8-39f240f947be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490386553 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all
.3490386553
Directory /workspace/31.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.2823287285
Short name T529
Test name
Test status
Simulation time 110565465280 ps
CPU time 105.91 seconds
Started Mar 21 12:46:00 PM PDT 24
Finished Mar 21 12:47:46 PM PDT 24
Peak memory 210128 kb
Host smart-1d6537b4-7745-4b95-a5f7-2e5cc80b8902
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823287285 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all_with_rand_reset.2823287285
Directory /workspace/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_alert_test.3094245285
Short name T449
Test name
Test status
Simulation time 425226792 ps
CPU time 1.58 seconds
Started Mar 21 12:46:11 PM PDT 24
Finished Mar 21 12:46:13 PM PDT 24
Peak memory 201408 kb
Host smart-ecc16a4e-b830-4d4f-9368-058ec028b715
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094245285 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.3094245285
Directory /workspace/32.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt.3088289549
Short name T152
Test name
Test status
Simulation time 494329663529 ps
CPU time 260.92 seconds
Started Mar 21 12:45:54 PM PDT 24
Finished Mar 21 12:50:16 PM PDT 24
Peak memory 201828 kb
Host smart-7e3766fe-bb41-4ddc-bedd-157022adc1a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088289549 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.3088289549
Directory /workspace/32.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt_fixed.2737933459
Short name T203
Test name
Test status
Simulation time 161863455647 ps
CPU time 357.38 seconds
Started Mar 21 12:45:58 PM PDT 24
Finished Mar 21 12:51:56 PM PDT 24
Peak memory 201708 kb
Host smart-3f82b31e-e810-44b1-b400-0982c3d3b319
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737933459 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interru
pt_fixed.2737933459
Directory /workspace/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled.2774502083
Short name T791
Test name
Test status
Simulation time 325365722253 ps
CPU time 793.26 seconds
Started Mar 21 12:45:56 PM PDT 24
Finished Mar 21 12:59:09 PM PDT 24
Peak memory 201736 kb
Host smart-58c225ed-1f1d-4a3f-b3f0-31de3d27a1ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774502083 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.2774502083
Directory /workspace/32.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled_fixed.4018505228
Short name T496
Test name
Test status
Simulation time 490869045005 ps
CPU time 492.16 seconds
Started Mar 21 12:46:03 PM PDT 24
Finished Mar 21 12:54:16 PM PDT 24
Peak memory 201712 kb
Host smart-07fcb90a-5bad-4d63-9ec1-48d24d4fbc09
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018505228 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fix
ed.4018505228
Directory /workspace/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup.3651615116
Short name T646
Test name
Test status
Simulation time 205373875912 ps
CPU time 127.08 seconds
Started Mar 21 12:45:58 PM PDT 24
Finished Mar 21 12:48:05 PM PDT 24
Peak memory 201776 kb
Host smart-0214aaec-3f94-4e5a-86bb-15ff3688ac13
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651615116 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters
_wakeup.3651615116
Directory /workspace/32.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup_fixed.2804391022
Short name T31
Test name
Test status
Simulation time 391902227003 ps
CPU time 706.57 seconds
Started Mar 21 12:46:01 PM PDT 24
Finished Mar 21 12:57:48 PM PDT 24
Peak memory 201804 kb
Host smart-33346ff8-6376-4312-b9c5-4bc9ba0d4b2d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804391022 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32
.adc_ctrl_filters_wakeup_fixed.2804391022
Directory /workspace/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_fsm_reset.2250988740
Short name T40
Test name
Test status
Simulation time 108143381896 ps
CPU time 351.92 seconds
Started Mar 21 12:47:36 PM PDT 24
Finished Mar 21 12:53:28 PM PDT 24
Peak memory 201944 kb
Host smart-5c002dd5-fcc4-4721-b431-0331268a8d48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250988740 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.2250988740
Directory /workspace/32.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_lowpower_counter.1031115678
Short name T352
Test name
Test status
Simulation time 42779918228 ps
CPU time 103.33 seconds
Started Mar 21 12:45:58 PM PDT 24
Finished Mar 21 12:47:42 PM PDT 24
Peak memory 201492 kb
Host smart-4c36dd5f-ffc0-4cc9-abaa-a929512250ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031115678 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.1031115678
Directory /workspace/32.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_poweron_counter.679147435
Short name T343
Test name
Test status
Simulation time 5339607374 ps
CPU time 12.11 seconds
Started Mar 21 12:45:56 PM PDT 24
Finished Mar 21 12:46:08 PM PDT 24
Peak memory 201496 kb
Host smart-11fed00a-6ae9-430e-b4a9-1cf578c15029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679147435 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.679147435
Directory /workspace/32.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_smoke.2894478025
Short name T478
Test name
Test status
Simulation time 5715349835 ps
CPU time 13.97 seconds
Started Mar 21 12:45:58 PM PDT 24
Finished Mar 21 12:46:12 PM PDT 24
Peak memory 201540 kb
Host smart-001f0872-a084-4cfa-a59c-67d0207cb73f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894478025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.2894478025
Directory /workspace/32.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all.2183092600
Short name T264
Test name
Test status
Simulation time 347154163429 ps
CPU time 146.49 seconds
Started Mar 21 12:46:11 PM PDT 24
Finished Mar 21 12:48:38 PM PDT 24
Peak memory 201792 kb
Host smart-e6d6d6a0-fdc3-426f-93e9-7bd126e7ac8c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183092600 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all
.2183092600
Directory /workspace/32.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.adc_ctrl_alert_test.2063571775
Short name T677
Test name
Test status
Simulation time 534699105 ps
CPU time 1.03 seconds
Started Mar 21 12:46:12 PM PDT 24
Finished Mar 21 12:46:14 PM PDT 24
Peak memory 201344 kb
Host smart-6dabfcac-9b1f-4b49-85a0-b5442ee48de0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063571775 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.2063571775
Directory /workspace/33.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_both.221170832
Short name T530
Test name
Test status
Simulation time 372127009985 ps
CPU time 244.62 seconds
Started Mar 21 12:46:06 PM PDT 24
Finished Mar 21 12:50:11 PM PDT 24
Peak memory 201784 kb
Host smart-6d3d8e58-1533-4e89-aabf-5b5c783d56bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221170832 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.221170832
Directory /workspace/33.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt.2017371053
Short name T407
Test name
Test status
Simulation time 484064932677 ps
CPU time 481.71 seconds
Started Mar 21 12:46:06 PM PDT 24
Finished Mar 21 12:54:08 PM PDT 24
Peak memory 201820 kb
Host smart-e0f005a0-7ab7-4be2-ba85-e08234cff051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017371053 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.2017371053
Directory /workspace/33.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt_fixed.1583290637
Short name T373
Test name
Test status
Simulation time 329971640244 ps
CPU time 211.31 seconds
Started Mar 21 12:46:06 PM PDT 24
Finished Mar 21 12:49:37 PM PDT 24
Peak memory 201676 kb
Host smart-293fe776-fea1-4b67-ba9e-d1f674272058
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583290637 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interru
pt_fixed.1583290637
Directory /workspace/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled.1110838264
Short name T766
Test name
Test status
Simulation time 331734351763 ps
CPU time 52.52 seconds
Started Mar 21 12:46:05 PM PDT 24
Finished Mar 21 12:46:58 PM PDT 24
Peak memory 201868 kb
Host smart-be71c413-4112-44f4-8d10-7cc075a89342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110838264 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.1110838264
Directory /workspace/33.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled_fixed.1984747031
Short name T350
Test name
Test status
Simulation time 332602720531 ps
CPU time 562.18 seconds
Started Mar 21 12:47:23 PM PDT 24
Finished Mar 21 12:56:47 PM PDT 24
Peak memory 199516 kb
Host smart-4e61338a-1654-4b1b-9919-1e5d21e0680d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984747031 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fix
ed.1984747031
Directory /workspace/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup.1128181245
Short name T281
Test name
Test status
Simulation time 537206088796 ps
CPU time 612.27 seconds
Started Mar 21 12:46:06 PM PDT 24
Finished Mar 21 12:56:19 PM PDT 24
Peak memory 201788 kb
Host smart-bbc29b6a-0e99-44ee-a508-58f9c8029c59
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128181245 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters
_wakeup.1128181245
Directory /workspace/33.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup_fixed.1902021177
Short name T792
Test name
Test status
Simulation time 404574347150 ps
CPU time 244.2 seconds
Started Mar 21 12:46:13 PM PDT 24
Finished Mar 21 12:50:18 PM PDT 24
Peak memory 201724 kb
Host smart-71c63de9-b84b-4fad-a344-36d4a45347f3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902021177 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33
.adc_ctrl_filters_wakeup_fixed.1902021177
Directory /workspace/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_fsm_reset.400662609
Short name T211
Test name
Test status
Simulation time 111657929573 ps
CPU time 544.09 seconds
Started Mar 21 12:46:07 PM PDT 24
Finished Mar 21 12:55:11 PM PDT 24
Peak memory 201968 kb
Host smart-43e4a505-cfa8-45be-b627-2d59a4dde4ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400662609 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.400662609
Directory /workspace/33.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_lowpower_counter.523018804
Short name T198
Test name
Test status
Simulation time 41415548544 ps
CPU time 95.92 seconds
Started Mar 21 12:46:07 PM PDT 24
Finished Mar 21 12:47:43 PM PDT 24
Peak memory 201616 kb
Host smart-6f7104ac-6301-4e5a-bac7-683e57af98db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523018804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.523018804
Directory /workspace/33.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_poweron_counter.3757101911
Short name T493
Test name
Test status
Simulation time 3800197160 ps
CPU time 10.63 seconds
Started Mar 21 12:46:12 PM PDT 24
Finished Mar 21 12:46:24 PM PDT 24
Peak memory 201468 kb
Host smart-66ae7366-72ef-4e90-a1df-14be43584625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757101911 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.3757101911
Directory /workspace/33.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_smoke.1841035798
Short name T486
Test name
Test status
Simulation time 5609464121 ps
CPU time 1.97 seconds
Started Mar 21 12:46:11 PM PDT 24
Finished Mar 21 12:46:15 PM PDT 24
Peak memory 201532 kb
Host smart-62780120-345c-4328-954b-1ef5dc088134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841035798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.1841035798
Directory /workspace/33.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all.4251912511
Short name T519
Test name
Test status
Simulation time 370906887042 ps
CPU time 228.85 seconds
Started Mar 21 12:46:07 PM PDT 24
Finished Mar 21 12:49:56 PM PDT 24
Peak memory 201792 kb
Host smart-88a54304-264f-4e81-975b-3b2398fe2121
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251912511 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all
.4251912511
Directory /workspace/33.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.4213204042
Short name T20
Test name
Test status
Simulation time 73030994058 ps
CPU time 122.09 seconds
Started Mar 21 12:46:05 PM PDT 24
Finished Mar 21 12:48:07 PM PDT 24
Peak memory 210344 kb
Host smart-79e26c3d-1adc-4004-be6a-d58e483f8698
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213204042 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all_with_rand_reset.4213204042
Directory /workspace/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_alert_test.2432821384
Short name T536
Test name
Test status
Simulation time 537804237 ps
CPU time 1.21 seconds
Started Mar 21 12:46:20 PM PDT 24
Finished Mar 21 12:46:21 PM PDT 24
Peak memory 201420 kb
Host smart-dc7453a8-58eb-4d32-a495-7cda472e7b90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432821384 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.2432821384
Directory /workspace/34.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_both.640321685
Short name T130
Test name
Test status
Simulation time 318720549309 ps
CPU time 401.94 seconds
Started Mar 21 12:46:06 PM PDT 24
Finished Mar 21 12:52:48 PM PDT 24
Peak memory 201796 kb
Host smart-35c5c394-00f4-46a3-9347-f95f5b82f9ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640321685 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.640321685
Directory /workspace/34.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt.3030499590
Short name T498
Test name
Test status
Simulation time 336405551479 ps
CPU time 789.22 seconds
Started Mar 21 12:46:11 PM PDT 24
Finished Mar 21 12:59:21 PM PDT 24
Peak memory 201784 kb
Host smart-b2fd33e8-8b5a-4c99-a990-abe3a5bc7111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030499590 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.3030499590
Directory /workspace/34.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt_fixed.2894900534
Short name T376
Test name
Test status
Simulation time 495652055891 ps
CPU time 316.21 seconds
Started Mar 21 12:47:23 PM PDT 24
Finished Mar 21 12:52:41 PM PDT 24
Peak memory 199604 kb
Host smart-ebf75812-f171-4f5e-ab1f-81fca0f7fb34
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894900534 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interru
pt_fixed.2894900534
Directory /workspace/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled.70626214
Short name T414
Test name
Test status
Simulation time 161297131213 ps
CPU time 81.28 seconds
Started Mar 21 12:46:06 PM PDT 24
Finished Mar 21 12:47:27 PM PDT 24
Peak memory 201788 kb
Host smart-71f579dc-98a4-4095-a588-bc74d64d97f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70626214 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.70626214
Directory /workspace/34.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled_fixed.1233016229
Short name T439
Test name
Test status
Simulation time 487283526608 ps
CPU time 1077.14 seconds
Started Mar 21 12:46:12 PM PDT 24
Finished Mar 21 01:04:10 PM PDT 24
Peak memory 201716 kb
Host smart-1ea038dd-86e0-4b97-9ec4-ca4126773420
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233016229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fix
ed.1233016229
Directory /workspace/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup.1409827846
Short name T631
Test name
Test status
Simulation time 366644439615 ps
CPU time 872.33 seconds
Started Mar 21 12:47:37 PM PDT 24
Finished Mar 21 01:02:09 PM PDT 24
Peak memory 201712 kb
Host smart-a5b17227-9fbd-4d3b-b727-bf2064102d0f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409827846 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters
_wakeup.1409827846
Directory /workspace/34.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.4146749048
Short name T531
Test name
Test status
Simulation time 602484242324 ps
CPU time 206.25 seconds
Started Mar 21 12:46:07 PM PDT 24
Finished Mar 21 12:49:33 PM PDT 24
Peak memory 201724 kb
Host smart-e1e813e5-39bf-42ec-86b9-49486e48aa5c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146749048 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34
.adc_ctrl_filters_wakeup_fixed.4146749048
Directory /workspace/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_lowpower_counter.278338311
Short name T610
Test name
Test status
Simulation time 24340128982 ps
CPU time 59.56 seconds
Started Mar 21 12:46:18 PM PDT 24
Finished Mar 21 12:47:18 PM PDT 24
Peak memory 201516 kb
Host smart-55729340-28d4-4393-bf7a-60708ea1cd0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278338311 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.278338311
Directory /workspace/34.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_poweron_counter.1626039246
Short name T787
Test name
Test status
Simulation time 5234427559 ps
CPU time 6.25 seconds
Started Mar 21 12:46:08 PM PDT 24
Finished Mar 21 12:46:14 PM PDT 24
Peak memory 201516 kb
Host smart-03942f82-a04a-46d7-970a-07228b3f6130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626039246 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.1626039246
Directory /workspace/34.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_smoke.1520248651
Short name T329
Test name
Test status
Simulation time 6217497117 ps
CPU time 1.79 seconds
Started Mar 21 12:46:10 PM PDT 24
Finished Mar 21 12:46:13 PM PDT 24
Peak memory 201528 kb
Host smart-128dd321-e712-49d8-bdc5-46312ba72d2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520248651 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.1520248651
Directory /workspace/34.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.adc_ctrl_alert_test.899837290
Short name T638
Test name
Test status
Simulation time 441190786 ps
CPU time 1.1 seconds
Started Mar 21 12:46:18 PM PDT 24
Finished Mar 21 12:46:19 PM PDT 24
Peak memory 201560 kb
Host smart-51b9cc39-2018-4227-979d-26710a4be8be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899837290 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.899837290
Directory /workspace/35.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.adc_ctrl_clock_gating.3365168930
Short name T711
Test name
Test status
Simulation time 186731968204 ps
CPU time 403.32 seconds
Started Mar 21 12:46:19 PM PDT 24
Finished Mar 21 12:53:02 PM PDT 24
Peak memory 201788 kb
Host smart-12bd7e2b-d69c-44b5-94b6-f2283fe4d00e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365168930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gat
ing.3365168930
Directory /workspace/35.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_both.3087051996
Short name T290
Test name
Test status
Simulation time 535493746582 ps
CPU time 1288.14 seconds
Started Mar 21 12:46:22 PM PDT 24
Finished Mar 21 01:07:50 PM PDT 24
Peak memory 201784 kb
Host smart-ec9305cd-92ca-4a69-97e4-349581f20df2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087051996 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.3087051996
Directory /workspace/35.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt_fixed.4176292087
Short name T401
Test name
Test status
Simulation time 324966799233 ps
CPU time 696.32 seconds
Started Mar 21 12:46:18 PM PDT 24
Finished Mar 21 12:57:55 PM PDT 24
Peak memory 201720 kb
Host smart-65258298-302f-4f37-9d67-57dd2241e364
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176292087 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interru
pt_fixed.4176292087
Directory /workspace/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled.597725171
Short name T98
Test name
Test status
Simulation time 338985417237 ps
CPU time 383.12 seconds
Started Mar 21 12:46:20 PM PDT 24
Finished Mar 21 12:52:43 PM PDT 24
Peak memory 201892 kb
Host smart-c90d6c26-c6d5-4821-bf90-70cad0f76726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597725171 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.597725171
Directory /workspace/35.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled_fixed.12749639
Short name T406
Test name
Test status
Simulation time 159658817197 ps
CPU time 101.62 seconds
Started Mar 21 12:46:19 PM PDT 24
Finished Mar 21 12:48:00 PM PDT 24
Peak memory 201796 kb
Host smart-a17a7274-47f0-404b-95b2-423a7183e22d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=12749639 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fixed
.12749639
Directory /workspace/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup.2536927492
Short name T741
Test name
Test status
Simulation time 357260678281 ps
CPU time 211.03 seconds
Started Mar 21 12:46:16 PM PDT 24
Finished Mar 21 12:49:47 PM PDT 24
Peak memory 201816 kb
Host smart-865e63fb-5638-44b5-a4dc-676884207e37
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536927492 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters
_wakeup.2536927492
Directory /workspace/35.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup_fixed.2907513608
Short name T391
Test name
Test status
Simulation time 588977092309 ps
CPU time 327.89 seconds
Started Mar 21 12:46:19 PM PDT 24
Finished Mar 21 12:51:48 PM PDT 24
Peak memory 201848 kb
Host smart-6be76802-8929-435b-8c22-4aa789271204
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907513608 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35
.adc_ctrl_filters_wakeup_fixed.2907513608
Directory /workspace/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_fsm_reset.1829231588
Short name T651
Test name
Test status
Simulation time 65330573063 ps
CPU time 392.41 seconds
Started Mar 21 12:46:17 PM PDT 24
Finished Mar 21 12:52:50 PM PDT 24
Peak memory 202080 kb
Host smart-09de1618-00d5-44b9-a1e8-765999155b6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829231588 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.1829231588
Directory /workspace/35.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_lowpower_counter.387258793
Short name T355
Test name
Test status
Simulation time 41564168933 ps
CPU time 23.28 seconds
Started Mar 21 12:46:16 PM PDT 24
Finished Mar 21 12:46:40 PM PDT 24
Peak memory 201500 kb
Host smart-ba69486e-98e9-4b08-bb0e-68e089cb1cfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387258793 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.387258793
Directory /workspace/35.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_poweron_counter.2952513514
Short name T410
Test name
Test status
Simulation time 3080392143 ps
CPU time 4.3 seconds
Started Mar 21 12:46:18 PM PDT 24
Finished Mar 21 12:46:23 PM PDT 24
Peak memory 201400 kb
Host smart-a3e1531c-76a7-4970-ae1d-dfded7a21e9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952513514 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.2952513514
Directory /workspace/35.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_smoke.2275433324
Short name T413
Test name
Test status
Simulation time 5780948254 ps
CPU time 1.69 seconds
Started Mar 21 12:46:19 PM PDT 24
Finished Mar 21 12:46:21 PM PDT 24
Peak memory 201532 kb
Host smart-e3b320f8-931f-4135-a712-d1112d4e8851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275433324 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.2275433324
Directory /workspace/35.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all.1503850995
Short name T687
Test name
Test status
Simulation time 501960283304 ps
CPU time 1662.39 seconds
Started Mar 21 12:46:18 PM PDT 24
Finished Mar 21 01:14:01 PM PDT 24
Peak memory 210212 kb
Host smart-2ac2288c-c78e-49d7-8bd3-6a3867dc4982
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503850995 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all
.1503850995
Directory /workspace/35.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.adc_ctrl_alert_test.1205205816
Short name T629
Test name
Test status
Simulation time 301926473 ps
CPU time 0.8 seconds
Started Mar 21 12:46:32 PM PDT 24
Finished Mar 21 12:46:33 PM PDT 24
Peak memory 201432 kb
Host smart-864d21b7-c309-4ec5-985d-5bcf522d8595
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205205816 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.1205205816
Directory /workspace/36.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_both.3351077748
Short name T266
Test name
Test status
Simulation time 498159247035 ps
CPU time 1112.58 seconds
Started Mar 21 12:46:30 PM PDT 24
Finished Mar 21 01:05:03 PM PDT 24
Peak memory 201712 kb
Host smart-e9b877aa-6b63-4346-8958-724cefe772a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351077748 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.3351077748
Directory /workspace/36.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt.2324047742
Short name T428
Test name
Test status
Simulation time 488055466966 ps
CPU time 1179 seconds
Started Mar 21 12:46:33 PM PDT 24
Finished Mar 21 01:06:12 PM PDT 24
Peak memory 201708 kb
Host smart-95805123-eb64-49f8-ba1f-14821a29fcd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324047742 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.2324047742
Directory /workspace/36.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.594610831
Short name T544
Test name
Test status
Simulation time 325568225223 ps
CPU time 768.89 seconds
Started Mar 21 12:46:31 PM PDT 24
Finished Mar 21 12:59:20 PM PDT 24
Peak memory 201640 kb
Host smart-d46a4efe-7d8d-48c1-853d-1343d8fe22a6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=594610831 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrup
t_fixed.594610831
Directory /workspace/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled.359397135
Short name T383
Test name
Test status
Simulation time 162764169324 ps
CPU time 204.58 seconds
Started Mar 21 12:46:31 PM PDT 24
Finished Mar 21 12:49:56 PM PDT 24
Peak memory 201808 kb
Host smart-304d91ac-a24e-4e55-a75f-c0eaafa24021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359397135 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.359397135
Directory /workspace/36.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled_fixed.1773999022
Short name T514
Test name
Test status
Simulation time 494761765779 ps
CPU time 332.24 seconds
Started Mar 21 12:46:32 PM PDT 24
Finished Mar 21 12:52:04 PM PDT 24
Peak memory 201716 kb
Host smart-7f9d6b17-baed-4073-b2ee-d7b4d33a6ec1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773999022 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fix
ed.1773999022
Directory /workspace/36.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup.1069032194
Short name T236
Test name
Test status
Simulation time 629401946248 ps
CPU time 714.16 seconds
Started Mar 21 12:46:33 PM PDT 24
Finished Mar 21 12:58:28 PM PDT 24
Peak memory 201704 kb
Host smart-84805264-d0ef-4656-87f8-769f615d77ff
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069032194 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters
_wakeup.1069032194
Directory /workspace/36.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup_fixed.1117772589
Short name T105
Test name
Test status
Simulation time 413364832121 ps
CPU time 234.24 seconds
Started Mar 21 12:46:31 PM PDT 24
Finished Mar 21 12:50:25 PM PDT 24
Peak memory 201716 kb
Host smart-16172341-8e2f-4b55-a949-e0a0ab8530b8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117772589 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36
.adc_ctrl_filters_wakeup_fixed.1117772589
Directory /workspace/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_fsm_reset.3025423475
Short name T688
Test name
Test status
Simulation time 79310658504 ps
CPU time 312.55 seconds
Started Mar 21 12:46:34 PM PDT 24
Finished Mar 21 12:51:46 PM PDT 24
Peak memory 202080 kb
Host smart-4dcf8cdb-9324-4211-961f-ab6f8b9dbaed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025423475 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.3025423475
Directory /workspace/36.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_lowpower_counter.1975729171
Short name T491
Test name
Test status
Simulation time 40469233427 ps
CPU time 24.78 seconds
Started Mar 21 12:46:35 PM PDT 24
Finished Mar 21 12:46:59 PM PDT 24
Peak memory 201512 kb
Host smart-8dc8cd4f-f0d9-4268-945b-5b84c084e401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975729171 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.1975729171
Directory /workspace/36.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_poweron_counter.571611206
Short name T505
Test name
Test status
Simulation time 4005526530 ps
CPU time 2.58 seconds
Started Mar 21 12:46:31 PM PDT 24
Finished Mar 21 12:46:33 PM PDT 24
Peak memory 201580 kb
Host smart-1fac3f21-de0e-42f0-bca2-8f3135fe051c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571611206 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.571611206
Directory /workspace/36.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_smoke.231141938
Short name T429
Test name
Test status
Simulation time 6178919536 ps
CPU time 4.54 seconds
Started Mar 21 12:46:36 PM PDT 24
Finished Mar 21 12:46:41 PM PDT 24
Peak memory 201540 kb
Host smart-9e5fd121-a596-437e-ba7d-be8d69dab986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231141938 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.231141938
Directory /workspace/36.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all.179545167
Short name T304
Test name
Test status
Simulation time 527462766484 ps
CPU time 793.78 seconds
Started Mar 21 12:46:35 PM PDT 24
Finished Mar 21 12:59:49 PM PDT 24
Peak memory 201844 kb
Host smart-819ee03e-2d56-472d-aa81-884f02c1cc6b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179545167 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all.
179545167
Directory /workspace/36.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.2383452158
Short name T550
Test name
Test status
Simulation time 68143118680 ps
CPU time 133.46 seconds
Started Mar 21 12:46:33 PM PDT 24
Finished Mar 21 12:48:46 PM PDT 24
Peak memory 210400 kb
Host smart-1a4a4c6e-f66a-4abf-a28e-3f00270600b4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383452158 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all_with_rand_reset.2383452158
Directory /workspace/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_alert_test.1969962426
Short name T497
Test name
Test status
Simulation time 486695725 ps
CPU time 0.9 seconds
Started Mar 21 12:46:44 PM PDT 24
Finished Mar 21 12:46:46 PM PDT 24
Peak memory 201396 kb
Host smart-a420fc3d-7009-4e7f-ac20-04d841589075
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969962426 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.1969962426
Directory /workspace/37.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.adc_ctrl_clock_gating.571338498
Short name T527
Test name
Test status
Simulation time 335013530148 ps
CPU time 222.94 seconds
Started Mar 21 12:46:44 PM PDT 24
Finished Mar 21 12:50:28 PM PDT 24
Peak memory 201880 kb
Host smart-0c68ffd7-9766-4705-9162-4146b4143ff7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571338498 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gati
ng.571338498
Directory /workspace/37.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt_fixed.1508294037
Short name T77
Test name
Test status
Simulation time 158897943578 ps
CPU time 177.4 seconds
Started Mar 21 12:46:32 PM PDT 24
Finished Mar 21 12:49:29 PM PDT 24
Peak memory 201712 kb
Host smart-27e36a73-896f-4a51-a947-4ba1ede6e211
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508294037 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interru
pt_fixed.1508294037
Directory /workspace/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled.2261349018
Short name T400
Test name
Test status
Simulation time 167125897948 ps
CPU time 376.58 seconds
Started Mar 21 12:46:31 PM PDT 24
Finished Mar 21 12:52:48 PM PDT 24
Peak memory 201864 kb
Host smart-24007d2a-217f-4a56-af66-e0fa51285bed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261349018 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.2261349018
Directory /workspace/37.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.3080545619
Short name T670
Test name
Test status
Simulation time 164926327303 ps
CPU time 68.51 seconds
Started Mar 21 12:46:33 PM PDT 24
Finished Mar 21 12:47:41 PM PDT 24
Peak memory 201864 kb
Host smart-cc1419f8-db02-4efc-aacb-120e8e55fe97
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080545619 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fix
ed.3080545619
Directory /workspace/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup.1870415922
Short name T2
Test name
Test status
Simulation time 360937834157 ps
CPU time 206.53 seconds
Started Mar 21 12:46:32 PM PDT 24
Finished Mar 21 12:49:59 PM PDT 24
Peak memory 201804 kb
Host smart-bdc5e8ea-7053-4238-a8fe-9deab1cf23c5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870415922 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters
_wakeup.1870415922
Directory /workspace/37.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup_fixed.739823111
Short name T503
Test name
Test status
Simulation time 412530228788 ps
CPU time 499.61 seconds
Started Mar 21 12:46:31 PM PDT 24
Finished Mar 21 12:54:51 PM PDT 24
Peak memory 201692 kb
Host smart-5931ca23-1d46-45b7-85bc-e16ec4035640
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739823111 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
adc_ctrl_filters_wakeup_fixed.739823111
Directory /workspace/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_fsm_reset.2254952319
Short name T445
Test name
Test status
Simulation time 61380177678 ps
CPU time 369.71 seconds
Started Mar 21 12:46:49 PM PDT 24
Finished Mar 21 12:52:59 PM PDT 24
Peak memory 202028 kb
Host smart-5608e0fe-afbd-4dec-8e3d-0441373a260b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254952319 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.2254952319
Directory /workspace/37.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_lowpower_counter.3590618357
Short name T171
Test name
Test status
Simulation time 47008054570 ps
CPU time 31.19 seconds
Started Mar 21 12:46:48 PM PDT 24
Finished Mar 21 12:47:20 PM PDT 24
Peak memory 201576 kb
Host smart-99bcc05c-ba36-454a-b935-61f531f65f70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590618357 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.3590618357
Directory /workspace/37.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_poweron_counter.2958827516
Short name T587
Test name
Test status
Simulation time 3954230318 ps
CPU time 3.29 seconds
Started Mar 21 12:46:50 PM PDT 24
Finished Mar 21 12:46:53 PM PDT 24
Peak memory 201500 kb
Host smart-bf32c527-afa3-4641-9b1b-6d2b77edca61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958827516 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.2958827516
Directory /workspace/37.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_smoke.3225044845
Short name T639
Test name
Test status
Simulation time 5758822487 ps
CPU time 2.17 seconds
Started Mar 21 12:46:32 PM PDT 24
Finished Mar 21 12:46:34 PM PDT 24
Peak memory 201532 kb
Host smart-95387a73-d7c5-483d-a18e-02f991fbba6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225044845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.3225044845
Directory /workspace/37.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all.2851681512
Short name T734
Test name
Test status
Simulation time 112655682722 ps
CPU time 353.88 seconds
Started Mar 21 12:46:44 PM PDT 24
Finished Mar 21 12:52:39 PM PDT 24
Peak memory 211060 kb
Host smart-9a2946f0-c1d6-4692-93e1-23ae88029724
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851681512 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all
.2851681512
Directory /workspace/37.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.2460693465
Short name T783
Test name
Test status
Simulation time 120402867753 ps
CPU time 191.21 seconds
Started Mar 21 12:46:45 PM PDT 24
Finished Mar 21 12:49:57 PM PDT 24
Peak memory 218232 kb
Host smart-56aa2701-0739-439e-924d-d86c7cbd1a6f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460693465 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.2460693465
Directory /workspace/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_alert_test.4012506959
Short name T595
Test name
Test status
Simulation time 347214410 ps
CPU time 1.05 seconds
Started Mar 21 12:46:46 PM PDT 24
Finished Mar 21 12:46:49 PM PDT 24
Peak memory 201408 kb
Host smart-d0ef9619-3eb7-4c2c-9668-5dadcf3a66c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012506959 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.4012506959
Directory /workspace/38.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_both.1864534982
Short name T720
Test name
Test status
Simulation time 501347673246 ps
CPU time 1193.72 seconds
Started Mar 21 12:46:43 PM PDT 24
Finished Mar 21 01:06:39 PM PDT 24
Peak memory 201704 kb
Host smart-81f7cac1-5598-4b5a-a15f-43564f7ec4e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864534982 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.1864534982
Directory /workspace/38.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt.2753198846
Short name T635
Test name
Test status
Simulation time 331975218505 ps
CPU time 778.94 seconds
Started Mar 21 12:46:43 PM PDT 24
Finished Mar 21 12:59:42 PM PDT 24
Peak memory 201872 kb
Host smart-7e6289a7-2dae-4400-9cea-bd767b0f0fc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753198846 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.2753198846
Directory /workspace/38.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt_fixed.2450297508
Short name T91
Test name
Test status
Simulation time 335887818345 ps
CPU time 744.79 seconds
Started Mar 21 12:46:46 PM PDT 24
Finished Mar 21 12:59:12 PM PDT 24
Peak memory 201684 kb
Host smart-30254a4b-f26c-46ab-bb23-fe7f58d545a3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450297508 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interru
pt_fixed.2450297508
Directory /workspace/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled.1694009566
Short name T141
Test name
Test status
Simulation time 322681463915 ps
CPU time 688.87 seconds
Started Mar 21 12:46:44 PM PDT 24
Finished Mar 21 12:58:15 PM PDT 24
Peak memory 201792 kb
Host smart-10a07056-1d97-4d10-8430-d5d33a9ffa80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694009566 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.1694009566
Directory /workspace/38.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled_fixed.1727654234
Short name T612
Test name
Test status
Simulation time 326181808758 ps
CPU time 84.17 seconds
Started Mar 21 12:46:46 PM PDT 24
Finished Mar 21 12:48:12 PM PDT 24
Peak memory 201776 kb
Host smart-0aa1faee-c38c-4fc5-abda-5cbb91e35169
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727654234 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fix
ed.1727654234
Directory /workspace/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup.4023335773
Short name T538
Test name
Test status
Simulation time 176526568843 ps
CPU time 57.37 seconds
Started Mar 21 12:46:43 PM PDT 24
Finished Mar 21 12:47:40 PM PDT 24
Peak memory 201708 kb
Host smart-0c701de5-b390-4111-9403-150046832f4d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023335773 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters
_wakeup.4023335773
Directory /workspace/38.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup_fixed.2995980003
Short name T702
Test name
Test status
Simulation time 404923232390 ps
CPU time 277.93 seconds
Started Mar 21 12:46:51 PM PDT 24
Finished Mar 21 12:51:29 PM PDT 24
Peak memory 201732 kb
Host smart-796b397e-deed-478d-a50f-42cabd932d35
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995980003 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38
.adc_ctrl_filters_wakeup_fixed.2995980003
Directory /workspace/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_fsm_reset.340661570
Short name T649
Test name
Test status
Simulation time 124491007387 ps
CPU time 484.68 seconds
Started Mar 21 12:46:46 PM PDT 24
Finished Mar 21 12:54:52 PM PDT 24
Peak memory 202068 kb
Host smart-2bc50e30-f61f-4691-a22f-32b76b6dfd1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340661570 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.340661570
Directory /workspace/38.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_lowpower_counter.2669404870
Short name T42
Test name
Test status
Simulation time 46802942226 ps
CPU time 58.26 seconds
Started Mar 21 12:46:45 PM PDT 24
Finished Mar 21 12:47:45 PM PDT 24
Peak memory 201580 kb
Host smart-9dc59651-94a7-4a6c-9d0d-0280d4c10311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669404870 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.2669404870
Directory /workspace/38.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_poweron_counter.3905281834
Short name T344
Test name
Test status
Simulation time 4234921028 ps
CPU time 3.2 seconds
Started Mar 21 12:46:50 PM PDT 24
Finished Mar 21 12:46:53 PM PDT 24
Peak memory 201460 kb
Host smart-e958a9a0-208b-4f9f-8183-7c380df6742e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905281834 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.3905281834
Directory /workspace/38.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_smoke.2892853406
Short name T101
Test name
Test status
Simulation time 6267916004 ps
CPU time 1.65 seconds
Started Mar 21 12:46:44 PM PDT 24
Finished Mar 21 12:46:47 PM PDT 24
Peak memory 201500 kb
Host smart-3a842203-20ab-4948-93c3-28e178094274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892853406 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.2892853406
Directory /workspace/38.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all.335249867
Short name T618
Test name
Test status
Simulation time 190424516509 ps
CPU time 463.42 seconds
Started Mar 21 12:46:49 PM PDT 24
Finished Mar 21 12:54:32 PM PDT 24
Peak memory 201800 kb
Host smart-009bb829-1381-4e15-a233-8394ebf27062
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335249867 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all.
335249867
Directory /workspace/38.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.889067341
Short name T49
Test name
Test status
Simulation time 48064017820 ps
CPU time 147.56 seconds
Started Mar 21 12:46:51 PM PDT 24
Finished Mar 21 12:49:19 PM PDT 24
Peak memory 210768 kb
Host smart-eea6940a-d228-4030-8abd-ef116c2f698d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889067341 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all_with_rand_reset.889067341
Directory /workspace/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_alert_test.2990860188
Short name T28
Test name
Test status
Simulation time 338880046 ps
CPU time 1.44 seconds
Started Mar 21 12:46:56 PM PDT 24
Finished Mar 21 12:46:58 PM PDT 24
Peak memory 201392 kb
Host smart-cc2d4180-e420-4cd7-9d82-4297d7563483
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990860188 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.2990860188
Directory /workspace/39.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.adc_ctrl_clock_gating.372548468
Short name T10
Test name
Test status
Simulation time 163839583234 ps
CPU time 89.8 seconds
Started Mar 21 12:46:51 PM PDT 24
Finished Mar 21 12:48:21 PM PDT 24
Peak memory 201780 kb
Host smart-a3359d21-0ed9-44c8-bb6c-f09e4e11f22c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372548468 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gati
ng.372548468
Directory /workspace/39.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_both.1524451121
Short name T689
Test name
Test status
Simulation time 366964941177 ps
CPU time 245.69 seconds
Started Mar 21 12:46:46 PM PDT 24
Finished Mar 21 12:50:53 PM PDT 24
Peak memory 201700 kb
Host smart-1e53c7c9-fa57-41f5-8679-d965e3f97fad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524451121 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.1524451121
Directory /workspace/39.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt.3096503981
Short name T287
Test name
Test status
Simulation time 157354618991 ps
CPU time 58.51 seconds
Started Mar 21 12:46:43 PM PDT 24
Finished Mar 21 12:47:43 PM PDT 24
Peak memory 201704 kb
Host smart-c296f53d-8125-4eab-8545-c7d13ee58449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096503981 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.3096503981
Directory /workspace/39.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt_fixed.2656597340
Short name T494
Test name
Test status
Simulation time 329841743160 ps
CPU time 189.06 seconds
Started Mar 21 12:46:50 PM PDT 24
Finished Mar 21 12:49:59 PM PDT 24
Peak memory 201712 kb
Host smart-66682ccf-4f33-4939-b6f7-267700a01764
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656597340 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interru
pt_fixed.2656597340
Directory /workspace/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled.3198933554
Short name T516
Test name
Test status
Simulation time 495510001955 ps
CPU time 575.67 seconds
Started Mar 21 12:46:50 PM PDT 24
Finished Mar 21 12:56:26 PM PDT 24
Peak memory 201808 kb
Host smart-9192dfea-f92a-4a31-a188-1bda388d5981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198933554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.3198933554
Directory /workspace/39.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled_fixed.3519696441
Short name T99
Test name
Test status
Simulation time 492542845896 ps
CPU time 567.86 seconds
Started Mar 21 12:46:44 PM PDT 24
Finished Mar 21 12:56:13 PM PDT 24
Peak memory 201788 kb
Host smart-d635fb94-4400-4f2f-9e25-eef55362c775
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519696441 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fix
ed.3519696441
Directory /workspace/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup.1183511592
Short name T621
Test name
Test status
Simulation time 530222092040 ps
CPU time 554.76 seconds
Started Mar 21 12:46:50 PM PDT 24
Finished Mar 21 12:56:04 PM PDT 24
Peak memory 201728 kb
Host smart-00f07450-1f96-4436-8bb5-8cdeb7cebdd8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183511592 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters
_wakeup.1183511592
Directory /workspace/39.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.2507871746
Short name T370
Test name
Test status
Simulation time 192717364673 ps
CPU time 406.99 seconds
Started Mar 21 12:46:50 PM PDT 24
Finished Mar 21 12:53:37 PM PDT 24
Peak memory 201728 kb
Host smart-fcab5d66-e533-46e3-92c9-2629a60d8937
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507871746 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39
.adc_ctrl_filters_wakeup_fixed.2507871746
Directory /workspace/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_fsm_reset.3164352149
Short name T452
Test name
Test status
Simulation time 128410641365 ps
CPU time 704.33 seconds
Started Mar 21 12:46:50 PM PDT 24
Finished Mar 21 12:58:35 PM PDT 24
Peak memory 202200 kb
Host smart-9c7c4023-a836-4b9c-989b-459d44fdb16a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164352149 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.3164352149
Directory /workspace/39.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_lowpower_counter.345911172
Short name T666
Test name
Test status
Simulation time 25360483042 ps
CPU time 58.84 seconds
Started Mar 21 12:46:43 PM PDT 24
Finished Mar 21 12:47:42 PM PDT 24
Peak memory 201624 kb
Host smart-678a68da-dd9d-4324-8d0d-40cda25ee13c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345911172 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.345911172
Directory /workspace/39.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_poweron_counter.2066965898
Short name T632
Test name
Test status
Simulation time 3039644374 ps
CPU time 4.19 seconds
Started Mar 21 12:46:52 PM PDT 24
Finished Mar 21 12:46:56 PM PDT 24
Peak memory 201440 kb
Host smart-3e89e4a4-0a92-4fb3-aeeb-980679a3bf19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066965898 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.2066965898
Directory /workspace/39.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_smoke.3140839733
Short name T184
Test name
Test status
Simulation time 5616855789 ps
CPU time 12.67 seconds
Started Mar 21 12:46:48 PM PDT 24
Finished Mar 21 12:47:01 PM PDT 24
Peak memory 201536 kb
Host smart-a42c3b12-d59a-4b78-b457-dab52dbcd5a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140839733 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.3140839733
Directory /workspace/39.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all.2232568429
Short name T581
Test name
Test status
Simulation time 488934080928 ps
CPU time 1189.83 seconds
Started Mar 21 12:46:54 PM PDT 24
Finished Mar 21 01:06:44 PM PDT 24
Peak memory 201716 kb
Host smart-85a37cf4-fde8-4463-8fdb-7637589034af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232568429 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all
.2232568429
Directory /workspace/39.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.2448780266
Short name T644
Test name
Test status
Simulation time 54134953082 ps
CPU time 119.31 seconds
Started Mar 21 12:46:44 PM PDT 24
Finished Mar 21 12:48:44 PM PDT 24
Peak memory 202008 kb
Host smart-afd5eb72-4ff6-4331-8a63-c4c5a35ba761
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448780266 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all_with_rand_reset.2448780266
Directory /workspace/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_alert_test.2222813042
Short name T613
Test name
Test status
Simulation time 525865605 ps
CPU time 1.73 seconds
Started Mar 21 12:44:20 PM PDT 24
Finished Mar 21 12:44:22 PM PDT 24
Peak memory 201412 kb
Host smart-0f602eaf-25e2-471d-a992-171992fcbee5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222813042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.2222813042
Directory /workspace/4.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.adc_ctrl_clock_gating.2727503283
Short name T86
Test name
Test status
Simulation time 531476240424 ps
CPU time 199.38 seconds
Started Mar 21 12:44:19 PM PDT 24
Finished Mar 21 12:47:39 PM PDT 24
Peak memory 201748 kb
Host smart-15999a35-767a-4b7c-824c-cb8b3717907e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727503283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gati
ng.2727503283
Directory /workspace/4.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_both.2562306855
Short name T242
Test name
Test status
Simulation time 491064255971 ps
CPU time 531.32 seconds
Started Mar 21 12:44:24 PM PDT 24
Finished Mar 21 12:53:16 PM PDT 24
Peak memory 201800 kb
Host smart-742b955e-1bef-4ab4-a3fa-66be3232f2ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562306855 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.2562306855
Directory /workspace/4.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt.1212312340
Short name T780
Test name
Test status
Simulation time 164572645688 ps
CPU time 129.9 seconds
Started Mar 21 12:44:25 PM PDT 24
Finished Mar 21 12:46:35 PM PDT 24
Peak memory 201692 kb
Host smart-f369a280-4298-4189-ba37-e5f094baee89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212312340 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.1212312340
Directory /workspace/4.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt_fixed.3871316223
Short name T611
Test name
Test status
Simulation time 328722660299 ps
CPU time 794.07 seconds
Started Mar 21 12:44:21 PM PDT 24
Finished Mar 21 12:57:36 PM PDT 24
Peak memory 201768 kb
Host smart-c22787ff-ce7c-4526-acdb-6477d360fd2e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871316223 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrup
t_fixed.3871316223
Directory /workspace/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled.4045989553
Short name T386
Test name
Test status
Simulation time 495356767250 ps
CPU time 462.95 seconds
Started Mar 21 12:44:22 PM PDT 24
Finished Mar 21 12:52:05 PM PDT 24
Peak memory 201808 kb
Host smart-2382c59d-bc07-4fd2-9d1a-e7fd39db4543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045989553 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.4045989553
Directory /workspace/4.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled_fixed.2179133458
Short name T578
Test name
Test status
Simulation time 326923527155 ps
CPU time 405.26 seconds
Started Mar 21 12:44:19 PM PDT 24
Finished Mar 21 12:51:05 PM PDT 24
Peak memory 201884 kb
Host smart-02fb3cb0-e00e-4b8c-83c2-486c98138f58
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179133458 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixe
d.2179133458
Directory /workspace/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup.1806386806
Short name T313
Test name
Test status
Simulation time 541729828815 ps
CPU time 1331.46 seconds
Started Mar 21 12:44:20 PM PDT 24
Finished Mar 21 01:06:32 PM PDT 24
Peak memory 201760 kb
Host smart-79675f1c-2d01-434c-8dd1-a5830a768cab
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806386806 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_
wakeup.1806386806
Directory /workspace/4.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup_fixed.2070678860
Short name T437
Test name
Test status
Simulation time 584823172538 ps
CPU time 1274.61 seconds
Started Mar 21 12:44:19 PM PDT 24
Finished Mar 21 01:05:34 PM PDT 24
Peak memory 201688 kb
Host smart-3f774761-e5c2-4db1-8bbd-6dc37696fb7b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070678860 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
adc_ctrl_filters_wakeup_fixed.2070678860
Directory /workspace/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_fsm_reset.2303386408
Short name T217
Test name
Test status
Simulation time 134587998047 ps
CPU time 551.2 seconds
Started Mar 21 12:44:18 PM PDT 24
Finished Mar 21 12:53:30 PM PDT 24
Peak memory 202016 kb
Host smart-a5f81284-3568-4c77-8312-e91542075972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303386408 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.2303386408
Directory /workspace/4.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_lowpower_counter.3449004346
Short name T390
Test name
Test status
Simulation time 42759742220 ps
CPU time 24.74 seconds
Started Mar 21 12:44:23 PM PDT 24
Finished Mar 21 12:44:48 PM PDT 24
Peak memory 201504 kb
Host smart-bcfe1b3b-d6a5-4c19-b323-90914d2fbea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449004346 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.3449004346
Directory /workspace/4.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_poweron_counter.3304289710
Short name T349
Test name
Test status
Simulation time 5155762373 ps
CPU time 13.71 seconds
Started Mar 21 12:44:22 PM PDT 24
Finished Mar 21 12:44:36 PM PDT 24
Peak memory 201600 kb
Host smart-c8c137f6-167d-4964-b81a-d4d231f947fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304289710 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.3304289710
Directory /workspace/4.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_sec_cm.2625517898
Short name T63
Test name
Test status
Simulation time 4522816415 ps
CPU time 1.4 seconds
Started Mar 21 12:44:23 PM PDT 24
Finished Mar 21 12:44:25 PM PDT 24
Peak memory 217240 kb
Host smart-a6b59ea5-e222-4ab7-ace6-f4502b166e39
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625517898 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.2625517898
Directory /workspace/4.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.adc_ctrl_smoke.4243067736
Short name T358
Test name
Test status
Simulation time 5705174123 ps
CPU time 14.75 seconds
Started Mar 21 12:44:21 PM PDT 24
Finished Mar 21 12:44:36 PM PDT 24
Peak memory 201552 kb
Host smart-170265cb-5e02-4414-9d09-f68817fedeb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243067736 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.4243067736
Directory /workspace/4.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all.1553940979
Short name T645
Test name
Test status
Simulation time 206366833235 ps
CPU time 125.49 seconds
Started Mar 21 12:44:22 PM PDT 24
Finished Mar 21 12:46:27 PM PDT 24
Peak memory 201788 kb
Host smart-5e5df194-47ac-4f2a-8937-d5f889202ad5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553940979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.
1553940979
Directory /workspace/4.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.3081545272
Short name T293
Test name
Test status
Simulation time 151274924486 ps
CPU time 363.29 seconds
Started Mar 21 12:44:20 PM PDT 24
Finished Mar 21 12:50:23 PM PDT 24
Peak memory 210392 kb
Host smart-bd69959b-4e06-4e5d-8488-77c590e91faa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081545272 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all_with_rand_reset.3081545272
Directory /workspace/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_alert_test.1478345222
Short name T499
Test name
Test status
Simulation time 283955570 ps
CPU time 1.2 seconds
Started Mar 21 12:47:04 PM PDT 24
Finished Mar 21 12:47:06 PM PDT 24
Peak memory 201428 kb
Host smart-7d361cda-aded-4451-bbd7-42c1d1d29ac8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478345222 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.1478345222
Directory /workspace/40.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_both.2248693501
Short name T312
Test name
Test status
Simulation time 328031452368 ps
CPU time 230.79 seconds
Started Mar 21 12:46:54 PM PDT 24
Finished Mar 21 12:50:45 PM PDT 24
Peak memory 201716 kb
Host smart-61dc5103-d65c-4a6f-beee-fb96e78cf24a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248693501 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.2248693501
Directory /workspace/40.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt.3050551962
Short name T237
Test name
Test status
Simulation time 166645107340 ps
CPU time 104.9 seconds
Started Mar 21 12:46:52 PM PDT 24
Finished Mar 21 12:48:37 PM PDT 24
Peak memory 201788 kb
Host smart-16681278-d187-4f72-ac7e-9a868f993333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050551962 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.3050551962
Directory /workspace/40.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt_fixed.3050750596
Short name T724
Test name
Test status
Simulation time 165587593336 ps
CPU time 95.23 seconds
Started Mar 21 12:46:56 PM PDT 24
Finished Mar 21 12:48:32 PM PDT 24
Peak memory 201688 kb
Host smart-45b333ae-c50a-495d-b94f-4bc2e6c0b80c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050750596 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interru
pt_fixed.3050750596
Directory /workspace/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled.401388662
Short name T226
Test name
Test status
Simulation time 493470525818 ps
CPU time 1210.81 seconds
Started Mar 21 12:46:54 PM PDT 24
Finished Mar 21 01:07:05 PM PDT 24
Peak memory 201724 kb
Host smart-a4048ae8-ee8e-4d7e-8169-1456cf4da87b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401388662 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.401388662
Directory /workspace/40.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled_fixed.2866231921
Short name T770
Test name
Test status
Simulation time 331203487628 ps
CPU time 721.14 seconds
Started Mar 21 12:46:51 PM PDT 24
Finished Mar 21 12:58:52 PM PDT 24
Peak memory 201796 kb
Host smart-19248db5-4cab-4229-b918-8a355c2fbcaf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866231921 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fix
ed.2866231921
Directory /workspace/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup.3491119270
Short name T246
Test name
Test status
Simulation time 358301966475 ps
CPU time 810.98 seconds
Started Mar 21 12:46:52 PM PDT 24
Finished Mar 21 01:00:24 PM PDT 24
Peak memory 201864 kb
Host smart-bd797f1c-1e91-4b88-89e8-723b34198e84
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491119270 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters
_wakeup.3491119270
Directory /workspace/40.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup_fixed.3246507319
Short name T482
Test name
Test status
Simulation time 399340014995 ps
CPU time 488.75 seconds
Started Mar 21 12:46:52 PM PDT 24
Finished Mar 21 12:55:01 PM PDT 24
Peak memory 201760 kb
Host smart-8a7ff279-b614-4ef2-ab3c-1fdaa2cbf89b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246507319 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40
.adc_ctrl_filters_wakeup_fixed.3246507319
Directory /workspace/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_fsm_reset.2977802424
Short name T173
Test name
Test status
Simulation time 108548467097 ps
CPU time 407.82 seconds
Started Mar 21 12:46:54 PM PDT 24
Finished Mar 21 12:53:42 PM PDT 24
Peak memory 202112 kb
Host smart-90c45126-166a-4a8a-89c2-f36020dbe0b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977802424 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.2977802424
Directory /workspace/40.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_lowpower_counter.3777544880
Short name T354
Test name
Test status
Simulation time 38250482922 ps
CPU time 42.72 seconds
Started Mar 21 12:46:55 PM PDT 24
Finished Mar 21 12:47:38 PM PDT 24
Peak memory 201504 kb
Host smart-2ef62743-33e9-4499-868c-ddd81eb2560e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777544880 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.3777544880
Directory /workspace/40.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_poweron_counter.3544524277
Short name T378
Test name
Test status
Simulation time 4408382865 ps
CPU time 10.87 seconds
Started Mar 21 12:46:52 PM PDT 24
Finished Mar 21 12:47:03 PM PDT 24
Peak memory 201504 kb
Host smart-744558dd-9b5d-4390-8017-3f0e14813b2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544524277 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.3544524277
Directory /workspace/40.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_smoke.1069181057
Short name T526
Test name
Test status
Simulation time 5776527746 ps
CPU time 7.76 seconds
Started Mar 21 12:46:53 PM PDT 24
Finished Mar 21 12:47:00 PM PDT 24
Peak memory 201536 kb
Host smart-54da6c2f-cf4d-4fce-b99f-67ff947c47bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069181057 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.1069181057
Directory /workspace/40.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all.3874860253
Short name T416
Test name
Test status
Simulation time 136314929132 ps
CPU time 669.96 seconds
Started Mar 21 12:46:55 PM PDT 24
Finished Mar 21 12:58:05 PM PDT 24
Peak memory 210324 kb
Host smart-b2a112bf-1575-4b4b-a918-bb698fbee1ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874860253 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all
.3874860253
Directory /workspace/40.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.2918526259
Short name T207
Test name
Test status
Simulation time 437985943183 ps
CPU time 103.71 seconds
Started Mar 21 12:46:51 PM PDT 24
Finished Mar 21 12:48:35 PM PDT 24
Peak memory 218044 kb
Host smart-d92d9d11-1bbe-4f09-8c82-9a67086289c6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918526259 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all_with_rand_reset.2918526259
Directory /workspace/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_alert_test.511906965
Short name T604
Test name
Test status
Simulation time 543372295 ps
CPU time 0.98 seconds
Started Mar 21 12:47:03 PM PDT 24
Finished Mar 21 12:47:05 PM PDT 24
Peak memory 201420 kb
Host smart-09cf21a8-7ccc-4ecb-a795-5fe05599430b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511906965 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.511906965
Directory /workspace/41.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_both.4270807280
Short name T78
Test name
Test status
Simulation time 170052614980 ps
CPU time 376.64 seconds
Started Mar 21 12:47:02 PM PDT 24
Finished Mar 21 12:53:21 PM PDT 24
Peak memory 201860 kb
Host smart-919136c2-f5f9-4a14-9e9a-4f8f572c8dc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270807280 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.4270807280
Directory /workspace/41.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt.3696691913
Short name T506
Test name
Test status
Simulation time 486864704727 ps
CPU time 1173.61 seconds
Started Mar 21 12:47:07 PM PDT 24
Finished Mar 21 01:06:41 PM PDT 24
Peak memory 201772 kb
Host smart-9014028f-5b0a-4c91-883d-75e20f675b2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696691913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.3696691913
Directory /workspace/41.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt_fixed.3905607927
Short name T521
Test name
Test status
Simulation time 321151526726 ps
CPU time 686.68 seconds
Started Mar 21 12:47:07 PM PDT 24
Finished Mar 21 12:58:34 PM PDT 24
Peak memory 201684 kb
Host smart-a79a461e-2697-4677-accc-31598407ff34
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905607927 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interru
pt_fixed.3905607927
Directory /workspace/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled.10627185
Short name T142
Test name
Test status
Simulation time 165286678685 ps
CPU time 100.77 seconds
Started Mar 21 12:47:02 PM PDT 24
Finished Mar 21 12:48:45 PM PDT 24
Peak memory 201704 kb
Host smart-36988ce8-bb39-4e33-9421-97ac81fa4d2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10627185 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.10627185
Directory /workspace/41.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled_fixed.3541131936
Short name T558
Test name
Test status
Simulation time 165530352115 ps
CPU time 203.51 seconds
Started Mar 21 12:47:01 PM PDT 24
Finished Mar 21 12:50:25 PM PDT 24
Peak memory 201632 kb
Host smart-b8517d5d-7c4b-49f2-90cd-fd31fb8487f1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541131936 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fix
ed.3541131936
Directory /workspace/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup.835800405
Short name T12
Test name
Test status
Simulation time 173010692965 ps
CPU time 387.92 seconds
Started Mar 21 12:47:01 PM PDT 24
Finished Mar 21 12:53:30 PM PDT 24
Peak memory 201868 kb
Host smart-26248e89-2542-4eb1-8efd-fecb21b43862
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835800405 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_
wakeup.835800405
Directory /workspace/41.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.144685240
Short name T744
Test name
Test status
Simulation time 604259050127 ps
CPU time 132.04 seconds
Started Mar 21 12:47:03 PM PDT 24
Finished Mar 21 12:49:16 PM PDT 24
Peak memory 201816 kb
Host smart-a309a4ae-0408-4967-85f3-78d04a2b98eb
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144685240 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
adc_ctrl_filters_wakeup_fixed.144685240
Directory /workspace/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_fsm_reset.26964633
Short name T325
Test name
Test status
Simulation time 81359682009 ps
CPU time 414.73 seconds
Started Mar 21 12:47:02 PM PDT 24
Finished Mar 21 12:53:57 PM PDT 24
Peak memory 202092 kb
Host smart-ecd2619c-31c4-4243-91e6-2fb8b4883f07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26964633 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.26964633
Directory /workspace/41.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_lowpower_counter.3302088391
Short name T346
Test name
Test status
Simulation time 21415595809 ps
CPU time 14.08 seconds
Started Mar 21 12:47:02 PM PDT 24
Finished Mar 21 12:47:18 PM PDT 24
Peak memory 201500 kb
Host smart-e239dc0f-0e06-4921-912f-838bc9529958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302088391 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.3302088391
Directory /workspace/41.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_poweron_counter.1523690532
Short name T532
Test name
Test status
Simulation time 4639828792 ps
CPU time 3.44 seconds
Started Mar 21 12:47:02 PM PDT 24
Finished Mar 21 12:47:07 PM PDT 24
Peak memory 201464 kb
Host smart-810fd0f7-e6f4-48e7-b4c6-413ffcbeaf8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523690532 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.1523690532
Directory /workspace/41.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_smoke.18410747
Short name T715
Test name
Test status
Simulation time 5863447317 ps
CPU time 14.8 seconds
Started Mar 21 12:47:05 PM PDT 24
Finished Mar 21 12:47:20 PM PDT 24
Peak memory 201532 kb
Host smart-0a31828e-328e-416b-a7fa-c89c34cd436e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18410747 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.18410747
Directory /workspace/41.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all.1507640718
Short name T220
Test name
Test status
Simulation time 93360448280 ps
CPU time 363.78 seconds
Started Mar 21 12:47:06 PM PDT 24
Finished Mar 21 12:53:11 PM PDT 24
Peak memory 202092 kb
Host smart-edb868ee-fba8-491d-bf3d-72c0e5319602
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507640718 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all
.1507640718
Directory /workspace/41.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.1046132559
Short name T464
Test name
Test status
Simulation time 20038619423 ps
CPU time 48 seconds
Started Mar 21 12:47:03 PM PDT 24
Finished Mar 21 12:47:52 PM PDT 24
Peak memory 210064 kb
Host smart-07b717bd-1faf-4f69-b76b-80c069187094
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046132559 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all_with_rand_reset.1046132559
Directory /workspace/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_alert_test.1051962964
Short name T389
Test name
Test status
Simulation time 370319722 ps
CPU time 1.56 seconds
Started Mar 21 12:47:15 PM PDT 24
Finished Mar 21 12:47:17 PM PDT 24
Peak memory 201432 kb
Host smart-23f4bf30-3797-4cdd-ab7c-7e74a334fda2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051962964 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.1051962964
Directory /workspace/42.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.adc_ctrl_clock_gating.3922153293
Short name T436
Test name
Test status
Simulation time 181810968204 ps
CPU time 446.19 seconds
Started Mar 21 12:47:04 PM PDT 24
Finished Mar 21 12:54:32 PM PDT 24
Peak memory 201780 kb
Host smart-c585e401-8876-4b23-989b-c6607ef67ea4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922153293 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gat
ing.3922153293
Directory /workspace/42.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt.179400829
Short name T164
Test name
Test status
Simulation time 495887570950 ps
CPU time 326.04 seconds
Started Mar 21 12:47:07 PM PDT 24
Finished Mar 21 12:52:33 PM PDT 24
Peak memory 201712 kb
Host smart-2560f822-2214-4cc3-bbc9-0a73440722bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179400829 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.179400829
Directory /workspace/42.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt_fixed.3902201316
Short name T183
Test name
Test status
Simulation time 336850650129 ps
CPU time 201.5 seconds
Started Mar 21 12:47:05 PM PDT 24
Finished Mar 21 12:50:27 PM PDT 24
Peak memory 201708 kb
Host smart-8f1d28ff-3275-47ec-81b6-3ac0f7c45e6d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902201316 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interru
pt_fixed.3902201316
Directory /workspace/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled.3719584765
Short name T739
Test name
Test status
Simulation time 166886118507 ps
CPU time 389.88 seconds
Started Mar 21 12:47:02 PM PDT 24
Finished Mar 21 12:53:34 PM PDT 24
Peak memory 201724 kb
Host smart-dcfd6c13-494c-4c36-bb87-6342495e9dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719584765 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.3719584765
Directory /workspace/42.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.464177923
Short name T500
Test name
Test status
Simulation time 482447641347 ps
CPU time 617.3 seconds
Started Mar 21 12:47:03 PM PDT 24
Finished Mar 21 12:57:21 PM PDT 24
Peak memory 201708 kb
Host smart-6ecbf67f-514d-4714-80d8-4a33670882f8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=464177923 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fixe
d.464177923
Directory /workspace/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup.2558165549
Short name T393
Test name
Test status
Simulation time 169522777071 ps
CPU time 53.1 seconds
Started Mar 21 12:47:04 PM PDT 24
Finished Mar 21 12:47:57 PM PDT 24
Peak memory 201816 kb
Host smart-5d336869-0380-4cc8-9bf4-51815c5e15fc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558165549 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters
_wakeup.2558165549
Directory /workspace/42.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup_fixed.3467464642
Short name T680
Test name
Test status
Simulation time 572236445561 ps
CPU time 1246.44 seconds
Started Mar 21 12:47:02 PM PDT 24
Finished Mar 21 01:07:50 PM PDT 24
Peak memory 201772 kb
Host smart-904abd99-b2f6-4a02-ac41-0c999dc817d1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467464642 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42
.adc_ctrl_filters_wakeup_fixed.3467464642
Directory /workspace/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_lowpower_counter.2387516861
Short name T580
Test name
Test status
Simulation time 35572716974 ps
CPU time 84.16 seconds
Started Mar 21 12:47:13 PM PDT 24
Finished Mar 21 12:48:37 PM PDT 24
Peak memory 201612 kb
Host smart-375edc52-8939-41be-bc3f-6b8882d50f6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387516861 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.2387516861
Directory /workspace/42.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_poweron_counter.2408000532
Short name T583
Test name
Test status
Simulation time 3632103516 ps
CPU time 5.25 seconds
Started Mar 21 12:47:10 PM PDT 24
Finished Mar 21 12:47:16 PM PDT 24
Peak memory 201536 kb
Host smart-299124ec-1068-4d4a-94da-f9077275e3c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408000532 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.2408000532
Directory /workspace/42.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_smoke.318262225
Short name T453
Test name
Test status
Simulation time 5971162446 ps
CPU time 2.67 seconds
Started Mar 21 12:47:02 PM PDT 24
Finished Mar 21 12:47:07 PM PDT 24
Peak memory 201540 kb
Host smart-09e314ab-2567-4d9b-a2f7-a2981a0aa2c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318262225 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.318262225
Directory /workspace/42.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all.3653156194
Short name T137
Test name
Test status
Simulation time 518481510311 ps
CPU time 298.45 seconds
Started Mar 21 12:47:10 PM PDT 24
Finished Mar 21 12:52:08 PM PDT 24
Peak memory 201700 kb
Host smart-252ca315-1639-4669-8b89-127ad0c33877
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653156194 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all
.3653156194
Directory /workspace/42.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.353668779
Short name T302
Test name
Test status
Simulation time 124996218799 ps
CPU time 156.86 seconds
Started Mar 21 12:47:14 PM PDT 24
Finished Mar 21 12:49:51 PM PDT 24
Peak memory 210376 kb
Host smart-0b3f7a94-0ba2-43c2-997a-21706e5dd9d6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353668779 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all_with_rand_reset.353668779
Directory /workspace/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_alert_test.409976065
Short name T454
Test name
Test status
Simulation time 371271373 ps
CPU time 0.76 seconds
Started Mar 21 12:47:12 PM PDT 24
Finished Mar 21 12:47:13 PM PDT 24
Peak memory 201484 kb
Host smart-747bddf7-82b1-4750-8c49-0bf6fba95b85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409976065 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.409976065
Directory /workspace/43.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_both.1287332658
Short name T82
Test name
Test status
Simulation time 414941159186 ps
CPU time 259.01 seconds
Started Mar 21 12:47:11 PM PDT 24
Finished Mar 21 12:51:30 PM PDT 24
Peak memory 201688 kb
Host smart-7d74f206-31be-4a92-b91a-5706759f3d97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287332658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.1287332658
Directory /workspace/43.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt.3125932301
Short name T643
Test name
Test status
Simulation time 492982551866 ps
CPU time 1194.5 seconds
Started Mar 21 12:47:12 PM PDT 24
Finished Mar 21 01:07:06 PM PDT 24
Peak memory 201704 kb
Host smart-e0699da4-9832-4ad7-b216-d77595b8efe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125932301 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.3125932301
Directory /workspace/43.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.271119780
Short name T362
Test name
Test status
Simulation time 491334370160 ps
CPU time 1125.29 seconds
Started Mar 21 12:47:11 PM PDT 24
Finished Mar 21 01:05:57 PM PDT 24
Peak memory 201844 kb
Host smart-565cf087-4471-46e2-91b4-8bb5041c1cda
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=271119780 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrup
t_fixed.271119780
Directory /workspace/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled.4121457504
Short name T554
Test name
Test status
Simulation time 161216184092 ps
CPU time 185.21 seconds
Started Mar 21 12:47:12 PM PDT 24
Finished Mar 21 12:50:17 PM PDT 24
Peak memory 201808 kb
Host smart-b49607a6-d519-4280-b471-73d7816afa37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121457504 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.4121457504
Directory /workspace/43.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled_fixed.4095623949
Short name T667
Test name
Test status
Simulation time 496474156700 ps
CPU time 278.26 seconds
Started Mar 21 12:47:11 PM PDT 24
Finished Mar 21 12:51:49 PM PDT 24
Peak memory 201716 kb
Host smart-81e88a34-2368-40ab-b685-0cb1fcdbee3c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095623949 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fix
ed.4095623949
Directory /workspace/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup.1920324835
Short name T784
Test name
Test status
Simulation time 187656957457 ps
CPU time 115.19 seconds
Started Mar 21 12:47:10 PM PDT 24
Finished Mar 21 12:49:06 PM PDT 24
Peak memory 201848 kb
Host smart-5fa0c68a-ddf5-4044-ad70-ca756c9d3a68
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920324835 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters
_wakeup.1920324835
Directory /workspace/43.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.2724149085
Short name T534
Test name
Test status
Simulation time 197635199422 ps
CPU time 56.51 seconds
Started Mar 21 12:47:16 PM PDT 24
Finished Mar 21 12:48:13 PM PDT 24
Peak memory 201812 kb
Host smart-c5c7b8d2-096c-462a-8197-f1b6cf72c271
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724149085 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43
.adc_ctrl_filters_wakeup_fixed.2724149085
Directory /workspace/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_fsm_reset.96171445
Short name T765
Test name
Test status
Simulation time 108755244778 ps
CPU time 421.1 seconds
Started Mar 21 12:47:11 PM PDT 24
Finished Mar 21 12:54:12 PM PDT 24
Peak memory 202108 kb
Host smart-1c3c2a47-c7a7-49e9-96df-605e4ded3022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96171445 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.96171445
Directory /workspace/43.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_lowpower_counter.772721537
Short name T456
Test name
Test status
Simulation time 34340345825 ps
CPU time 79.62 seconds
Started Mar 21 12:47:12 PM PDT 24
Finished Mar 21 12:48:32 PM PDT 24
Peak memory 201580 kb
Host smart-dc528c4e-7258-49fd-8a03-2e8e123eda01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772721537 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.772721537
Directory /workspace/43.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_poweron_counter.3481338927
Short name T80
Test name
Test status
Simulation time 4668934662 ps
CPU time 6.35 seconds
Started Mar 21 12:47:13 PM PDT 24
Finished Mar 21 12:47:20 PM PDT 24
Peak memory 201644 kb
Host smart-362335e9-2428-406d-873a-c64b2f5beeff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481338927 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.3481338927
Directory /workspace/43.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_smoke.2577856775
Short name T419
Test name
Test status
Simulation time 5771073738 ps
CPU time 14.55 seconds
Started Mar 21 12:47:20 PM PDT 24
Finished Mar 21 12:47:35 PM PDT 24
Peak memory 201536 kb
Host smart-90d34f74-4175-405c-a428-195e0570bc40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577856775 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.2577856775
Directory /workspace/43.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all.3219283533
Short name T165
Test name
Test status
Simulation time 429592952425 ps
CPU time 486.64 seconds
Started Mar 21 12:47:11 PM PDT 24
Finished Mar 21 12:55:18 PM PDT 24
Peak memory 210368 kb
Host smart-d38fcba9-8ce9-4f19-be9e-60feeec1fd95
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219283533 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all
.3219283533
Directory /workspace/43.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.3336116455
Short name T750
Test name
Test status
Simulation time 146667657295 ps
CPU time 406.94 seconds
Started Mar 21 12:47:15 PM PDT 24
Finished Mar 21 12:54:02 PM PDT 24
Peak memory 218308 kb
Host smart-aed06726-385e-4ead-b51d-b89e14f26b85
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336116455 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.3336116455
Directory /workspace/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_alert_test.2530374009
Short name T774
Test name
Test status
Simulation time 496214512 ps
CPU time 0.9 seconds
Started Mar 21 12:47:23 PM PDT 24
Finished Mar 21 12:47:24 PM PDT 24
Peak memory 201360 kb
Host smart-f6519d22-4755-4975-a457-bc78bbcd7853
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530374009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.2530374009
Directory /workspace/44.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.adc_ctrl_clock_gating.2349631714
Short name T280
Test name
Test status
Simulation time 330578190850 ps
CPU time 213.66 seconds
Started Mar 21 12:47:23 PM PDT 24
Finished Mar 21 12:50:56 PM PDT 24
Peak memory 201720 kb
Host smart-505acff5-73c7-415d-9a27-845499be668c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349631714 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gat
ing.2349631714
Directory /workspace/44.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_both.47489078
Short name T597
Test name
Test status
Simulation time 520753952036 ps
CPU time 351.76 seconds
Started Mar 21 12:47:22 PM PDT 24
Finished Mar 21 12:53:13 PM PDT 24
Peak memory 201800 kb
Host smart-45d0a62d-e238-49df-ad3f-351773fbfb80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47489078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.47489078
Directory /workspace/44.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt.1012847223
Short name T131
Test name
Test status
Simulation time 489619132976 ps
CPU time 559.62 seconds
Started Mar 21 12:47:23 PM PDT 24
Finished Mar 21 12:56:42 PM PDT 24
Peak memory 201772 kb
Host smart-ccca630b-b008-439e-8bb1-98abddf93ba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012847223 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.1012847223
Directory /workspace/44.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt_fixed.2340101408
Short name T579
Test name
Test status
Simulation time 485091122572 ps
CPU time 306.12 seconds
Started Mar 21 12:47:21 PM PDT 24
Finished Mar 21 12:52:27 PM PDT 24
Peak memory 201712 kb
Host smart-0e2ef7bd-8cf9-4f9d-ad15-9fa0238f4364
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340101408 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interru
pt_fixed.2340101408
Directory /workspace/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled.2782398871
Short name T517
Test name
Test status
Simulation time 162652502204 ps
CPU time 388.3 seconds
Started Mar 21 12:47:22 PM PDT 24
Finished Mar 21 12:53:50 PM PDT 24
Peak memory 201820 kb
Host smart-39e4ba58-4138-4547-9a6e-57f55251fb20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782398871 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.2782398871
Directory /workspace/44.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled_fixed.3757519845
Short name T387
Test name
Test status
Simulation time 165018794805 ps
CPU time 376.25 seconds
Started Mar 21 12:47:21 PM PDT 24
Finished Mar 21 12:53:37 PM PDT 24
Peak memory 201716 kb
Host smart-ba732329-e232-42ae-9078-b8920f501178
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757519845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fix
ed.3757519845
Directory /workspace/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup.540645228
Short name T245
Test name
Test status
Simulation time 583193898076 ps
CPU time 1315.43 seconds
Started Mar 21 12:47:23 PM PDT 24
Finished Mar 21 01:09:19 PM PDT 24
Peak memory 201740 kb
Host smart-45dc1165-67a0-4dfd-b328-057dde8902bc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540645228 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_
wakeup.540645228
Directory /workspace/44.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup_fixed.198860525
Short name T590
Test name
Test status
Simulation time 616063959702 ps
CPU time 190.86 seconds
Started Mar 21 12:47:21 PM PDT 24
Finished Mar 21 12:50:32 PM PDT 24
Peak memory 201672 kb
Host smart-258891f5-39c5-4467-8cce-3f401c9f5efc
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198860525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
adc_ctrl_filters_wakeup_fixed.198860525
Directory /workspace/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_fsm_reset.814707309
Short name T725
Test name
Test status
Simulation time 112963897270 ps
CPU time 481.07 seconds
Started Mar 21 12:47:58 PM PDT 24
Finished Mar 21 12:55:59 PM PDT 24
Peak memory 202048 kb
Host smart-7e6009dd-ada7-44d2-81b4-b98581a7f986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814707309 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.814707309
Directory /workspace/44.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_lowpower_counter.92116191
Short name T624
Test name
Test status
Simulation time 25219809653 ps
CPU time 54.38 seconds
Started Mar 21 12:47:22 PM PDT 24
Finished Mar 21 12:48:16 PM PDT 24
Peak memory 201512 kb
Host smart-56cf5d14-c3d8-4d3c-b0bc-0583ca147617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92116191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.92116191
Directory /workspace/44.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_poweron_counter.419692499
Short name T708
Test name
Test status
Simulation time 3017693433 ps
CPU time 7.73 seconds
Started Mar 21 12:47:22 PM PDT 24
Finished Mar 21 12:47:30 PM PDT 24
Peak memory 201392 kb
Host smart-67060307-746d-4b2d-88de-c2fae04156c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419692499 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.419692499
Directory /workspace/44.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_smoke.1820760224
Short name T746
Test name
Test status
Simulation time 5971323597 ps
CPU time 12.88 seconds
Started Mar 21 12:47:21 PM PDT 24
Finished Mar 21 12:47:34 PM PDT 24
Peak memory 201516 kb
Host smart-a80b16e5-cd05-4612-ac79-cca927b1c97f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820760224 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.1820760224
Directory /workspace/44.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all.997938226
Short name T75
Test name
Test status
Simulation time 364545236981 ps
CPU time 160.94 seconds
Started Mar 21 12:47:21 PM PDT 24
Finished Mar 21 12:50:02 PM PDT 24
Peak memory 201704 kb
Host smart-9702d081-0a43-450e-9b97-b24dab59ec40
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997938226 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all.
997938226
Directory /workspace/44.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.1368970482
Short name T699
Test name
Test status
Simulation time 35998192259 ps
CPU time 85.73 seconds
Started Mar 21 12:47:21 PM PDT 24
Finished Mar 21 12:48:47 PM PDT 24
Peak memory 210072 kb
Host smart-2091e60f-c2e0-4b8f-bdeb-f3625e0f4309
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368970482 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all_with_rand_reset.1368970482
Directory /workspace/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_alert_test.1183689213
Short name T512
Test name
Test status
Simulation time 291824243 ps
CPU time 1.35 seconds
Started Mar 21 12:47:31 PM PDT 24
Finished Mar 21 12:47:33 PM PDT 24
Peak memory 201380 kb
Host smart-436b7f4d-f7fc-4b91-8ff4-751009b330d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183689213 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.1183689213
Directory /workspace/45.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_both.92189314
Short name T192
Test name
Test status
Simulation time 178690341089 ps
CPU time 420.97 seconds
Started Mar 21 12:47:33 PM PDT 24
Finished Mar 21 12:54:35 PM PDT 24
Peak memory 201716 kb
Host smart-df48bab2-7f74-4665-9210-7f4d58ffedd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92189314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.92189314
Directory /workspace/45.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt.3488489661
Short name T762
Test name
Test status
Simulation time 337308321695 ps
CPU time 154.67 seconds
Started Mar 21 12:47:32 PM PDT 24
Finished Mar 21 12:50:07 PM PDT 24
Peak memory 201708 kb
Host smart-4f68d65f-71cb-4cdc-b64a-1114859a3a82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488489661 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.3488489661
Directory /workspace/45.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt_fixed.2265340402
Short name T396
Test name
Test status
Simulation time 161230759570 ps
CPU time 26.09 seconds
Started Mar 21 12:47:30 PM PDT 24
Finished Mar 21 12:47:56 PM PDT 24
Peak memory 201692 kb
Host smart-775d9d60-1b6c-4dd0-b6b3-45b904489c02
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265340402 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interru
pt_fixed.2265340402
Directory /workspace/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled.1905934428
Short name T148
Test name
Test status
Simulation time 491409799163 ps
CPU time 1131.86 seconds
Started Mar 21 12:47:22 PM PDT 24
Finished Mar 21 01:06:14 PM PDT 24
Peak memory 201804 kb
Host smart-56b51058-27e2-4283-a009-be2e91f9351c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905934428 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.1905934428
Directory /workspace/45.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled_fixed.974013297
Short name T573
Test name
Test status
Simulation time 163716839215 ps
CPU time 100.27 seconds
Started Mar 21 12:47:32 PM PDT 24
Finished Mar 21 12:49:12 PM PDT 24
Peak memory 201708 kb
Host smart-e2151b46-1292-4e14-b308-99e5cc0eb17c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=974013297 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fixe
d.974013297
Directory /workspace/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup.3995688963
Short name T546
Test name
Test status
Simulation time 190388283283 ps
CPU time 398.2 seconds
Started Mar 21 12:47:33 PM PDT 24
Finished Mar 21 12:54:11 PM PDT 24
Peak memory 201736 kb
Host smart-c6aea045-37ee-47ad-ae38-77215b4ad225
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995688963 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters
_wakeup.3995688963
Directory /workspace/45.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup_fixed.3121496285
Short name T703
Test name
Test status
Simulation time 192498213126 ps
CPU time 138.69 seconds
Started Mar 21 12:47:30 PM PDT 24
Finished Mar 21 12:49:48 PM PDT 24
Peak memory 201872 kb
Host smart-6d0d8ee7-e439-46ef-8f2d-49b3fcf5b88f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121496285 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45
.adc_ctrl_filters_wakeup_fixed.3121496285
Directory /workspace/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_fsm_reset.4037145093
Short name T221
Test name
Test status
Simulation time 79528005417 ps
CPU time 248.8 seconds
Started Mar 21 12:47:31 PM PDT 24
Finished Mar 21 12:51:40 PM PDT 24
Peak memory 202128 kb
Host smart-2259d83a-3ad4-4dc1-b4aa-5c4c97c6783c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037145093 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.4037145093
Directory /workspace/45.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_lowpower_counter.2157637347
Short name T545
Test name
Test status
Simulation time 34559867921 ps
CPU time 17.47 seconds
Started Mar 21 12:47:31 PM PDT 24
Finished Mar 21 12:47:48 PM PDT 24
Peak memory 201540 kb
Host smart-fa5447c6-7c22-4fbe-8b3c-e1f154fe2d5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157637347 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.2157637347
Directory /workspace/45.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_poweron_counter.1017252881
Short name T104
Test name
Test status
Simulation time 4426401247 ps
CPU time 5.97 seconds
Started Mar 21 12:47:30 PM PDT 24
Finished Mar 21 12:47:36 PM PDT 24
Peak memory 201500 kb
Host smart-4eec65dc-969f-403e-bd04-75de0e030b2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017252881 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.1017252881
Directory /workspace/45.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_smoke.4289447550
Short name T8
Test name
Test status
Simulation time 5875410079 ps
CPU time 13.05 seconds
Started Mar 21 12:47:23 PM PDT 24
Finished Mar 21 12:47:36 PM PDT 24
Peak memory 201480 kb
Host smart-c812b8d0-e106-40b4-8d85-93ea6d7f60e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289447550 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.4289447550
Directory /workspace/45.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.3968832932
Short name T683
Test name
Test status
Simulation time 300108192863 ps
CPU time 173.21 seconds
Started Mar 21 12:47:30 PM PDT 24
Finished Mar 21 12:50:24 PM PDT 24
Peak memory 201924 kb
Host smart-f4f784a6-3891-4a62-9520-cf6a9f788aaf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968832932 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all_with_rand_reset.3968832932
Directory /workspace/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_alert_test.609788637
Short name T340
Test name
Test status
Simulation time 321925206 ps
CPU time 0.93 seconds
Started Mar 21 12:47:40 PM PDT 24
Finished Mar 21 12:47:41 PM PDT 24
Peak memory 201420 kb
Host smart-ba47767e-b02c-44e7-9c37-2c9dd04a6386
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609788637 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.609788637
Directory /workspace/46.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.adc_ctrl_clock_gating.3931553143
Short name T771
Test name
Test status
Simulation time 328276126737 ps
CPU time 105.87 seconds
Started Mar 21 12:47:30 PM PDT 24
Finished Mar 21 12:49:16 PM PDT 24
Peak memory 201728 kb
Host smart-bcf13ec7-a8d6-4e6f-8916-8ac73b680875
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931553143 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gat
ing.3931553143
Directory /workspace/46.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_both.7826719
Short name T160
Test name
Test status
Simulation time 506298646040 ps
CPU time 1137.32 seconds
Started Mar 21 12:47:31 PM PDT 24
Finished Mar 21 01:06:28 PM PDT 24
Peak memory 201808 kb
Host smart-9e6abeff-8603-4ecf-8ea9-9f6215966dd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7826719 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.7826719
Directory /workspace/46.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt.3119056444
Short name T735
Test name
Test status
Simulation time 326907332338 ps
CPU time 203.47 seconds
Started Mar 21 12:47:33 PM PDT 24
Finished Mar 21 12:50:57 PM PDT 24
Peak memory 201784 kb
Host smart-d2d26428-bb1a-48ac-bcb0-5ddca95ee4b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119056444 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.3119056444
Directory /workspace/46.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.2937246939
Short name T467
Test name
Test status
Simulation time 493853034389 ps
CPU time 252.26 seconds
Started Mar 21 12:47:30 PM PDT 24
Finished Mar 21 12:51:42 PM PDT 24
Peak memory 201712 kb
Host smart-bcf1f159-7f74-4c3c-a8cb-54db1f494f94
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937246939 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interru
pt_fixed.2937246939
Directory /workspace/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled.2509319204
Short name T732
Test name
Test status
Simulation time 337407221304 ps
CPU time 537.46 seconds
Started Mar 21 12:47:31 PM PDT 24
Finished Mar 21 12:56:29 PM PDT 24
Peak memory 201836 kb
Host smart-69bfb6d4-f4fc-4428-81c2-49118832c196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509319204 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.2509319204
Directory /workspace/46.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled_fixed.4164005025
Short name T696
Test name
Test status
Simulation time 493486430153 ps
CPU time 657.92 seconds
Started Mar 21 12:47:32 PM PDT 24
Finished Mar 21 12:58:30 PM PDT 24
Peak memory 201684 kb
Host smart-c5739a2d-e742-43bf-b617-6a4a2424ecd0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164005025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fix
ed.4164005025
Directory /workspace/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup.3615586827
Short name T292
Test name
Test status
Simulation time 341036668316 ps
CPU time 423.75 seconds
Started Mar 21 12:47:34 PM PDT 24
Finished Mar 21 12:54:37 PM PDT 24
Peak memory 201796 kb
Host smart-011f7547-311c-4708-b189-0e8385394bf5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615586827 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters
_wakeup.3615586827
Directory /workspace/46.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup_fixed.317332675
Short name T559
Test name
Test status
Simulation time 601407977757 ps
CPU time 614.27 seconds
Started Mar 21 12:47:32 PM PDT 24
Finished Mar 21 12:57:47 PM PDT 24
Peak memory 201796 kb
Host smart-9dc0f483-d5e7-4c90-88fc-946be2b69aa8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317332675 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
adc_ctrl_filters_wakeup_fixed.317332675
Directory /workspace/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_fsm_reset.1762070279
Short name T218
Test name
Test status
Simulation time 144397012107 ps
CPU time 512.7 seconds
Started Mar 21 12:47:39 PM PDT 24
Finished Mar 21 12:56:12 PM PDT 24
Peak memory 201980 kb
Host smart-18cdbe50-1d46-43e7-9daf-3bea9af18452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762070279 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.1762070279
Directory /workspace/46.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_lowpower_counter.588097232
Short name T778
Test name
Test status
Simulation time 38991916563 ps
CPU time 93.04 seconds
Started Mar 21 12:47:40 PM PDT 24
Finished Mar 21 12:49:13 PM PDT 24
Peak memory 201532 kb
Host smart-26b308d8-c81f-46d7-953f-fb627ec76f50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588097232 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.588097232
Directory /workspace/46.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_poweron_counter.1979183285
Short name T660
Test name
Test status
Simulation time 4766692373 ps
CPU time 3.34 seconds
Started Mar 21 12:47:31 PM PDT 24
Finished Mar 21 12:47:34 PM PDT 24
Peak memory 201488 kb
Host smart-66cfb83b-4cda-408e-81a1-5384dbd2c6ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979183285 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.1979183285
Directory /workspace/46.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_smoke.857455075
Short name T513
Test name
Test status
Simulation time 5823786227 ps
CPU time 13.73 seconds
Started Mar 21 12:47:31 PM PDT 24
Finished Mar 21 12:47:45 PM PDT 24
Peak memory 201536 kb
Host smart-2c6fedde-bdc0-4550-8763-42af66c803ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857455075 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.857455075
Directory /workspace/46.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all.2901841490
Short name T564
Test name
Test status
Simulation time 350340816465 ps
CPU time 404.35 seconds
Started Mar 21 12:47:41 PM PDT 24
Finished Mar 21 12:54:25 PM PDT 24
Peak memory 201676 kb
Host smart-754dc3e6-75cd-4345-afd1-152057b8f9cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901841490 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all
.2901841490
Directory /workspace/46.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.30918133
Short name T24
Test name
Test status
Simulation time 131289071652 ps
CPU time 337.39 seconds
Started Mar 21 12:47:40 PM PDT 24
Finished Mar 21 12:53:17 PM PDT 24
Peak memory 210940 kb
Host smart-0ed545a1-bca0-4d6e-98f8-c2e0f20a9e10
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30918133 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all_with_rand_reset.30918133
Directory /workspace/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_alert_test.207973750
Short name T404
Test name
Test status
Simulation time 352754876 ps
CPU time 1.44 seconds
Started Mar 21 12:47:53 PM PDT 24
Finished Mar 21 12:47:54 PM PDT 24
Peak memory 201400 kb
Host smart-ad0d8ba5-fb4a-4afc-9334-e230e4cb3fa0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207973750 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.207973750
Directory /workspace/47.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.adc_ctrl_clock_gating.3596125339
Short name T181
Test name
Test status
Simulation time 162688112864 ps
CPU time 170.36 seconds
Started Mar 21 12:47:40 PM PDT 24
Finished Mar 21 12:50:31 PM PDT 24
Peak memory 201720 kb
Host smart-26cb7c8a-83f3-4cfc-ae76-66d18b9e6b1e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596125339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gat
ing.3596125339
Directory /workspace/47.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt.2612827184
Short name T634
Test name
Test status
Simulation time 165561757218 ps
CPU time 89.32 seconds
Started Mar 21 12:47:39 PM PDT 24
Finished Mar 21 12:49:09 PM PDT 24
Peak memory 201812 kb
Host smart-0a2cedbd-7259-47db-966b-ab7b5fd9934e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612827184 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.2612827184
Directory /workspace/47.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt_fixed.2355656328
Short name T673
Test name
Test status
Simulation time 484241288973 ps
CPU time 593.23 seconds
Started Mar 21 12:47:39 PM PDT 24
Finished Mar 21 12:57:32 PM PDT 24
Peak memory 201700 kb
Host smart-0fbe3495-df75-4101-9868-df91ba10c440
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355656328 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interru
pt_fixed.2355656328
Directory /workspace/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled.2746816928
Short name T161
Test name
Test status
Simulation time 487912826519 ps
CPU time 313.15 seconds
Started Mar 21 12:47:39 PM PDT 24
Finished Mar 21 12:52:52 PM PDT 24
Peak memory 201932 kb
Host smart-0dbbb60a-ac6e-45dd-9df1-9bacd3924d3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746816928 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.2746816928
Directory /workspace/47.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled_fixed.2466918751
Short name T495
Test name
Test status
Simulation time 496382052783 ps
CPU time 1154.79 seconds
Started Mar 21 12:47:40 PM PDT 24
Finished Mar 21 01:06:55 PM PDT 24
Peak memory 201712 kb
Host smart-d5754eb7-b2d3-4ef6-8413-b058e7b8edc4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466918751 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fix
ed.2466918751
Directory /workspace/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup.1755768247
Short name T706
Test name
Test status
Simulation time 201298647949 ps
CPU time 116.14 seconds
Started Mar 21 12:47:40 PM PDT 24
Finished Mar 21 12:49:36 PM PDT 24
Peak memory 201680 kb
Host smart-8702fb6a-94f5-4272-a35f-c0d420cf7246
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755768247 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters
_wakeup.1755768247
Directory /workspace/47.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.3693659643
Short name T736
Test name
Test status
Simulation time 383188626907 ps
CPU time 872.89 seconds
Started Mar 21 12:47:41 PM PDT 24
Finished Mar 21 01:02:14 PM PDT 24
Peak memory 201744 kb
Host smart-3dc70144-244e-4932-b53a-83dcd46d3421
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693659643 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47
.adc_ctrl_filters_wakeup_fixed.3693659643
Directory /workspace/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_lowpower_counter.3228754570
Short name T96
Test name
Test status
Simulation time 21821407713 ps
CPU time 12.52 seconds
Started Mar 21 12:47:51 PM PDT 24
Finished Mar 21 12:48:04 PM PDT 24
Peak memory 201596 kb
Host smart-15f6fce5-f3fb-4bc5-8e09-25cc16e8e216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228754570 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.3228754570
Directory /workspace/47.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_poweron_counter.1539735091
Short name T338
Test name
Test status
Simulation time 3934085681 ps
CPU time 2.8 seconds
Started Mar 21 12:47:51 PM PDT 24
Finished Mar 21 12:47:54 PM PDT 24
Peak memory 201448 kb
Host smart-d1c3a293-da0c-46aa-94e7-08049bfecf38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539735091 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.1539735091
Directory /workspace/47.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_smoke.2569334370
Short name T535
Test name
Test status
Simulation time 5712579157 ps
CPU time 13 seconds
Started Mar 21 12:47:43 PM PDT 24
Finished Mar 21 12:47:56 PM PDT 24
Peak memory 201536 kb
Host smart-4d1d9bc3-fb9b-482c-a047-69bb76a2e159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569334370 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.2569334370
Directory /workspace/47.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all.4159558050
Short name T761
Test name
Test status
Simulation time 165596095126 ps
CPU time 593.32 seconds
Started Mar 21 12:47:51 PM PDT 24
Finished Mar 21 12:57:44 PM PDT 24
Peak memory 210392 kb
Host smart-1ed0f104-b53c-4ca5-8b62-c645ab4e76e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159558050 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all
.4159558050
Directory /workspace/47.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.3566616690
Short name T655
Test name
Test status
Simulation time 302832600927 ps
CPU time 289.36 seconds
Started Mar 21 12:47:52 PM PDT 24
Finished Mar 21 12:52:41 PM PDT 24
Peak memory 210404 kb
Host smart-e2fd76e3-36af-43bc-b39a-2391d36a2826
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566616690 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all_with_rand_reset.3566616690
Directory /workspace/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_alert_test.1929485032
Short name T522
Test name
Test status
Simulation time 353849447 ps
CPU time 1.38 seconds
Started Mar 21 12:48:00 PM PDT 24
Finished Mar 21 12:48:02 PM PDT 24
Peak memory 201392 kb
Host smart-7de18f7d-a10a-4b9d-8593-3c0a883c15c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929485032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.1929485032
Directory /workspace/48.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.adc_ctrl_clock_gating.3682586294
Short name T231
Test name
Test status
Simulation time 425218631605 ps
CPU time 268.84 seconds
Started Mar 21 12:47:51 PM PDT 24
Finished Mar 21 12:52:20 PM PDT 24
Peak memory 201712 kb
Host smart-99d2e98c-971a-407c-872d-668b1261cabf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682586294 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gat
ing.3682586294
Directory /workspace/48.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_both.2524903337
Short name T233
Test name
Test status
Simulation time 495840109651 ps
CPU time 1155.05 seconds
Started Mar 21 12:47:53 PM PDT 24
Finished Mar 21 01:07:08 PM PDT 24
Peak memory 201780 kb
Host smart-0a6b9c99-3bd7-454d-8b58-867813615f91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524903337 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.2524903337
Directory /workspace/48.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt.2547030639
Short name T582
Test name
Test status
Simulation time 158343080371 ps
CPU time 201.39 seconds
Started Mar 21 12:47:53 PM PDT 24
Finished Mar 21 12:51:15 PM PDT 24
Peak memory 201712 kb
Host smart-8c5533ae-4548-4b93-9472-cd3fe903caee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547030639 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.2547030639
Directory /workspace/48.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt_fixed.3416736020
Short name T776
Test name
Test status
Simulation time 497601408194 ps
CPU time 1106.75 seconds
Started Mar 21 12:47:50 PM PDT 24
Finished Mar 21 01:06:17 PM PDT 24
Peak memory 201712 kb
Host smart-d2441ae0-f105-4aa6-acc9-940100bb7edf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416736020 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interru
pt_fixed.3416736020
Directory /workspace/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled.1870712954
Short name T691
Test name
Test status
Simulation time 162829431975 ps
CPU time 185.27 seconds
Started Mar 21 12:47:53 PM PDT 24
Finished Mar 21 12:50:58 PM PDT 24
Peak memory 201736 kb
Host smart-8a000639-dff0-4be4-a4cc-7dc5ba2393b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870712954 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.1870712954
Directory /workspace/48.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled_fixed.2472924910
Short name T542
Test name
Test status
Simulation time 484970524194 ps
CPU time 588.08 seconds
Started Mar 21 12:47:49 PM PDT 24
Finished Mar 21 12:57:38 PM PDT 24
Peak memory 201836 kb
Host smart-a70883bd-7444-4f84-b95f-dc6d565d3b6f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472924910 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fix
ed.2472924910
Directory /workspace/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup.688639889
Short name T268
Test name
Test status
Simulation time 535936325528 ps
CPU time 1287.56 seconds
Started Mar 21 12:47:52 PM PDT 24
Finished Mar 21 01:09:20 PM PDT 24
Peak memory 201708 kb
Host smart-149ad880-3b81-4ec0-9b6c-5e2ff32b1f3d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688639889 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_
wakeup.688639889
Directory /workspace/48.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.1461961035
Short name T695
Test name
Test status
Simulation time 621135720773 ps
CPU time 673.12 seconds
Started Mar 21 12:47:50 PM PDT 24
Finished Mar 21 12:59:03 PM PDT 24
Peak memory 201724 kb
Host smart-38428738-1570-4584-a28e-c7c5972687f2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461961035 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48
.adc_ctrl_filters_wakeup_fixed.1461961035
Directory /workspace/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_fsm_reset.1781793444
Short name T323
Test name
Test status
Simulation time 74311969416 ps
CPU time 384.33 seconds
Started Mar 21 12:47:59 PM PDT 24
Finished Mar 21 12:54:23 PM PDT 24
Peak memory 202160 kb
Host smart-f62f670b-e96f-42e6-ae4b-c4684993f2e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781793444 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.1781793444
Directory /workspace/48.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_lowpower_counter.1917096828
Short name T342
Test name
Test status
Simulation time 41845415113 ps
CPU time 92 seconds
Started Mar 21 12:47:51 PM PDT 24
Finished Mar 21 12:49:23 PM PDT 24
Peak memory 201556 kb
Host smart-103ffeec-6fff-4fe2-8295-34b3b2a3d52d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917096828 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.1917096828
Directory /workspace/48.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_poweron_counter.331405070
Short name T710
Test name
Test status
Simulation time 3440444428 ps
CPU time 8.04 seconds
Started Mar 21 12:47:51 PM PDT 24
Finished Mar 21 12:47:59 PM PDT 24
Peak memory 201472 kb
Host smart-dbd7d854-46fa-4cba-a74b-faa8fc007834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331405070 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.331405070
Directory /workspace/48.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_smoke.1712279112
Short name T585
Test name
Test status
Simulation time 5639162809 ps
CPU time 4.14 seconds
Started Mar 21 12:47:51 PM PDT 24
Finished Mar 21 12:47:56 PM PDT 24
Peak memory 201552 kb
Host smart-42288ad1-66cf-48f4-b152-787c0cd72b04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712279112 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.1712279112
Directory /workspace/48.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all.199014149
Short name T26
Test name
Test status
Simulation time 389130771502 ps
CPU time 1337.03 seconds
Started Mar 21 12:48:00 PM PDT 24
Finished Mar 21 01:10:18 PM PDT 24
Peak memory 218516 kb
Host smart-40441823-a9bb-4cd6-9e85-5758c1147aaf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199014149 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all.
199014149
Directory /workspace/48.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.1197874380
Short name T731
Test name
Test status
Simulation time 37719676852 ps
CPU time 59.8 seconds
Started Mar 21 12:48:03 PM PDT 24
Finished Mar 21 12:49:03 PM PDT 24
Peak memory 210784 kb
Host smart-d1c9e37a-4c0b-44d0-98f9-f09ccbce37d0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197874380 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all_with_rand_reset.1197874380
Directory /workspace/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_alert_test.3592077922
Short name T363
Test name
Test status
Simulation time 302262243 ps
CPU time 1.28 seconds
Started Mar 21 12:48:01 PM PDT 24
Finished Mar 21 12:48:02 PM PDT 24
Peak memory 201348 kb
Host smart-f54ca9f8-9285-4e4b-9dab-c3cb6f8adf44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592077922 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.3592077922
Directory /workspace/49.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.adc_ctrl_clock_gating.293987520
Short name T296
Test name
Test status
Simulation time 498700213760 ps
CPU time 301.4 seconds
Started Mar 21 12:48:00 PM PDT 24
Finished Mar 21 12:53:02 PM PDT 24
Peak memory 201784 kb
Host smart-0131a8fe-3172-4197-ad23-01bdbf9d870a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293987520 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gati
ng.293987520
Directory /workspace/49.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_both.3443025358
Short name T488
Test name
Test status
Simulation time 509182130572 ps
CPU time 332.55 seconds
Started Mar 21 12:48:01 PM PDT 24
Finished Mar 21 12:53:34 PM PDT 24
Peak memory 201708 kb
Host smart-e9c2c754-b492-4a1e-987c-2988052e14e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443025358 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.3443025358
Directory /workspace/49.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt_fixed.95489311
Short name T480
Test name
Test status
Simulation time 165873850917 ps
CPU time 374.19 seconds
Started Mar 21 12:48:01 PM PDT 24
Finished Mar 21 12:54:15 PM PDT 24
Peak memory 201704 kb
Host smart-43576e06-4cb2-426c-8238-ba0f613c6e92
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=95489311 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt
_fixed.95489311
Directory /workspace/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled.290957073
Short name T729
Test name
Test status
Simulation time 163925468987 ps
CPU time 58.31 seconds
Started Mar 21 12:48:01 PM PDT 24
Finished Mar 21 12:49:00 PM PDT 24
Peak memory 201808 kb
Host smart-29f97cd4-388f-4ad1-bf04-e310c2474417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290957073 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.290957073
Directory /workspace/49.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled_fixed.2524339990
Short name T172
Test name
Test status
Simulation time 166783329742 ps
CPU time 98.79 seconds
Started Mar 21 12:48:01 PM PDT 24
Finished Mar 21 12:49:40 PM PDT 24
Peak memory 201720 kb
Host smart-167e453b-ea66-458c-9e8f-5adae84e0658
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524339990 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fix
ed.2524339990
Directory /workspace/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup.1800252860
Short name T753
Test name
Test status
Simulation time 336811862778 ps
CPU time 514.08 seconds
Started Mar 21 12:48:02 PM PDT 24
Finished Mar 21 12:56:36 PM PDT 24
Peak memory 201820 kb
Host smart-58d79bbb-fb3a-483c-8893-c74ebbab3f04
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800252860 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters
_wakeup.1800252860
Directory /workspace/49.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup_fixed.2577919394
Short name T679
Test name
Test status
Simulation time 400785994067 ps
CPU time 865.42 seconds
Started Mar 21 12:48:01 PM PDT 24
Finished Mar 21 01:02:28 PM PDT 24
Peak memory 201772 kb
Host smart-4e83e16d-b2eb-4b5f-9d0c-33d9de1b5cdd
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577919394 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49
.adc_ctrl_filters_wakeup_fixed.2577919394
Directory /workspace/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_fsm_reset.3248024412
Short name T222
Test name
Test status
Simulation time 146084029164 ps
CPU time 540.89 seconds
Started Mar 21 12:48:01 PM PDT 24
Finished Mar 21 12:57:02 PM PDT 24
Peak memory 202088 kb
Host smart-c9689a57-4c18-4b89-b547-00309fc124b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248024412 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.3248024412
Directory /workspace/49.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_lowpower_counter.2939910661
Short name T360
Test name
Test status
Simulation time 42275039966 ps
CPU time 22.28 seconds
Started Mar 21 12:48:00 PM PDT 24
Finished Mar 21 12:48:23 PM PDT 24
Peak memory 201508 kb
Host smart-f8209dae-320e-4574-8b63-fa0665b6bf4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939910661 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.2939910661
Directory /workspace/49.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_poweron_counter.2696877666
Short name T568
Test name
Test status
Simulation time 3112214749 ps
CPU time 2.54 seconds
Started Mar 21 12:47:58 PM PDT 24
Finished Mar 21 12:48:01 PM PDT 24
Peak memory 201456 kb
Host smart-d9ecc7c8-2b22-492a-ac23-ab01bffd9c31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696877666 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.2696877666
Directory /workspace/49.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_smoke.2219202615
Short name T168
Test name
Test status
Simulation time 5879333006 ps
CPU time 4.59 seconds
Started Mar 21 12:48:01 PM PDT 24
Finished Mar 21 12:48:07 PM PDT 24
Peak memory 201632 kb
Host smart-e332ed86-adbe-4081-a351-aa231d690ff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219202615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.2219202615
Directory /workspace/49.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all.569712018
Short name T289
Test name
Test status
Simulation time 627258756715 ps
CPU time 1127.03 seconds
Started Mar 21 12:48:00 PM PDT 24
Finished Mar 21 01:06:48 PM PDT 24
Peak memory 210340 kb
Host smart-a4f3348b-1bb4-4903-b24b-cbed3f119f00
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569712018 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all.
569712018
Directory /workspace/49.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.892514516
Short name T60
Test name
Test status
Simulation time 144086737131 ps
CPU time 301.2 seconds
Started Mar 21 12:48:03 PM PDT 24
Finished Mar 21 12:53:05 PM PDT 24
Peak memory 210408 kb
Host smart-094be09a-1618-49d6-bde0-6998d75c21c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892514516 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all_with_rand_reset.892514516
Directory /workspace/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_alert_test.1897463659
Short name T733
Test name
Test status
Simulation time 385903755 ps
CPU time 0.88 seconds
Started Mar 21 12:44:23 PM PDT 24
Finished Mar 21 12:44:24 PM PDT 24
Peak memory 201424 kb
Host smart-065a8198-83ca-454b-b756-488cd823bdb2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897463659 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.1897463659
Directory /workspace/5.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.adc_ctrl_clock_gating.3741630015
Short name T427
Test name
Test status
Simulation time 167340128629 ps
CPU time 92.44 seconds
Started Mar 21 12:44:25 PM PDT 24
Finished Mar 21 12:45:57 PM PDT 24
Peak memory 201884 kb
Host smart-f85eae27-e9f9-4f00-8c0f-0557323fc3d5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741630015 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gati
ng.3741630015
Directory /workspace/5.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt.2251253281
Short name T166
Test name
Test status
Simulation time 165840289944 ps
CPU time 54.83 seconds
Started Mar 21 12:44:21 PM PDT 24
Finished Mar 21 12:45:16 PM PDT 24
Peak memory 201804 kb
Host smart-3a10a692-6357-4b00-b66c-9ef6de797e01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251253281 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.2251253281
Directory /workspace/5.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt_fixed.2733277552
Short name T511
Test name
Test status
Simulation time 329601051194 ps
CPU time 193.76 seconds
Started Mar 21 12:44:22 PM PDT 24
Finished Mar 21 12:47:36 PM PDT 24
Peak memory 201772 kb
Host smart-9f2bd629-27c7-41ee-a890-0da39faa05f8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733277552 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrup
t_fixed.2733277552
Directory /workspace/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled.1045041010
Short name T274
Test name
Test status
Simulation time 327412392337 ps
CPU time 748.51 seconds
Started Mar 21 12:44:21 PM PDT 24
Finished Mar 21 12:56:50 PM PDT 24
Peak memory 201784 kb
Host smart-401a2b6c-3fda-4edf-985f-9597221225a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045041010 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.1045041010
Directory /workspace/5.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled_fixed.3837195619
Short name T430
Test name
Test status
Simulation time 166482968017 ps
CPU time 406.23 seconds
Started Mar 21 12:44:20 PM PDT 24
Finished Mar 21 12:51:06 PM PDT 24
Peak memory 201796 kb
Host smart-a5fa03a6-5039-44d6-9e6e-270cf905a866
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837195619 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixe
d.3837195619
Directory /workspace/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup.3966143320
Short name T163
Test name
Test status
Simulation time 420113967084 ps
CPU time 269.62 seconds
Started Mar 21 12:44:21 PM PDT 24
Finished Mar 21 12:48:51 PM PDT 24
Peak memory 201940 kb
Host smart-ce4a35d9-a1a1-4380-be34-a3d428af0027
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966143320 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_
wakeup.3966143320
Directory /workspace/5.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup_fixed.522017176
Short name T330
Test name
Test status
Simulation time 612125924899 ps
CPU time 1501.43 seconds
Started Mar 21 12:44:22 PM PDT 24
Finished Mar 21 01:09:24 PM PDT 24
Peak memory 201720 kb
Host smart-e4779583-9946-4f69-8da1-6e99548a1c6b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522017176 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.a
dc_ctrl_filters_wakeup_fixed.522017176
Directory /workspace/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_fsm_reset.701276565
Short name T208
Test name
Test status
Simulation time 120051747981 ps
CPU time 381.44 seconds
Started Mar 21 12:44:21 PM PDT 24
Finished Mar 21 12:50:43 PM PDT 24
Peak memory 202052 kb
Host smart-08d75bc0-ab05-49a0-b448-7d8d661be154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701276565 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.701276565
Directory /workspace/5.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_lowpower_counter.17500821
Short name T594
Test name
Test status
Simulation time 32005840763 ps
CPU time 10.22 seconds
Started Mar 21 12:44:22 PM PDT 24
Finished Mar 21 12:44:32 PM PDT 24
Peak memory 201788 kb
Host smart-6182a1b3-18c4-4929-a441-79187aa3ebb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17500821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.17500821
Directory /workspace/5.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_poweron_counter.3491452017
Short name T444
Test name
Test status
Simulation time 3522693030 ps
CPU time 8.92 seconds
Started Mar 21 12:44:22 PM PDT 24
Finished Mar 21 12:44:31 PM PDT 24
Peak memory 201468 kb
Host smart-2e403cdc-650a-41b5-8503-12d1c47986aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491452017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.3491452017
Directory /workspace/5.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_smoke.3003674624
Short name T365
Test name
Test status
Simulation time 5939318912 ps
CPU time 11.21 seconds
Started Mar 21 12:44:24 PM PDT 24
Finished Mar 21 12:44:36 PM PDT 24
Peak memory 201236 kb
Host smart-15ee42b1-9633-40db-8519-37f35591d876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003674624 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.3003674624
Directory /workspace/5.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.2279208856
Short name T674
Test name
Test status
Simulation time 118823623367 ps
CPU time 143.24 seconds
Started Mar 21 12:44:24 PM PDT 24
Finished Mar 21 12:46:47 PM PDT 24
Peak memory 201996 kb
Host smart-b6ec42f8-2c11-47de-8285-bc6fda174935
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279208856 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all_with_rand_reset.2279208856
Directory /workspace/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_alert_test.2788817032
Short name T426
Test name
Test status
Simulation time 432157933 ps
CPU time 0.89 seconds
Started Mar 21 12:44:26 PM PDT 24
Finished Mar 21 12:44:27 PM PDT 24
Peak memory 201548 kb
Host smart-7319acc1-b36f-4a13-89fe-1c84d43a2a17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788817032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.2788817032
Directory /workspace/6.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.adc_ctrl_clock_gating.1556252177
Short name T433
Test name
Test status
Simulation time 164017854486 ps
CPU time 276.85 seconds
Started Mar 21 12:44:22 PM PDT 24
Finished Mar 21 12:48:59 PM PDT 24
Peak memory 201784 kb
Host smart-7b0c9601-ae5a-4ad8-9f43-6460b873f53d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556252177 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gati
ng.1556252177
Directory /workspace/6.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_both.4120259158
Short name T309
Test name
Test status
Simulation time 324879388584 ps
CPU time 98.6 seconds
Started Mar 21 12:44:22 PM PDT 24
Finished Mar 21 12:46:01 PM PDT 24
Peak memory 201736 kb
Host smart-8fc6bf8e-caef-4ed5-9cad-d235981130ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120259158 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.4120259158
Directory /workspace/6.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt.3464009278
Short name T144
Test name
Test status
Simulation time 491683594354 ps
CPU time 1200.49 seconds
Started Mar 21 12:44:20 PM PDT 24
Finished Mar 21 01:04:21 PM PDT 24
Peak memory 201696 kb
Host smart-f981b554-8ff4-458a-93d6-febdeeefddfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464009278 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.3464009278
Directory /workspace/6.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt_fixed.1594469358
Short name T385
Test name
Test status
Simulation time 335111895394 ps
CPU time 410.06 seconds
Started Mar 21 12:44:18 PM PDT 24
Finished Mar 21 12:51:08 PM PDT 24
Peak memory 201696 kb
Host smart-0d3e3d8b-7532-4f49-be25-21d6904c6eab
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594469358 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrup
t_fixed.1594469358
Directory /workspace/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.516157064
Short name T185
Test name
Test status
Simulation time 491151350492 ps
CPU time 119.79 seconds
Started Mar 21 12:44:23 PM PDT 24
Finished Mar 21 12:46:23 PM PDT 24
Peak memory 201780 kb
Host smart-58409988-8742-43ce-8129-3fedb6fc0cd7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=516157064 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixed
.516157064
Directory /workspace/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup_fixed.3960792055
Short name T584
Test name
Test status
Simulation time 201361222518 ps
CPU time 458.39 seconds
Started Mar 21 12:44:20 PM PDT 24
Finished Mar 21 12:51:58 PM PDT 24
Peak memory 201676 kb
Host smart-50d5ab24-98ff-4aac-b103-cb445c9bb072
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960792055 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.
adc_ctrl_filters_wakeup_fixed.3960792055
Directory /workspace/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_fsm_reset.1490300525
Short name T769
Test name
Test status
Simulation time 133777872056 ps
CPU time 728.14 seconds
Started Mar 21 12:44:25 PM PDT 24
Finished Mar 21 12:56:34 PM PDT 24
Peak memory 202072 kb
Host smart-300afcf4-3ce8-41a6-8211-f4bf7aa4cd53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490300525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.1490300525
Directory /workspace/6.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_lowpower_counter.1523707035
Short name T90
Test name
Test status
Simulation time 41903504653 ps
CPU time 22.27 seconds
Started Mar 21 12:44:22 PM PDT 24
Finished Mar 21 12:44:45 PM PDT 24
Peak memory 201512 kb
Host smart-beef51b0-fcac-4316-887a-45ae446c6523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523707035 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.1523707035
Directory /workspace/6.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_poweron_counter.1766426670
Short name T331
Test name
Test status
Simulation time 3295236055 ps
CPU time 8.87 seconds
Started Mar 21 12:44:21 PM PDT 24
Finished Mar 21 12:44:30 PM PDT 24
Peak memory 201476 kb
Host smart-ba4b5b44-cef6-4ed0-8720-36abd4a22904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766426670 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.1766426670
Directory /workspace/6.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_smoke.2900620063
Short name T3
Test name
Test status
Simulation time 5834986492 ps
CPU time 13.46 seconds
Started Mar 21 12:44:19 PM PDT 24
Finished Mar 21 12:44:32 PM PDT 24
Peak memory 201608 kb
Host smart-b71d20d5-29a5-48f0-ae0b-80fac63d18a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900620063 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.2900620063
Directory /workspace/6.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all.2449645884
Short name T261
Test name
Test status
Simulation time 656345766954 ps
CPU time 412.62 seconds
Started Mar 21 12:44:22 PM PDT 24
Finished Mar 21 12:51:14 PM PDT 24
Peak memory 201852 kb
Host smart-955f66a5-9560-4d11-82ee-4ee8dd453a8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449645884 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.
2449645884
Directory /workspace/6.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.1528927714
Short name T258
Test name
Test status
Simulation time 169454768936 ps
CPU time 102.2 seconds
Started Mar 21 12:44:22 PM PDT 24
Finished Mar 21 12:46:04 PM PDT 24
Peak memory 201908 kb
Host smart-2c00f227-da80-4a2c-bb08-117b837d94e2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528927714 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all_with_rand_reset.1528927714
Directory /workspace/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_alert_test.1392590940
Short name T4
Test name
Test status
Simulation time 393622680 ps
CPU time 1.58 seconds
Started Mar 21 12:44:21 PM PDT 24
Finished Mar 21 12:44:22 PM PDT 24
Peak memory 201368 kb
Host smart-9fd6d1d0-c324-4bdc-a9a1-d3f5aaeb70c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392590940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.1392590940
Directory /workspace/7.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.adc_ctrl_clock_gating.113407187
Short name T600
Test name
Test status
Simulation time 459598206629 ps
CPU time 463.28 seconds
Started Mar 21 12:44:21 PM PDT 24
Finished Mar 21 12:52:05 PM PDT 24
Peak memory 201792 kb
Host smart-01298bfb-3d82-4450-a4c0-db4fdb6d1f9c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113407187 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gatin
g.113407187
Directory /workspace/7.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_both.931386371
Short name T675
Test name
Test status
Simulation time 159947566325 ps
CPU time 198.37 seconds
Started Mar 21 12:44:23 PM PDT 24
Finished Mar 21 12:47:41 PM PDT 24
Peak memory 201804 kb
Host smart-447ffde9-4c1c-4c24-97e7-0cad880d2d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931386371 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.931386371
Directory /workspace/7.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt.117547302
Short name T272
Test name
Test status
Simulation time 164946491855 ps
CPU time 88.46 seconds
Started Mar 21 12:44:24 PM PDT 24
Finished Mar 21 12:45:52 PM PDT 24
Peak memory 201684 kb
Host smart-0b4847ba-c066-4945-93d8-1910a58f7d6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117547302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.117547302
Directory /workspace/7.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt_fixed.2668346599
Short name T76
Test name
Test status
Simulation time 486389343254 ps
CPU time 1079.7 seconds
Started Mar 21 12:44:28 PM PDT 24
Finished Mar 21 01:02:28 PM PDT 24
Peak memory 201840 kb
Host smart-ddbc3004-0643-47cf-b605-9631807a22d9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668346599 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrup
t_fixed.2668346599
Directory /workspace/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled.3506765104
Short name T654
Test name
Test status
Simulation time 165020722077 ps
CPU time 178.81 seconds
Started Mar 21 12:44:20 PM PDT 24
Finished Mar 21 12:47:18 PM PDT 24
Peak memory 201700 kb
Host smart-8a73b07b-2f34-4de0-92d8-c9941309f89a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506765104 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.3506765104
Directory /workspace/7.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled_fixed.3859781748
Short name T156
Test name
Test status
Simulation time 508196476056 ps
CPU time 1246.17 seconds
Started Mar 21 12:44:23 PM PDT 24
Finished Mar 21 01:05:09 PM PDT 24
Peak memory 201800 kb
Host smart-530622ac-a12e-41fe-bc7c-e1631dbd8a15
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859781748 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixe
d.3859781748
Directory /workspace/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup_fixed.61930769
Short name T337
Test name
Test status
Simulation time 208172651178 ps
CPU time 468.43 seconds
Started Mar 21 12:44:24 PM PDT 24
Finished Mar 21 12:52:13 PM PDT 24
Peak memory 201436 kb
Host smart-d4805749-bbf2-4725-b241-33af911bbc18
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61930769 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.ad
c_ctrl_filters_wakeup_fixed.61930769
Directory /workspace/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_fsm_reset.1210752817
Short name T328
Test name
Test status
Simulation time 94605291393 ps
CPU time 392.51 seconds
Started Mar 21 12:44:21 PM PDT 24
Finished Mar 21 12:50:54 PM PDT 24
Peak memory 202016 kb
Host smart-b99ec3f9-0574-4eb0-8065-c9e870b3da56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210752817 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.1210752817
Directory /workspace/7.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_lowpower_counter.1989866017
Short name T460
Test name
Test status
Simulation time 29433037164 ps
CPU time 64.95 seconds
Started Mar 21 12:44:24 PM PDT 24
Finished Mar 21 12:45:29 PM PDT 24
Peak memory 201596 kb
Host smart-e1043cf7-bd8a-4eb8-a058-f675b71a43cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989866017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.1989866017
Directory /workspace/7.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_poweron_counter.2675235393
Short name T434
Test name
Test status
Simulation time 5097610321 ps
CPU time 3.63 seconds
Started Mar 21 12:44:25 PM PDT 24
Finished Mar 21 12:44:29 PM PDT 24
Peak memory 201520 kb
Host smart-ad6cc808-ba6c-4439-8e85-a903aefa802b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675235393 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.2675235393
Directory /workspace/7.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_smoke.768448044
Short name T752
Test name
Test status
Simulation time 5723530301 ps
CPU time 7.06 seconds
Started Mar 21 12:44:21 PM PDT 24
Finished Mar 21 12:44:28 PM PDT 24
Peak memory 201540 kb
Host smart-0549aaa5-ebde-4d94-b18c-050451258187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768448044 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.768448044
Directory /workspace/7.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.1881992181
Short name T704
Test name
Test status
Simulation time 100236929799 ps
CPU time 215.31 seconds
Started Mar 21 12:44:23 PM PDT 24
Finished Mar 21 12:47:59 PM PDT 24
Peak memory 210100 kb
Host smart-ab13b5e6-ba79-464e-9fd0-4c500cf31310
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881992181 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all_with_rand_reset.1881992181
Directory /workspace/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_alert_test.1037696007
Short name T576
Test name
Test status
Simulation time 424696690 ps
CPU time 0.88 seconds
Started Mar 21 12:44:23 PM PDT 24
Finished Mar 21 12:44:23 PM PDT 24
Peak memory 201532 kb
Host smart-eb403135-3ed1-4f77-b8d5-29d512ee6109
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037696007 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.1037696007
Directory /workspace/8.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.adc_ctrl_clock_gating.1684129992
Short name T490
Test name
Test status
Simulation time 335786287606 ps
CPU time 77.33 seconds
Started Mar 21 12:44:27 PM PDT 24
Finished Mar 21 12:45:45 PM PDT 24
Peak memory 201796 kb
Host smart-37357741-6930-4627-9a86-fe12e66d5d6a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684129992 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gati
ng.1684129992
Directory /workspace/8.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_both.1968776104
Short name T178
Test name
Test status
Simulation time 352433397574 ps
CPU time 75.12 seconds
Started Mar 21 12:44:23 PM PDT 24
Finished Mar 21 12:45:39 PM PDT 24
Peak memory 201680 kb
Host smart-9945f5b5-b45b-419a-96a6-b07a0f4c998b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968776104 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.1968776104
Directory /workspace/8.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt.3041418658
Short name T431
Test name
Test status
Simulation time 324956028288 ps
CPU time 690.26 seconds
Started Mar 21 12:44:25 PM PDT 24
Finished Mar 21 12:55:56 PM PDT 24
Peak memory 201776 kb
Host smart-56ddc4e1-27c5-428b-855f-abea63d0dded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041418658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.3041418658
Directory /workspace/8.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt_fixed.491157942
Short name T382
Test name
Test status
Simulation time 331322983255 ps
CPU time 181.2 seconds
Started Mar 21 12:44:22 PM PDT 24
Finished Mar 21 12:47:23 PM PDT 24
Peak memory 201684 kb
Host smart-0cdf0671-8c6c-4521-a57f-3647500722ea
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=491157942 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt
_fixed.491157942
Directory /workspace/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled.1341704391
Short name T451
Test name
Test status
Simulation time 332445671246 ps
CPU time 768.43 seconds
Started Mar 21 12:44:22 PM PDT 24
Finished Mar 21 12:57:10 PM PDT 24
Peak memory 201772 kb
Host smart-2d1c2976-15ad-4616-8f60-8902b85bf192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341704391 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.1341704391
Directory /workspace/8.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.1403526717
Short name T381
Test name
Test status
Simulation time 332039309167 ps
CPU time 192.75 seconds
Started Mar 21 12:44:20 PM PDT 24
Finished Mar 21 12:47:33 PM PDT 24
Peak memory 201700 kb
Host smart-c78d9658-991c-485b-aa7e-187709e456d1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403526717 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixe
d.1403526717
Directory /workspace/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup_fixed.580918208
Short name T520
Test name
Test status
Simulation time 399688465451 ps
CPU time 89.37 seconds
Started Mar 21 12:44:30 PM PDT 24
Finished Mar 21 12:45:59 PM PDT 24
Peak memory 201776 kb
Host smart-c6796af9-2d9d-4a6b-9ad7-860618b280e9
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580918208 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.a
dc_ctrl_filters_wakeup_fixed.580918208
Directory /workspace/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_fsm_reset.3848813725
Short name T738
Test name
Test status
Simulation time 82021777993 ps
CPU time 344.35 seconds
Started Mar 21 12:44:24 PM PDT 24
Finished Mar 21 12:50:09 PM PDT 24
Peak memory 202012 kb
Host smart-0b8c4556-36f1-4046-b104-b7e70beffa30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848813725 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.3848813725
Directory /workspace/8.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_lowpower_counter.1563721013
Short name T630
Test name
Test status
Simulation time 22635976795 ps
CPU time 7.36 seconds
Started Mar 21 12:44:27 PM PDT 24
Finished Mar 21 12:44:34 PM PDT 24
Peak memory 201432 kb
Host smart-e2d31946-5443-47f6-8ec7-0ded54ddc372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563721013 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.1563721013
Directory /workspace/8.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_poweron_counter.1577704845
Short name T669
Test name
Test status
Simulation time 2931816125 ps
CPU time 2.63 seconds
Started Mar 21 12:44:21 PM PDT 24
Finished Mar 21 12:44:24 PM PDT 24
Peak memory 201452 kb
Host smart-e594ae33-8da6-4cf1-99b7-fc9d82c833cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577704845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.1577704845
Directory /workspace/8.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_smoke.64283400
Short name T636
Test name
Test status
Simulation time 5725641731 ps
CPU time 2.5 seconds
Started Mar 21 12:44:22 PM PDT 24
Finished Mar 21 12:44:24 PM PDT 24
Peak memory 201536 kb
Host smart-be165409-0da7-4aa5-a8bf-950c0ba8291c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64283400 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.64283400
Directory /workspace/8.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all.3180968323
Short name T754
Test name
Test status
Simulation time 336291920899 ps
CPU time 414.71 seconds
Started Mar 21 12:44:28 PM PDT 24
Finished Mar 21 12:51:22 PM PDT 24
Peak memory 201776 kb
Host smart-9a674884-aee7-44b2-aabb-efb24fd7cc2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180968323 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.
3180968323
Directory /workspace/8.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.187222443
Short name T199
Test name
Test status
Simulation time 221660580843 ps
CPU time 264.66 seconds
Started Mar 21 12:44:30 PM PDT 24
Finished Mar 21 12:48:55 PM PDT 24
Peak memory 210424 kb
Host smart-8533cdd2-b8b3-4f9b-955b-9e3d8bffdc57
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187222443 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all_with_rand_reset.187222443
Directory /workspace/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_alert_test.2087494939
Short name T92
Test name
Test status
Simulation time 400434972 ps
CPU time 0.78 seconds
Started Mar 21 12:44:34 PM PDT 24
Finished Mar 21 12:44:35 PM PDT 24
Peak memory 201412 kb
Host smart-cd362023-2df5-404a-923b-b93cbf0c1f80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087494939 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.2087494939
Directory /workspace/9.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.adc_ctrl_clock_gating.490638035
Short name T262
Test name
Test status
Simulation time 170500018164 ps
CPU time 85.43 seconds
Started Mar 21 12:44:39 PM PDT 24
Finished Mar 21 12:46:04 PM PDT 24
Peak memory 201664 kb
Host smart-03e56fb3-865c-446d-8acd-cd135848a02b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490638035 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gatin
g.490638035
Directory /workspace/9.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt.795610269
Short name T740
Test name
Test status
Simulation time 165670601742 ps
CPU time 133.93 seconds
Started Mar 21 12:44:24 PM PDT 24
Finished Mar 21 12:46:38 PM PDT 24
Peak memory 201616 kb
Host smart-bba9410a-5c86-469a-b19c-caf38dd1371e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795610269 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.795610269
Directory /workspace/9.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt_fixed.2973357329
Short name T202
Test name
Test status
Simulation time 324780878324 ps
CPU time 185.46 seconds
Started Mar 21 12:44:38 PM PDT 24
Finished Mar 21 12:47:44 PM PDT 24
Peak memory 201664 kb
Host smart-6063b3c6-7ff2-4daa-91b2-77375b17cbd6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973357329 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrup
t_fixed.2973357329
Directory /workspace/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled.3202861627
Short name T151
Test name
Test status
Simulation time 163093502435 ps
CPU time 57.68 seconds
Started Mar 21 12:44:24 PM PDT 24
Finished Mar 21 12:45:22 PM PDT 24
Peak memory 201720 kb
Host smart-2191454a-5953-4e53-926c-c69f71eb0d74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202861627 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.3202861627
Directory /workspace/9.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled_fixed.2402992302
Short name T193
Test name
Test status
Simulation time 492729302850 ps
CPU time 283.19 seconds
Started Mar 21 12:44:27 PM PDT 24
Finished Mar 21 12:49:10 PM PDT 24
Peak memory 201616 kb
Host smart-758def08-6e75-4e59-aa77-59af534cc77a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402992302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixe
d.2402992302
Directory /workspace/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup.3916576219
Short name T252
Test name
Test status
Simulation time 386872335257 ps
CPU time 466.35 seconds
Started Mar 21 12:44:35 PM PDT 24
Finished Mar 21 12:52:22 PM PDT 24
Peak memory 201784 kb
Host smart-fa97ed84-eff6-4ea5-bcc6-3eadd9bec2cb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916576219 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_
wakeup.3916576219
Directory /workspace/9.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup_fixed.3713747514
Short name T395
Test name
Test status
Simulation time 387320491798 ps
CPU time 420.77 seconds
Started Mar 21 12:44:35 PM PDT 24
Finished Mar 21 12:51:37 PM PDT 24
Peak memory 201716 kb
Host smart-cff906d4-9b7a-4405-b8a4-ec9cb2f3a6d6
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713747514 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.
adc_ctrl_filters_wakeup_fixed.3713747514
Directory /workspace/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_fsm_reset.3514813556
Short name T759
Test name
Test status
Simulation time 133664579793 ps
CPU time 664.51 seconds
Started Mar 21 12:44:33 PM PDT 24
Finished Mar 21 12:55:38 PM PDT 24
Peak memory 202108 kb
Host smart-1245b7b2-7ba1-4347-aa8d-3b7cb7d57ff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514813556 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.3514813556
Directory /workspace/9.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_lowpower_counter.3285708299
Short name T477
Test name
Test status
Simulation time 42343191211 ps
CPU time 29.15 seconds
Started Mar 21 12:44:33 PM PDT 24
Finished Mar 21 12:45:02 PM PDT 24
Peak memory 201468 kb
Host smart-0ea8d89e-cd8b-4e91-bc03-26e69d7baa15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285708299 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.3285708299
Directory /workspace/9.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_poweron_counter.1368743079
Short name T502
Test name
Test status
Simulation time 4545957290 ps
CPU time 5.63 seconds
Started Mar 21 12:44:34 PM PDT 24
Finished Mar 21 12:44:40 PM PDT 24
Peak memory 201484 kb
Host smart-c58cabd6-6567-4b6d-b861-2a49b535dc8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368743079 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.1368743079
Directory /workspace/9.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_smoke.3143496861
Short name T549
Test name
Test status
Simulation time 6055453420 ps
CPU time 8.62 seconds
Started Mar 21 12:44:24 PM PDT 24
Finished Mar 21 12:44:33 PM PDT 24
Peak memory 201544 kb
Host smart-7f9a565b-e7f1-4af9-8fd8-9c1dfedfafe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143496861 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.3143496861
Directory /workspace/9.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.4208708742
Short name T326
Test name
Test status
Simulation time 246589001457 ps
CPU time 357.95 seconds
Started Mar 21 12:44:35 PM PDT 24
Finished Mar 21 12:50:33 PM PDT 24
Peak memory 210484 kb
Host smart-45c382ed-9d19-4ecc-aa59-855443836a79
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208708742 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.4208708742
Directory /workspace/9.adc_ctrl_stress_all_with_rand_reset/latest
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