Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

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Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	7028	1			T5	4		T31	43		T39	65
testmodes[AdcCtrlTestmodeNormal]	5543	1			T2	1		T4	2		T5	8
testmodes[AdcCtrlTestmodeLowpower]	5872	1			T1	3		T3	14		T5	14
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	3789	1			T5	1		T31	9		T39	23
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1762	1			T5	3		T31	16		T39	17
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1371	1			T31	18		T39	24		T40	1
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1777	1			T5	2		T31	11		T39	14
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	2005	1			T4	1		T5	5		T6	1
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1411	1			T5	1		T31	16		T39	27
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1352	1			T31	23		T39	28		T41	13
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1432	1			T31	12		T39	23		T41	8
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2845	1			T1	2		T3	13		T5	13