Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27135

1

T1

31

T2

8

T3

14

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23053

1

T1

31

T2

8

T3

14

auto[ADC_CTRL_FILTER_COND_OUT]

4082

1

T4

1

T5

13

T8

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20811

1

T3

14

T4

2

T5

25

auto[1]

6324

1

T1

31

T2

8

T5

13

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22883

1

T1

31

T2

1

T3

14

auto[1]

4252

1

T2

7

T5

12

T7

19

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	14	1			T129	13		T228	1		-	-
values[0]	39	1			T4	1		T229	9		T230	7
values[1]	645	1			T8	3		T9	9		T65	12
values[2]	747	1			T6	1		T9	8		T65	12
values[3]	885	1			T40	34		T68	24		T32	23
values[4]	681	1			T4	1		T10	3		T40	1
values[5]	3140	1			T1	31		T2	8		T7	22
values[6]	646	1			T31	3		T43	7		T66	10
values[7]	662	1			T6	1		T10	9		T68	25
values[8]	850	1			T31	1		T66	7		T204	10
values[9]	1309	1			T5	13		T9	3		T65	4
minimum	17517	1			T3	14		T5	25		T31	142

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	912	1			T4	1		T8	3		T9	9
values[1]	751	1			T6	1		T9	8		T65	12
values[2]	673	1			T40	35		T63	10		T161	1
values[3]	3195	1			T1	31		T2	8		T4	1
values[4]	786	1			T231	1		T183	1		T165	5
values[5]	637	1			T6	1		T31	3		T43	7
values[6]	656	1			T10	9		T31	1		T68	25
values[7]	896	1			T66	7		T157	21		T204	10
values[8]	1004	1			T9	3		T40	24		T67	28
values[9]	108	1			T5	13		T65	4		T173	1
minimum	17517	1			T3	14		T5	25		T31	142

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22695

1

T1

3

T2

8

T3

14

auto[1]

4440

1

T1

28

T65

25

T40

24

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T4	1		T8	1		T9	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	339	1			T65	12		T66	18		T33	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T6	1		T9	1		T40	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T65	12		T161	1		T232	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T161	1		T173	1		T233	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T40	15		T63	10		T34	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1654	1			T1	31		T2	1		T7	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T4	1		T8	1		T67	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T231	1		T183	1		T165	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T166	1		T48	5		T207	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T6	1		T196	8		T52	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T31	1		T43	1		T66	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T10	1		T68	12		T166	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T31	1		T171	1		T174	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T163	6		T234	1		T130	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T66	7		T157	1		T204	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T9	1		T40	12		T68	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T67	15		T183	1		T64	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T235	13		T236	9		T237	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T5	1		T65	4		T173	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17382	1			T3	14		T5	25		T31	141
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T8	2		T9	8		T157	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T33	8		T129	3		T238	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T9	7		T40	4		T68	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T232	9		T239	15		T54	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T232	7		T194	1		T240	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T40	20		T34	2		T162	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	960	1			T2	7		T7	19		T10	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T67	9		T32	11		T46	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T47	1		T174	11		T239	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T166	5		T48	1		T207	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T52	1		T53	1		T239	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T31	2		T43	6		T162	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T10	8		T68	13		T166	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T171	16		T174	2		T207	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T163	7		T234	2		T130	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T157	20		T165	8		T34	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T9	2		T40	12		T68	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T67	13		T163	26		T129	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T235	11		T236	10		T237	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T5	12		T208	11		T241	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T31	1		T32	2		T46	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T129	11		T228	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T4	1		T229	1		T242	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T230	3		T243	10		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T8	1		T9	1		T157	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T65	12		T66	18		T210	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T6	1		T9	1		T40	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	318	1			T65	12		T33	11		T186	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T68	13		T197	5		T233	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T40	14		T32	12		T63	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T10	1		T173	1		T211	19
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T4	1		T40	1		T46	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1706	1			T1	31		T2	1		T7	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T8	1		T67	1		T173	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T183	1		T166	1		T174	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T31	1		T43	1		T66	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T6	1		T10	1		T68	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T34	11		T168	11		T171	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T163	6		T234	1		T244	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T31	1		T66	7		T204	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	345	1			T9	1		T40	12		T68	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	300	1			T5	1		T65	4		T67	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17382	1			T3	14		T5	25		T31	141
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T129	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T229	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T230	4		T243	10		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T8	2		T9	8		T157	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T129	3		T245	12		T175	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T9	7		T40	4		T246	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T33	8		T239	15		T55	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T68	11		T197	13		T232	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T40	20		T32	11		T34	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T10	2		T35	1		T247	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T46	4		T162	1		T248	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	979	1			T2	7		T7	19		T37	20
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T67	9		T166	5		T162	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T166	9		T174	11		T49	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T31	2		T43	6		T197	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T10	8		T68	13		T246	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T34	12		T168	13		T171	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T163	7		T234	2		T130	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T249	12		T175	3		T250	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	313	1			T9	2		T40	12		T68	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	351	1			T5	12		T67	13		T157	20
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T31	1		T32	2		T46	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T4	1		T8	3		T9	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T65	1		T66	1		T33	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T6	1		T9	8		T40	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T65	1		T161	1		T232	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T161	1		T173	1		T233	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T40	22		T63	1		T34	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1290	1			T1	3		T2	8		T7	22
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	346	1			T4	1		T8	1		T67	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T231	1		T183	1		T165	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T166	6		T48	5		T207	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T6	1		T196	1		T52	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T31	3		T43	7		T66	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T10	9		T68	14		T166	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T31	1		T171	17		T174	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	318	1			T163	8		T234	3		T130	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T66	1		T157	21		T204	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T9	3		T40	13		T68	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T67	14		T183	1		T64	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T235	12		T236	11		T237	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T5	13		T65	1		T173	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17517	1			T3	14		T5	25		T31	142
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T157	1		T204	10		T177	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	300	1			T65	11		T66	17		T33	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T68	12		T246	13		T197	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T65	11		T232	12		T54	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T233	11		T232	1		T251	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T40	13		T63	9		T34	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1324	1			T1	28		T58	19		T62	19
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T32	11		T46	3		T34	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T165	4		T47	1		T174	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T48	1		T207	10		T54	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T196	7		T52	1		T53	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T66	9		T162	11		T168	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T68	11		T246	12		T49	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T174	1		T207	7		T232	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T163	5		T130	11		T194	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T66	6		T204	9		T165	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T40	11		T68	12		T177	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T67	14		T163	23		T129	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T235	12		T236	8		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T65	3		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T129	3		T228	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T4	1		T229	9		T242	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T230	5		T243	11		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T8	3		T9	9		T157	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T65	1		T66	1		T210	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T6	1		T9	8		T40	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T65	1		T33	9		T186	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T68	12		T197	14		T233	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T40	21		T32	12		T63	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T10	3		T173	1		T211	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T4	1		T40	1		T46	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1321	1			T1	3		T2	8		T7	22
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T8	1		T67	10		T173	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T183	1		T166	10		T174	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T31	3		T43	7		T66	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T6	1		T10	9		T68	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T34	13		T168	14		T171	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T163	8		T234	3		T244	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T31	1		T66	1		T204	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	386	1			T9	3		T40	13		T68	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	418	1			T5	13		T65	1		T67	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17517	1			T3	14		T5	25		T31	142
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T129	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T230	2		T243	9		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T157	1		T177	15		T252	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T65	11		T66	17		T210	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T204	10		T246	13		T170	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T65	11		T33	10		T55	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T68	12		T197	4		T233	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T40	13		T32	11		T63	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T211	18		T253	21		T254	21
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T46	3		T248	9		T255	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1364	1			T1	28		T58	19		T62	19
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T162	11		T47	9		T48	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T174	10		T49	1		T50	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T66	9		T53	1		T54	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T68	11		T246	12		T52	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T34	10		T168	10		T174	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T163	5		T130	11		T187	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T66	6		T204	9		T249	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T40	11		T68	12		T177	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T65	3		T67	14		T165	8

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22695

1

T1

3

T2

8

T3

14

auto[1]

auto[0]

4440

1

T1

28

T65

25

T40

24

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27135

1

T1

31

T2

8

T3

14

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23214

1

T1

31

T2

8

T3

14

auto[ADC_CTRL_FILTER_COND_OUT]

3921

1

T4

1

T6

1

T8

4

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20716

1

T3

14

T5

38

T6

1

auto[1]

6419

1

T1

31

T2

8

T4

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22883

1

T1

31

T2

1

T3

14

auto[1]

4252

1

T2

7

T5

12

T7

19

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	24	1			T198	14		T256	10		-	-
values[0]	120	1			T40	24		T232	9		T257	1
values[1]	672	1			T6	1		T8	1		T31	1
values[2]	515	1			T10	3		T40	34		T161	1
values[3]	877	1			T9	11		T10	9		T65	12
values[4]	3090	1			T1	31		T2	8		T7	22
values[5]	730	1			T65	12		T31	3		T157	5
values[6]	886	1			T8	3		T65	4		T40	1
values[7]	723	1			T4	2		T231	2		T34	29
values[8]	749	1			T6	1		T9	9		T66	18
values[9]	1232	1			T5	13		T66	7		T67	28
minimum	17517	1			T3	14		T5	25		T31	142

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	942	1			T6	1		T8	1		T31	1
values[1]	583	1			T9	8		T10	12		T40	34
values[2]	844	1			T9	3		T65	12		T43	7
values[3]	3164	1			T1	31		T2	8		T7	22
values[4]	748	1			T65	4		T183	1		T204	14
values[5]	839	1			T4	1		T8	3		T40	1
values[6]	646	1			T4	1		T231	2		T173	1
values[7]	706	1			T6	1		T9	9		T66	18
values[8]	801	1			T66	7		T157	21		T33	1
values[9]	345	1			T5	13		T63	10		T64	1
minimum	17517	1			T3	14		T5	25		T31	142

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22695

1

T1

3

T2

8

T3

14

auto[1]

4440

1

T1

28

T65

25

T40

24

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	320	1			T6	1		T31	1		T40	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T8	1		T46	8		T197	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T9	1		T40	14		T166	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T10	2		T161	1		T163	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T65	12		T66	10		T183	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T9	1		T43	1		T67	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1725	1			T1	31		T2	1		T7	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T64	1		T157	2		T49	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T65	4		T204	3		T47	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T183	1		T204	11		T173	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T4	1		T33	11		T165	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T8	1		T40	1		T34	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T231	1		T244	1		T258	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T4	1		T231	1		T173	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T32	12		T166	1		T210	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T6	1		T9	1		T66	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T66	7		T157	1		T33	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T174	11		T169	1		T170	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T5	1		T64	1		T161	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T63	10		T163	16		T174	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17382	1			T3	14		T5	25		T31	141
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T40	16		T68	17		T168	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T46	4		T197	13		T130	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T9	7		T40	20		T166	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T10	10		T163	9		T130	28
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T234	2		T197	4		T53	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T9	2		T43	6		T67	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1025	1			T2	7		T7	19		T31	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T157	3		T49	1		T207	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T47	10		T187	12		T35	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T259	9		T260	9		T261	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T33	8		T34	12		T174	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T8	2		T34	2		T166	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T258	6		T262	14		T263	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T194	11		T239	9		T262	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T32	11		T50	5		T229	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T9	8		T67	13		T34	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T157	20		T47	1		T246	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T174	11		T264	8		T263	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T5	12		T207	2		T265	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T163	17		T174	10		T188	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T31	1		T32	2		T46	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T198	14		T256	10		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T40	12		T257	1		T135	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T232	2		T18	2		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T6	1		T31	1		T40	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T8	1		T46	8		T197	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T40	14		T163	6		T48	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T10	1		T161	1		T266	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T9	1		T65	12		T66	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	323	1			T9	1		T10	1		T43	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1686	1			T1	31		T2	1		T7	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T64	1		T173	1		T248	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T65	12		T31	1		T165	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T157	2		T204	11		T244	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T65	4		T33	11		T165	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T8	1		T40	1		T183	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T4	1		T231	1		T173	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T4	1		T231	1		T34	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T32	12		T210	12		T50	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T6	1		T9	1		T66	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	308	1			T5	1		T66	7		T64	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	391	1			T67	15		T63	10		T163	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17382	1			T3	14		T5	25		T31	141
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T40	12		T135	4		T267	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T232	7		T18	1		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T40	4		T68	17		T168	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T46	4		T197	13		T130	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T40	20		T163	7		T48	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T10	2		T236	10		T119	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T9	7		T166	5		T197	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T9	2		T10	8		T43	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1001	1			T2	7		T7	19		T37	20
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T194	8		T239	15		T54	19
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T31	2		T165	8		T47	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T157	3		T49	1		T207	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T33	8		T34	12		T174	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T8	2		T34	2		T268	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T263	14		T250	1		T269	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T34	16		T166	9		T162	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T32	11		T50	5		T270	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T9	8		T162	13		T255	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T5	12		T157	20		T47	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T67	13		T163	17		T174	21
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T31	1		T32	2		T46	1