Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27135

1

T1

31

T2

8

T3

14

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23388

1

T1

31

T2

8

T3

14

auto[ADC_CTRL_FILTER_COND_OUT]

3747

1

T4

1

T5

13

T6

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20841

1

T3

14

T4

1

T5

25

auto[1]

6294

1

T1

31

T2

8

T4

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22883

1

T1

31

T2

1

T3

14

auto[1]

4252

1

T2

7

T5

12

T7

19

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	9	1			T31	1		T330	1		T179	7
values[0]	73	1			T207	22		T240	16		T324	3
values[1]	724	1			T4	1		T6	1		T10	3
values[2]	800	1			T5	13		T8	1		T9	3
values[3]	927	1			T6	1		T40	34		T66	18
values[4]	485	1			T231	1		T64	1		T33	19
values[5]	753	1			T10	9		T65	12		T66	10
values[6]	609	1			T9	9		T65	4		T183	1
values[7]	569	1			T4	1		T162	2		T163	18
values[8]	3312	1			T1	31		T2	8		T7	22
values[9]	1357	1			T8	3		T65	12		T40	25
minimum	17517	1			T3	14		T5	25		T31	142

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	848	1			T4	1		T6	1		T9	3
values[1]	933	1			T5	13		T8	1		T40	39
values[2]	730	1			T6	1		T66	18		T68	19
values[3]	630	1			T231	1		T64	1		T33	19
values[4]	749	1			T10	9		T65	16		T66	10
values[5]	672	1			T9	9		T183	1		T161	1
values[6]	2984	1			T1	31		T2	8		T4	1
values[7]	891	1			T9	8		T32	23		T63	10
values[8]	949	1			T65	12		T40	25		T43	7
values[9]	188	1			T8	3		T31	1		T68	25
minimum	17561	1			T3	14		T5	25		T31	142

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22695

1

T1

3

T2

8

T3

14

auto[1]

4440

1

T1

28

T65

25

T40

24

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T9	1		T162	12		T207	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T4	1		T6	1		T10	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T40	15		T204	3		T166	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	351	1			T5	1		T8	1		T68	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T64	1		T161	1		T210	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T6	1		T66	18		T68	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T231	1		T64	1		T33	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T204	10		T129	5		T331	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T10	1		T65	16		T47	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T66	10		T173	1		T163	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T9	1		T292	1		T244	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T183	1		T161	1		T34	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1716	1			T1	31		T2	1		T4	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T66	7		T67	1		T33	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T9	1		T63	10		T157	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T32	12		T246	14		T235	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T40	1		T231	1		T67	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T65	12		T40	12		T43	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T8	1		T31	1		T68	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T332	1		T322	1		T289	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17386	1			T3	14		T5	25		T31	141
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T164	11		T265	1		T247	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T9	2		T162	13		T207	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T10	2		T31	2		T165	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T40	24		T166	5		T171	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T5	12		T68	11		T163	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T54	19		T263	14		T250	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T68	6		T197	13		T130	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T33	8		T248	10		T194	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T129	3		T262	14		T333	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T10	8		T47	10		T197	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T163	7		T174	2		T280	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T9	8		T49	1		T53	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T34	2		T162	1		T255	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1020	1			T2	7		T7	19		T37	20
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T67	9		T187	12		T259	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T9	7		T157	3		T246	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T32	11		T246	15		T235	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T67	13		T34	16		T258	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T40	12		T43	6		T157	20
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T8	2		T68	13		T168	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T289	5		T200	5		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T31	1		T32	2		T46	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T265	10		T247	12		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T31	1		T330	1		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T179	7		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T207	11		T324	1		T277	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T240	1		T290	2		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T162	12		T233	14		T196	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T4	1		T6	1		T10	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T9	1		T40	1		T166	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T5	1		T8	1		T68	26
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T40	14		T64	1		T204	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T6	1		T66	18		T161	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T231	1		T64	1		T33	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T174	2		T129	5		T196	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T10	1		T65	12		T166	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T66	10		T204	10		T163	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T9	1		T65	4		T292	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T183	1		T33	1		T161	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T4	1		T163	9		T232	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T162	1		T211	19		T265	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1840	1			T1	31		T2	1		T7	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T43	1		T66	7		T67	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T8	1		T40	1		T231	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	409	1			T65	12		T40	12		T157	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17382	1			T3	14		T5	25		T31	141
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T207	11		T324	2		T277	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T240	15		T290	5		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T162	13		T51	2		T262	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T10	2		T31	2		T165	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T9	2		T40	4		T166	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T5	12		T68	17		T163	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T40	20		T248	10		T53	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T197	13		T130	9		T52	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T33	8		T299	7		T334	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T174	2		T129	3		T262	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T10	8		T47	10		T194	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T163	7		T261	11		T271	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T9	8		T197	4		T49	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T34	2		T255	5		T47	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T163	9		T232	7		T187	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T162	1		T265	7		T239	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1131	1			T2	7		T7	19		T9	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T43	6		T67	9		T32	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T8	2		T67	13		T68	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	390	1			T40	12		T157	20		T234	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T31	1		T32	2		T46	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T9	3		T162	14		T207	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T4	1		T6	1		T10	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T40	26		T204	1		T166	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T5	13		T8	1		T68	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T64	1		T161	1		T210	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T6	1		T66	1		T68	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T231	1		T64	1		T33	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T204	1		T129	4		T331	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T10	9		T65	2		T47	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T66	1		T173	1		T163	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T9	9		T292	1		T244	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T183	1		T161	1		T34	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1368	1			T1	3		T2	8		T4	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T66	1		T67	10		T33	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T9	8		T63	1		T157	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T32	12		T246	16		T235	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T40	1		T231	1		T67	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	336	1			T65	1		T40	13		T43	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T8	3		T31	1		T68	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T332	1		T322	1		T289	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17523	1			T3	14		T5	25		T31	142
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T164	1		T265	11		T247	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T162	11		T207	10		T233	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T165	8		T50	9		T232	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T40	13		T204	2		T177	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	301	1			T68	12		T163	15		T253	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T210	11		T170	7		T54	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T66	17		T68	12		T197	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T33	10		T165	4		T248	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T204	9		T129	4		T228	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T65	14		T47	9		T270	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T66	9		T163	5		T174	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T49	1		T53	1		T302	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T34	16		T255	5		T47	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1368	1			T1	28		T46	3		T58	19
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T66	6		T252	28		T187	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T63	9		T157	1		T246	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T32	11		T246	13		T235	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T67	14		T34	12		T258	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T65	11		T40	11		T204	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T68	11		T168	10		T174	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T289	8		T179	6		T301	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T335	3		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T164	10		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T31	1		T330	1		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T179	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T207	12		T324	3		T277	17
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T240	16		T290	6		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T162	14		T233	1		T196	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T4	1		T6	1		T10	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T9	3		T40	5		T166	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T5	13		T8	1		T68	19
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T40	21		T64	1		T204	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T6	1		T66	1		T161	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T231	1		T64	1		T33	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T174	3		T129	4		T196	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T10	9		T65	1		T166	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T66	1		T204	1		T163	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T9	9		T65	1		T292	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T183	1		T33	1		T161	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T4	1		T163	10		T232	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T162	2		T211	1		T265	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1489	1			T1	3		T2	8		T7	22
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T43	7		T66	1		T67	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	331	1			T8	3		T40	1		T231	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	452	1			T65	1		T40	13		T157	21
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17517	1			T3	14		T5	25		T31	142
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T179	6		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T207	10		T277	8		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T290	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T162	11		T233	13		T196	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T165	8		T164	10		T50	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T177	15		T170	7		T336	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T68	24		T163	15		T232	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T40	13		T204	2		T248	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T66	17		T197	4		T130	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T33	10		T165	4		T210	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T174	1		T129	4		T196	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T65	11		T47	9		T55	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T66	9		T204	9		T163	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T65	3		T49	1		T53	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T34	16		T255	5		T47	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T163	8		T232	1		T187	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T211	18		T215	1		T337	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1482	1			T1	28		T46	3		T58	19
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T66	6		T32	11		T246	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T67	14		T68	11		T157	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	347	1			T65	11		T40	11		T204	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22695

1

T1

3

T2

8

T3

14

auto[1]

auto[0]

4440

1

T1

28

T65

25

T40

24