Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27135

1

T1

31

T2

8

T3

14

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23280

1

T1

31

T2

8

T3

14

auto[ADC_CTRL_FILTER_COND_OUT]

3855

1

T4

1

T6

2

T9

3

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20542

1

T3

14

T4

2

T5

25

auto[1]

6593

1

T1

31

T2

8

T5

13

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22883

1

T1

31

T2

1

T3

14

auto[1]

4252

1

T2

7

T5

12

T7

19

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	255	1			T10	9		T63	10		T157	21
values[0]	23	1			T228	1		T275	4		T294	3
values[1]	921	1			T9	8		T31	1		T231	1
values[2]	834	1			T4	1		T9	9		T46	12
values[3]	549	1			T4	1		T6	1		T65	16
values[4]	610	1			T5	13		T8	3		T231	1
values[5]	3140	1			T1	31		T2	8		T6	1
values[6]	767	1			T9	3		T31	3		T40	24
values[7]	648	1			T43	7		T157	5		T34	29
values[8]	680	1			T10	3		T64	1		T204	10
values[9]	1191	1			T8	1		T65	12		T40	39
minimum	17517	1			T3	14		T5	25		T31	142

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	885	1			T9	9		T31	1		T231	1
values[1]	731	1			T4	1		T6	1		T46	12
values[2]	547	1			T4	1		T5	13		T65	16
values[3]	2995	1			T1	31		T2	8		T7	22
values[4]	777	1			T6	1		T31	3		T66	10
values[5]	725	1			T9	3		T40	24		T43	7
values[6]	689	1			T10	3		T157	5		T34	29
values[7]	642	1			T66	18		T32	23		T64	1
values[8]	1155	1			T10	9		T65	12		T40	39
values[9]	160	1			T8	1		T196	8		T338	7
minimum	17829	1			T3	14		T5	25		T9	8

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22695

1

T1

3

T2

8

T3

14

auto[1]

4440

1

T1

28

T65

25

T40

24

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T9	1		T31	1		T231	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T166	1		T174	11		T210	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T46	8		T161	1		T204	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T4	1		T6	1		T248	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T4	1		T5	1		T65	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T65	12		T183	1		T173	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1692	1			T1	31		T2	1		T7	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T67	15		T248	1		T177	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T66	10		T211	19		T186	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T6	1		T31	1		T67	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T68	13		T197	1		T129	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T9	1		T40	12		T43	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T34	13		T177	4		T244	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T10	1		T157	2		T292	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T32	12		T268	1		T246	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T66	18		T64	1		T204	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T10	1		T65	12		T40	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	383	1			T40	14		T66	7		T63	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T8	1		T178	6		T296	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T196	8		T338	7		T282	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17455	1			T3	14		T5	25		T9	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T165	9		T255	6		T163	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T9	8		T34	2		T194	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T166	9		T174	11		T270	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T46	4		T171	16		T48	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T248	10		T47	10		T187	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T5	12		T166	5		T246	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T129	2		T280	10		T295	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1036	1			T2	7		T7	19		T8	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T67	13		T163	9		T207	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T172	17		T278	12		T288	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T31	2		T67	9		T33	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T68	11		T197	4		T129	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T9	2		T40	12		T43	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T34	16		T130	9		T265	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T10	2		T157	3		T163	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T32	11		T268	11		T246	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T194	8		T54	6		T229	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T10	8		T40	4		T68	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	296	1			T40	20		T157	20		T34	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T178	7		T296	2		T339	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T282	14		T119	13		T15	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T9	7		T31	1		T32	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T165	8		T255	5		T163	17

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T10	1		T173	1		T298	5
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T63	10		T157	1		T130	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T228	1		T275	4		T237	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T294	1		T297	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	303	1			T9	1		T31	1		T231	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T165	9		T255	6		T163	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T9	1		T46	8		T161	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T4	1		T166	1		T248	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T4	1		T65	4		T246	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T6	1		T65	12		T183	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T5	1		T8	1		T231	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T67	16		T248	1		T163	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1713	1			T1	31		T2	1		T7	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T6	1		T33	11		T161	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T68	13		T197	1		T129	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T9	1		T31	1		T40	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T34	13		T177	4		T244	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T43	1		T157	2		T292	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T268	1		T246	13		T258	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T10	1		T64	1		T204	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T8	1		T65	12		T40	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	382	1			T40	14		T66	25		T33	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17382	1			T3	14		T5	25		T31	141
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T10	8		T298	4		T263	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T157	20		T130	9		T282	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T237	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T294	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T9	7		T34	2		T162	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T165	8		T255	5		T163	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T9	8		T46	4		T171	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T166	9		T248	10		T47	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T246	15		T232	7		T236	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T259	9		T55	2		T280	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T5	12		T8	2		T166	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T67	22		T163	9		T129	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1022	1			T2	7		T7	19		T37	20
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T33	8		T130	19		T207	26
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T68	11		T197	4		T129	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T9	2		T31	2		T40	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T34	16		T35	1		T299	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T43	6		T157	3		T163	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T268	11		T246	9		T258	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T10	2		T54	6		T229	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T40	4		T68	13		T32	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	301	1			T40	20		T34	12		T168	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T31	1		T32	2		T46	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T9	9		T31	1		T231	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T166	10		T174	12		T210	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T46	9		T161	1		T204	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T4	1		T6	1		T248	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T4	1		T5	13		T65	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T65	1		T183	1		T173	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1384	1			T1	3		T2	8		T7	22
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T67	14		T248	1		T177	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T66	1		T211	1		T186	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T6	1		T31	3		T67	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T68	12		T197	5		T129	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T9	3		T40	13		T43	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T34	17		T177	1		T244	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T10	3		T157	4		T292	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T32	12		T268	12		T246	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T66	1		T64	1		T204	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	291	1			T10	9		T65	1		T40	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	354	1			T40	21		T66	1		T63	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T8	1		T178	8		T296	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T196	1		T338	1		T282	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17615	1			T3	14		T5	25		T9	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T165	9		T255	6		T163	18
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T34	16		T194	3		T299	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T174	10		T210	11		T270	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T46	3		T204	10		T48	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T248	9		T47	9		T187	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T65	3		T246	13		T232	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T65	11		T129	10		T252	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1344	1			T1	28		T68	12		T58	19
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T67	14		T177	15		T163	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T66	9		T211	18		T172	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T33	10		T165	4		T174	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T68	12		T129	4		T53	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T40	11		T197	4		T187	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T34	12		T177	3		T130	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T157	1		T163	5		T174	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T32	11		T246	12		T258	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T66	17		T204	9		T194	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T65	11		T68	11		T47	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	325	1			T40	13		T66	6		T63	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T178	5		T296	4		T339	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T196	7		T338	6		T282	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T162	11		T271	1		T337	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T165	8		T255	5		T163	15

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T10	9		T173	1		T298	5
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T63	1		T157	21		T130	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T228	1		T275	4		T237	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T294	3		T297	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T9	8		T31	1		T231	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T165	9		T255	6		T163	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T9	9		T46	9		T161	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T4	1		T166	10		T248	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T4	1		T65	1		T246	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T6	1		T65	1		T183	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T5	13		T8	3		T231	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T67	24		T248	1		T163	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1366	1			T1	3		T2	8		T7	22
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T6	1		T33	9		T161	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T68	12		T197	5		T129	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T9	3		T31	3		T40	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T34	17		T177	1		T244	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T43	7		T157	4		T292	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T268	12		T246	10		T258	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T10	3		T64	1		T204	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	307	1			T8	1		T65	1		T40	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	358	1			T40	21		T66	2		T33	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17517	1			T3	14		T5	25		T31	142
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T298	4		T291	2		T296	4
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T63	9		T130	11		T336	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T34	16		T162	11		T194	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T165	8		T255	5		T163	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T46	3		T204	10		T48	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T248	9		T47	9		T187	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T65	3		T246	13		T232	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T65	11		T252	18		T253	21
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T204	2		T49	1		T50	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T67	14		T163	8		T129	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1369	1			T1	28		T66	9		T68	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T33	10		T165	4		T177	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T68	12		T129	4		T53	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T40	11		T174	1		T197	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T34	12		T177	3		T233	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T157	1		T163	5		T174	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T246	12		T258	6		T130	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T204	9		T196	9		T54	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T65	11		T68	11		T32	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	325	1			T40	13		T66	23		T34	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22695

1

T1

3

T2

8

T3

14

auto[1]

auto[0]

4440

1

T1

28

T65

25

T40

24