Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27135

1

T1

31

T2

8

T3

14

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23407

1

T1

31

T2

8

T3

14

auto[ADC_CTRL_FILTER_COND_OUT]

3728

1

T4

1

T5

13

T6

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20930

1

T3

14

T4

2

T5

38

auto[1]

6205

1

T1

31

T2

8

T6

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22883

1

T1

31

T2

1

T3

14

auto[1]

4252

1

T2

7

T5

12

T7

19

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	274	1			T246	22		T194	2		T172	35
values[0]	66	1			T207	29		T186	1		T170	15
values[1]	571	1			T6	1		T65	16		T68	25
values[2]	542	1			T8	3		T65	12		T68	24
values[3]	812	1			T4	1		T10	3		T33	1
values[4]	757	1			T9	8		T40	6		T66	18
values[5]	809	1			T4	1		T10	9		T31	1
values[6]	892	1			T40	24		T66	10		T231	1
values[7]	864	1			T5	13		T8	1		T40	34
values[8]	643	1			T31	3		T63	10		T157	21
values[9]	3388	1			T1	31		T2	8		T6	1
minimum	17517	1			T3	14		T5	25		T31	142

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	489	1			T65	16		T33	19		T161	1
values[1]	731	1			T8	3		T65	12		T68	24
values[2]	649	1			T4	1		T10	3		T40	5
values[3]	871	1			T9	8		T40	1		T67	38
values[4]	734	1			T4	1		T10	9		T31	1
values[5]	915	1			T8	1		T40	58		T43	7
values[6]	3170	1			T1	31		T2	8		T5	13
values[7]	570	1			T6	1		T63	10		T157	21
values[8]	1068	1			T9	12		T66	7		T46	12
values[9]	142	1			T262	13		T340	1		T341	1
minimum	17796	1			T3	14		T5	25		T6	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22695

1

T1

3

T2

8

T3

14

auto[1]

4440

1

T1

28

T65

25

T40

24

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T65	4		T33	11		T161	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T65	12		T34	17		T49	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T8	1		T65	12		T68	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T33	1		T166	1		T174	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T10	1		T40	1		T66	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T4	1		T183	1		T163	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T9	1		T40	1		T67	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T157	2		T204	11		T129	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T4	1		T31	1		T246	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T10	1		T173	1		T292	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T8	1		T40	12		T43	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T40	14		T68	13		T239	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1677	1			T1	31		T2	1		T7	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T5	1		T231	1		T34	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T157	1		T173	1		T248	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T6	1		T63	10		T163	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	285	1			T9	2		T66	7		T46	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	312	1			T204	10		T255	6		T47	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T340	1		T341	1		T298	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T262	1		T298	2		T135	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17436	1			T3	14		T5	25		T31	141
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T6	1		T68	12		T207	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T33	8		T51	2		T265	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T34	2		T49	1		T207	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T8	2		T68	11		T130	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T166	5		T174	2		T197	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T10	2		T40	4		T162	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T163	17		T48	1		T187	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T9	7		T67	22		T165	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T157	3		T129	3		T247	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T246	15		T249	12		T285	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T10	8		T171	16		T174	21
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T40	12		T43	6		T162	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T40	20		T68	6		T239	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	986	1			T2	7		T7	19		T31	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T5	12		T34	12		T47	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T157	20		T248	10		T262	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T163	9		T234	2		T197	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T9	10		T46	4		T34	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T255	5		T47	10		T246	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T298	2		T342	6		T343	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T262	12		T298	1		T135	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T31	1		T32	2		T46	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T68	13		T207	15		T259	9

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T172	18		T340	1		T266	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T246	13		T194	1		T298	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T344	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T207	14		T186	1		T170	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T65	4		T33	11		T166	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T6	1		T65	12		T68	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T8	1		T65	12		T68	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T183	1		T166	1		T174	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T10	1		T162	1		T252	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T4	1		T33	1		T187	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T9	1		T40	2		T66	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T157	2		T204	11		T163	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T4	1		T31	1		T67	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T10	1		T173	1		T292	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T40	12		T66	10		T231	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T211	19		T239	1		T54	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T8	1		T43	1		T32	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	296	1			T5	1		T40	14		T231	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T31	1		T157	1		T173	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T63	10		T34	11		T248	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1788	1			T1	31		T2	1		T7	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T6	1		T204	10		T255	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17382	1			T3	14		T5	25		T31	141
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T172	17		T298	2		T240	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T246	9		T194	1		T298	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T207	15		T312	2		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T33	8		T232	7		T51	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T68	13		T34	2		T49	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T8	2		T68	11		T130	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T166	5		T174	2		T197	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T10	2		T162	1		T259	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T187	12		T53	1		T239	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T9	7		T40	4		T67	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T157	3		T163	17		T48	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T67	9		T246	15		T249	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T10	8		T171	16		T174	21
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T40	12		T162	13		T168	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T239	9		T54	6		T278	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T43	6		T32	11		T248	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T5	12		T40	20		T68	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T31	2		T157	20		T262	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T34	12		T163	9		T234	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1066	1			T2	7		T7	19		T9	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T255	5		T47	10		T163	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T31	1		T32	2		T46	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T65	1		T33	9		T161	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T65	1		T34	3		T49	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T8	3		T65	1		T68	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T33	1		T166	6		T174	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T10	3		T40	5		T66	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T4	1		T183	1		T163	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T9	8		T40	1		T67	24
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T157	4		T204	1		T129	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T4	1		T31	1		T246	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T10	9		T173	1		T292	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T8	1		T40	13		T43	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T40	21		T68	7		T239	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1317	1			T1	3		T2	8		T7	22
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T5	13		T231	1		T34	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T157	21		T173	1		T248	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T6	1		T63	1		T163	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T9	12		T66	1		T46	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	307	1			T204	1		T255	6		T47	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T340	1		T341	1		T298	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T262	13		T298	2		T135	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17561	1			T3	14		T5	25		T31	142
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T6	1		T68	14		T207	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T65	3		T33	10		T51	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T65	11		T34	16		T49	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T65	11		T68	12		T130	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T174	1		T197	4		T187	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T66	17		T252	10		T233	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T163	15		T48	1		T187	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T67	14		T204	2		T165	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T157	1		T204	10		T129	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T246	13		T249	11		T336	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T174	22		T211	18		T207	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T40	11		T66	9		T162	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T40	13		T68	12		T54	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1346	1			T1	28		T32	11		T58	19
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T34	10		T47	1		T130	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T248	9		T164	10		T285	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T63	9		T163	8		T299	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T66	6		T46	3		T165	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T204	9		T255	5		T47	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T298	4		T303	9		T343	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T298	1		T135	8		T321	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T177	15		T252	18		T232	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T68	11		T207	13		T170	14

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T172	18		T340	1		T266	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T246	10		T194	2		T298	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T344	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T207	16		T186	1		T170	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T65	1		T33	9		T166	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T6	1		T65	1		T68	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T8	3		T65	1		T68	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T183	1		T166	6		T174	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T10	3		T162	2		T252	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T4	1		T33	1		T187	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T9	8		T40	6		T66	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T157	4		T204	1		T163	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T4	1		T31	1		T67	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T10	9		T173	1		T292	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T40	13		T66	1		T231	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T211	1		T239	10		T54	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T8	1		T43	7		T32	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T5	13		T40	21		T231	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T31	3		T157	21		T173	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T63	1		T34	13		T248	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1427	1			T1	3		T2	8		T7	22
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	310	1			T6	1		T204	1		T255	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17517	1			T3	14		T5	25		T31	142
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T172	17		T298	4		T240	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T246	12		T298	1		T271	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T207	13		T170	14		T345	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T65	3		T33	10		T177	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T65	11		T68	11		T34	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T65	11		T68	12		T130	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T174	1		T197	4		T187	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T252	10		T233	13		T196	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T187	10		T53	1		T288	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T66	17		T67	14		T204	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T157	1		T204	10		T163	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T246	13		T249	11		T270	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T174	22		T207	10		T310	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T40	11		T66	9		T162	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T211	18		T54	5		T283	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T32	11		T248	9		T177	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T40	13		T68	12		T47	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T285	4		T282	14		T288	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T63	9		T34	10		T163	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1427	1			T1	28		T66	6		T46	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T204	9		T255	5		T47	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22695

1

T1

3

T2

8

T3

14

auto[1]

auto[0]

4440

1

T1

28

T65

25

T40

24