Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27135

1

T1

31

T2

8

T3

14

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23361

1

T1

31

T2

8

T3

14

auto[ADC_CTRL_FILTER_COND_OUT]

3774

1

T4

1

T5

13

T6

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20770

1

T3

14

T4

1

T5

25

auto[1]

6365

1

T1

31

T2

8

T4

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22883

1

T1

31

T2

1

T3

14

auto[1]

4252

1

T2

7

T5

12

T7

19

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	268	1			T31	1		T204	11		T173	1
values[0]	34	1			T240	16		T346	11		T290	7
values[1]	784	1			T4	1		T6	1		T10	3
values[2]	795	1			T5	13		T8	1		T9	3
values[3]	854	1			T6	1		T40	34		T66	18
values[4]	529	1			T231	1		T64	1		T33	19
values[5]	771	1			T10	9		T65	12		T66	10
values[6]	614	1			T9	9		T65	4		T183	1
values[7]	583	1			T4	1		T66	7		T33	1
values[8]	3261	1			T1	31		T2	8		T7	22
values[9]	1125	1			T8	3		T65	12		T40	25
minimum	17517	1			T3	14		T5	25		T31	142

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	577	1			T4	1		T6	1		T9	3
values[1]	908	1			T5	13		T8	1		T40	39
values[2]	740	1			T6	1		T66	18		T68	19
values[3]	626	1			T231	1		T64	1		T33	19
values[4]	712	1			T10	9		T65	16		T66	10
values[5]	687	1			T9	9		T183	1		T161	1
values[6]	3027	1			T1	31		T2	8		T4	1
values[7]	890	1			T9	8		T43	7		T32	23
values[8]	1036	1			T8	3		T65	12		T40	25
values[9]	76	1			T31	1		T168	24		T340	1
minimum	17856	1			T3	14		T5	25		T31	142

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22695

1

T1

3

T2

8

T3

14

auto[1]

4440

1

T1

28

T65

25

T40

24

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T9	1		T162	12		T50	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T4	1		T6	1		T10	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T40	15		T204	3		T166	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	349	1			T5	1		T8	1		T68	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T161	1		T210	12		T186	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T6	1		T66	18		T68	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T231	1		T64	1		T33	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T204	10		T129	5		T331	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T10	1		T65	16		T47	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T66	10		T163	6		T174	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T9	1		T292	1		T244	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T183	1		T161	1		T34	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1722	1			T1	31		T2	1		T4	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T66	7		T67	1		T33	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T9	1		T63	10		T157	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T43	1		T32	12		T246	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T8	1		T40	1		T231	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	301	1			T65	12		T40	12		T157	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T31	1		T168	11		T340	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T322	1		T289	9		T179	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17457	1			T3	14		T5	25		T31	141
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T165	9		T166	1		T268	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T9	2		T162	13		T50	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T10	2		T31	2		T54	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T40	24		T166	5		T171	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T5	12		T68	11		T163	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T54	19		T263	14		T250	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T68	6		T197	13		T130	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T33	8		T248	10		T194	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T129	3		T262	14		T333	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T10	8		T47	10		T197	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T163	7		T174	2		T280	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T9	8		T49	1		T130	19
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T34	2		T162	1		T255	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1023	1			T2	7		T7	19		T37	20
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T67	9		T174	10		T187	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T9	7		T157	3		T246	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T43	6		T32	11		T246	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T8	2		T67	13		T68	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T40	12		T157	20		T234	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T168	13		T306	13		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T289	5		T347	6		T200	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T31	1		T32	2		T46	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T165	8		T166	9		T268	11

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T31	1		T168	11		T130	11
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T204	11		T173	1		T262	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T346	11		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T240	1		T290	2		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T162	12		T50	15		T207	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T4	1		T6	1		T10	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T9	1		T40	1		T204	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	319	1			T5	1		T8	1		T68	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T40	14		T248	1		T186	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T6	1		T66	18		T68	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T231	1		T64	1		T33	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T129	5		T196	10		T331	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T10	1		T65	12		T166	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T66	10		T204	10		T163	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T9	1		T65	4		T292	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T183	1		T161	1		T34	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T4	1		T163	9		T232	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T66	7		T33	1		T174	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1802	1			T1	31		T2	1		T7	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T43	1		T67	1		T32	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T8	1		T40	1		T231	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	324	1			T65	12		T40	12		T157	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17382	1			T3	14		T5	25		T31	141
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T168	13		T130	9		T194	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T262	12		T235	10		T271	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T240	15		T290	5		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T162	13		T50	5		T207	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T10	2		T31	2		T165	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T9	2		T40	4		T166	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T5	12		T68	11		T163	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T40	20		T53	1		T54	19
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T68	6		T197	13		T130	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T33	8		T248	10		T299	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T129	3		T262	14		T288	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T10	8		T47	10		T194	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T163	7		T174	2		T280	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T9	8		T197	4		T49	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T34	2		T162	1		T255	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T163	9		T232	7		T160	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T174	10		T265	7		T239	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1092	1			T2	7		T7	19		T9	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T43	6		T67	9		T32	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T8	2		T67	13		T68	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	306	1			T40	12		T157	20		T234	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T31	1		T32	2		T46	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T9	3		T162	14		T50	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T4	1		T6	1		T10	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T40	26		T204	1		T166	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T5	13		T8	1		T68	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T161	1		T210	1		T186	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T6	1		T66	1		T68	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T231	1		T64	1		T33	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T204	1		T129	4		T331	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T10	9		T65	2		T47	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T66	1		T163	8		T174	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T9	9		T292	1		T244	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T183	1		T161	1		T34	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1371	1			T1	3		T2	8		T4	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T66	1		T67	10		T33	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T9	8		T63	1		T157	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T43	7		T32	12		T246	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T8	3		T40	1		T231	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	333	1			T65	1		T40	13		T157	21
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T31	1		T168	14		T340	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T322	1		T289	6		T179	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17609	1			T3	14		T5	25		T31	142
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T165	9		T166	10		T268	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T162	11		T50	9		T207	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T54	5		T80	2		T325	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T40	13		T204	2		T53	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T68	12		T177	15		T163	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T210	11		T170	7		T54	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T66	17		T68	12		T197	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T33	10		T165	4		T248	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T204	9		T129	4		T228	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T65	14		T47	9		T270	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T66	9		T163	5		T174	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T49	1		T53	1		T302	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T34	16		T255	5		T47	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1374	1			T1	28		T46	3		T58	19
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T66	6		T174	12		T252	28
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T63	9		T157	1		T246	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T32	11		T246	13		T235	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T67	14		T68	11		T34	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T65	11		T40	11		T204	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T168	10		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T289	8		T179	6		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T233	13		T288	11		T109	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T165	8		T164	10		T194	7

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T31	1		T168	14		T130	10
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T204	1		T173	1		T262	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T346	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T240	16		T290	6		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T162	14		T50	11		T207	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T4	1		T6	1		T10	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T9	3		T40	5		T204	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T5	13		T8	1		T68	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T40	21		T248	1		T186	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T6	1		T66	1		T68	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T231	1		T64	1		T33	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T129	4		T196	1		T331	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T10	9		T65	1		T166	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T66	1		T204	1		T163	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T9	9		T65	1		T292	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T183	1		T161	1		T34	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T4	1		T163	10		T232	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T66	1		T33	1		T174	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1441	1			T1	3		T2	8		T7	22
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T43	7		T67	10		T32	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T8	3		T40	1		T231	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	355	1			T65	1		T40	13		T157	21
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17517	1			T3	14		T5	25		T31	142
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T168	10		T130	10		T194	3
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T204	10		T235	11		T271	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T346	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T290	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T162	11		T50	9		T207	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T165	8		T164	10		T194	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T204	2		T336	15		T298	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T68	12		T177	15		T163	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T40	13		T53	1		T170	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T66	17		T68	12		T197	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T33	10		T165	4		T248	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T129	4		T196	9		T288	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T65	11		T47	9		T270	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T66	9		T204	9		T163	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T65	3		T49	1		T53	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T34	16		T255	5		T47	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T163	8		T232	1		T271	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T66	6		T174	12		T215	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1453	1			T1	28		T46	3		T58	19
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T32	11		T246	13		T252	28
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T67	14		T68	11		T34	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T65	11		T40	11		T177	3

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22695

1

T1

3

T2

8

T3

14

auto[1]

auto[0]

4440

1

T1

28

T65

25

T40

24