Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27135

1

T1

31

T2

8

T3

14

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23335

1

T1

31

T2

8

T3

14

auto[ADC_CTRL_FILTER_COND_OUT]

3800

1

T8

4

T9

20

T10

12

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20973

1

T3

14

T4

1

T5

38

auto[1]

6162

1

T1

31

T2

8

T4

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22883

1

T1

31

T2

1

T3

14

auto[1]

4252

1

T2

7

T5

12

T7

19

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	411	1			T183	1		T165	22		T34	29
values[0]	37	1			T246	22		T175	15		-	-
values[1]	655	1			T8	1		T9	9		T67	10
values[2]	3079	1			T1	31		T2	8		T5	13
values[3]	781	1			T65	12		T66	10		T204	10
values[4]	701	1			T6	1		T65	4		T40	24
values[5]	596	1			T9	3		T31	1		T40	1
values[6]	695	1			T10	9		T231	1		T67	28
values[7]	918	1			T4	1		T6	1		T65	12
values[8]	748	1			T9	8		T31	3		T64	1
values[9]	997	1			T4	1		T8	3		T10	3
minimum	17517	1			T3	14		T5	25		T31	142

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	776	1			T5	13		T8	1		T9	9
values[1]	3093	1			T1	31		T2	8		T7	22
values[2]	779	1			T66	10		T32	23		T204	10
values[3]	667	1			T6	1		T65	4		T31	1
values[4]	574	1			T9	3		T10	9		T40	1
values[5]	780	1			T6	1		T67	28		T68	19
values[6]	810	1			T4	1		T65	12		T68	25
values[7]	886	1			T8	3		T9	8		T31	3
values[8]	1046	1			T4	1		T10	3		T43	7
values[9]	69	1			T183	1		T47	4		T234	3
minimum	17655	1			T3	14		T5	25		T31	142

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22695

1

T1

3

T2

8

T3

14

auto[1]

4440

1

T1

28

T65

25

T40

24

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T5	1		T67	1		T34	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T8	1		T9	1		T40	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1729	1			T1	31		T2	1		T7	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T66	18		T258	7		T48	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T66	10		T163	6		T129	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T32	12		T204	10		T173	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T6	1		T64	1		T157	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T65	4		T31	1		T40	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T231	1		T183	1		T166	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T9	1		T10	1		T40	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	299	1			T6	1		T67	15		T68	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T33	1		T34	17		T51	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T4	1		T64	1		T157	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T65	12		T68	12		T255	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T166	2		T197	5		T49	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T8	1		T9	1		T31	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T4	1		T43	1		T46	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T10	1		T231	1		T168	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T47	3		T234	1		T283	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T183	1		T279	1		T176	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17403	1			T3	14		T5	25		T31	141
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T68	13		T174	11		T210	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T5	12		T67	9		T34	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T9	8		T40	20		T248	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1027	1			T2	7		T7	19		T37	20
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T258	6		T48	1		T130	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T163	7		T129	3		T53	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T32	11		T207	11		T261	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T157	3		T232	7		T54	19
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T40	12		T130	9		T270	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T194	8		T280	1		T282	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T9	2		T10	8		T33	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T67	13		T68	6		T162	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T34	2		T51	2		T239	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T157	20		T162	1		T47	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T68	13		T255	5		T130	19
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T166	14		T197	13		T49	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T8	2		T9	7		T31	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T43	6		T46	4		T165	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T10	2		T168	13		T172	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T47	1		T234	2		T281	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T176	10		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T31	1		T32	2		T46	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T68	11		T174	11		T207	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T165	14		T34	13		T47	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T183	1		T168	11		T278	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T175	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T246	13		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T67	1		T292	1		T164	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T8	1		T9	1		T68	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1703	1			T1	31		T2	1		T5	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T40	14		T66	18		T204	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T65	12		T66	10		T233	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T204	10		T173	1		T211	19
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T6	1		T64	1		T157	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T65	4		T40	12		T66	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T166	1		T177	4		T194	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T9	1		T31	1		T40	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T231	1		T67	15		T183	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T10	1		T33	1		T34	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	290	1			T4	1		T6	1		T68	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T65	12		T68	12		T130	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T64	1		T166	1		T49	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T9	1		T31	1		T161	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T4	1		T43	1		T46	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T8	1		T10	1		T40	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17382	1			T3	14		T5	25		T31	141
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T165	8		T34	16		T47	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T168	13		T278	12		T238	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T175	14		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T246	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T67	9		T262	14		T55	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T9	8		T68	11		T248	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1057	1			T2	7		T5	12		T7	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T40	20		T258	6		T48	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T285	6		T295	15		T122	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T130	9		T207	26		T261	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T157	3		T163	7		T129	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T40	12		T32	11		T130	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T194	8		T54	19		T280	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T9	2		T33	8		T50	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T67	13		T162	13		T265	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T10	8		T34	2		T268	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T68	6		T157	20		T162	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T68	13		T130	19		T232	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T166	5		T49	1		T53	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T9	7		T31	2		T255	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T43	6		T46	4		T166	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T8	2		T10	2		T40	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T31	1		T32	2		T46	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T5	13		T67	10		T34	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T8	1		T9	9		T40	21
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1373	1			T1	3		T2	8		T7	22
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T66	1		T258	7		T48	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T66	1		T163	8		T129	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T32	12		T204	1		T173	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T6	1		T64	1		T157	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T65	1		T31	1		T40	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T231	1		T183	1		T166	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T9	3		T10	9		T40	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T6	1		T67	14		T68	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T33	1		T34	3		T51	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T4	1		T64	1		T157	21
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T65	1		T68	14		T255	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T166	16		T197	14		T49	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T8	3		T9	8		T31	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	324	1			T4	1		T43	7		T46	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	305	1			T10	3		T231	1		T168	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T47	3		T234	3		T283	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T183	1		T279	1		T176	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17548	1			T3	14		T5	25		T31	142
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T68	12		T174	12		T210	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T34	10		T164	10		T196	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T40	13		T204	10		T248	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1383	1			T1	28		T65	11		T58	19
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T66	17		T258	6		T48	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T66	9		T163	5		T129	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T32	11		T204	9		T211	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T157	1		T232	1		T54	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T65	3		T40	11		T66	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T177	3		T194	7		T282	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T33	10		T174	12		T50	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T67	14		T68	12		T162	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T34	16		T51	2		T35	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T47	9		T246	13		T163	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T65	11		T68	11		T255	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T197	4		T49	1		T129	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T232	12		T187	15		T54	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T46	3		T63	9		T165	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T168	10		T253	21		T172	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T47	1		T283	12		T20	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T176	9		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T236	8		T348	1		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T68	12		T174	10		T210	11

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T165	10		T34	17		T47	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T183	1		T168	14		T278	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T175	15		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T246	10		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T67	10		T292	1		T164	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T8	1		T9	9		T68	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1403	1			T1	3		T2	8		T5	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T40	21		T66	1		T204	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T65	1		T66	1		T233	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T204	1		T173	1		T211	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T6	1		T64	1		T157	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T65	1		T40	13		T66	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T166	1		T177	1		T194	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T9	3		T31	1		T40	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T231	1		T67	14		T183	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T10	9		T33	1		T34	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T4	1		T6	1		T68	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T65	1		T68	14		T130	20
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T64	1		T166	6		T49	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T9	8		T31	3		T161	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	295	1			T4	1		T43	7		T46	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	308	1			T8	3		T10	3		T40	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17517	1			T3	14		T5	25		T31	142
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T165	12		T34	12		T47	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T168	10		T238	10		T228	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T246	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T164	10		T196	7		T55	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T68	12		T248	9		T174	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1357	1			T1	28		T58	19		T62	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T40	13		T66	17		T204	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T65	11		T66	9		T233	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T204	9		T211	18		T130	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T157	1		T163	5		T129	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T65	3		T40	11		T66	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T177	3		T194	7		T54	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T33	10		T50	9		T270	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T67	14		T162	11		T260	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T34	16		T174	12		T51	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T68	12		T47	9		T246	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T65	11		T68	11		T232	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T49	1		T53	1		T170	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T255	5		T187	15		T54	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T46	3		T63	9		T174	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T232	12		T253	21		T172	17

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22695

1

T1

3

T2

8

T3

14

auto[1]

auto[0]

4440

1

T1

28

T65

25

T40

24