Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27135

1

T1

31

T2

8

T3

14

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23420

1

T1

31

T2

8

T3

14

auto[ADC_CTRL_FILTER_COND_OUT]

3715

1

T4

1

T5

13

T6

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20864

1

T3

14

T4

2

T5

38

auto[1]

6271

1

T1

31

T2

8

T6

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22883

1

T1

31

T2

1

T3

14

auto[1]

4252

1

T2

7

T5

12

T7

19

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	56	1			T279	1		T178	19		T343	22
values[0]	90	1			T33	19		T207	29		T118	14
values[1]	530	1			T6	1		T65	16		T68	25
values[2]	568	1			T8	3		T65	12		T68	24
values[3]	838	1			T4	1		T10	3		T64	1
values[4]	722	1			T9	8		T40	6		T66	18
values[5]	796	1			T4	1		T10	9		T31	1
values[6]	909	1			T40	24		T43	7		T66	10
values[7]	863	1			T5	13		T8	1		T40	34
values[8]	635	1			T31	3		T63	10		T34	23
values[9]	3611	1			T1	31		T2	8		T6	1
minimum	17517	1			T3	14		T5	25		T31	142

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	743	1			T6	1		T65	16		T68	25
values[1]	664	1			T8	3		T65	12		T68	24
values[2]	705	1			T4	1		T10	3		T40	5
values[3]	836	1			T9	8		T40	1		T67	38
values[4]	793	1			T4	1		T10	9		T31	1
values[5]	877	1			T40	34		T43	7		T66	10
values[6]	3147	1			T1	31		T2	8		T5	13
values[7]	659	1			T6	1		T63	10		T157	21
values[8]	933	1			T9	12		T66	7		T46	12
values[9]	229	1			T262	13		T340	1		T341	1
minimum	17549	1			T3	14		T5	25		T31	142

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22695

1

T1

3

T2

8

T3

14

auto[1]

4440

1

T1

28

T65

25

T40

24

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T65	4		T161	1		T166	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T6	1		T65	12		T68	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T8	1		T68	13		T183	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T65	12		T33	1		T166	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T10	1		T40	1		T66	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T4	1		T183	1		T163	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T9	1		T40	1		T67	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T157	2		T204	11		T173	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T4	1		T31	1		T40	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T10	1		T292	1		T171	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T43	1		T66	10		T231	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T40	14		T68	13		T177	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1677	1			T1	31		T2	1		T7	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T5	1		T231	1		T34	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T157	1		T173	1		T248	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T6	1		T63	10		T163	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T9	2		T66	7		T161	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T46	8		T204	10		T255	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T340	1		T341	1		T298	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T262	1		T298	2		T135	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17395	1			T3	14		T5	25		T31	141
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T349	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T232	7		T51	2		T265	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T68	13		T34	2		T174	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T8	2		T68	11		T130	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T166	5		T197	13		T53	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T10	2		T40	4		T162	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T163	17		T187	16		T53	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T9	7		T67	22		T165	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T157	3		T129	3		T247	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T40	12		T246	15		T174	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T10	8		T171	16		T174	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T43	6		T162	13		T168	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T40	20		T68	6		T239	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1009	1			T2	7		T7	19		T31	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T5	12		T34	12		T47	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T157	20		T248	10		T262	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T163	9		T234	2		T197	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T9	10		T34	16		T166	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T46	4		T255	5		T246	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T298	2		T81	4		T104	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T262	12		T298	1		T135	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T31	1		T32	2		T46	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T279	1		T343	11		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T178	10		T350	14		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T33	11		T118	7		T347	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T207	14		T345	6		T312	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T65	4		T166	1		T177	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T6	1		T65	12		T68	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T8	1		T68	13		T183	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T65	12		T183	1		T166	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T10	1		T64	1		T162	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T4	1		T33	1		T187	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T9	1		T40	2		T66	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T157	2		T163	16		T129	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T4	1		T31	1		T67	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T10	1		T204	11		T173	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T40	12		T43	1		T66	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T211	19		T210	12		T196	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T8	1		T32	12		T157	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T5	1		T40	14		T231	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T31	1		T173	1		T340	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T63	10		T34	11		T248	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1844	1			T1	31		T2	1		T7	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	340	1			T6	1		T46	8		T204	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17382	1			T3	14		T5	25		T31	141
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T343	11		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T178	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T33	8		T118	7		T347	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T207	15		T312	2		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T232	7		T51	2		T265	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T68	13		T34	2		T174	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T8	2		T68	11		T130	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T166	5		T197	13		T187	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T10	2		T162	1		T232	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T187	12		T53	1		T280	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T9	7		T40	4		T67	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T157	3		T163	17		T129	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T67	9		T246	15		T174	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T10	8		T171	16		T174	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T40	12		T43	6		T162	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T239	9		T54	6		T278	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T32	11		T157	20		T248	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T5	12		T40	20		T68	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T31	2		T250	1		T285	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T34	12		T163	9		T234	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1145	1			T2	7		T7	19		T9	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T46	4		T255	5		T246	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T31	1		T32	2		T46	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T65	1		T161	1		T166	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T6	1		T65	1		T68	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T8	3		T68	12		T183	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T65	1		T33	1		T166	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T10	3		T40	5		T66	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T4	1		T183	1		T163	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T9	8		T40	1		T67	24
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T157	4		T204	1		T173	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T4	1		T31	1		T40	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T10	9		T292	1		T171	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T43	7		T66	1		T231	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T40	21		T68	7		T177	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1341	1			T1	3		T2	8		T7	22
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T5	13		T231	1		T34	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T157	21		T173	1		T248	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T6	1		T63	1		T163	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T9	12		T66	1		T161	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T46	9		T204	1		T255	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T340	1		T341	1		T298	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T262	13		T298	2		T135	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17529	1			T3	14		T5	25		T31	142
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T349	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T65	3		T177	15		T252	18
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T65	11		T68	11		T34	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T68	12		T130	11		T232	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T65	11		T197	4		T53	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T66	17		T48	1		T252	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T163	15		T187	15		T53	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T67	14		T204	2		T165	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T157	1		T204	10		T129	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T40	11		T246	13		T174	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T174	12		T211	18		T207	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T66	9		T162	11		T168	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T40	13		T68	12		T177	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1345	1			T1	28		T32	11		T58	19
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T34	10		T47	1		T50	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T248	9		T285	4		T282	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T63	9		T163	8		T232	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T66	6		T165	4		T34	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T46	3		T204	9		T255	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T298	4		T303	9		T81	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T298	1		T135	8		T16	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T33	10		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T349	9		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T279	1		T343	12		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T178	10		T350	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T33	9		T118	8		T347	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T207	16		T345	1		T312	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T65	1		T166	1		T177	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T6	1		T65	1		T68	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T8	3		T68	12		T183	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T65	1		T183	1		T166	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	290	1			T10	3		T64	1		T162	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T4	1		T33	1		T187	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T9	8		T40	6		T66	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T157	4		T163	18		T129	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T4	1		T31	1		T67	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T10	9		T204	1		T173	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T40	13		T43	7		T66	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T211	1		T210	1		T196	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T8	1		T32	12		T157	21
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T5	13		T40	21		T231	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T31	3		T173	1		T340	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T63	1		T34	13		T248	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1515	1			T1	3		T2	8		T7	22
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	356	1			T6	1		T46	9		T204	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17517	1			T3	14		T5	25		T31	142
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T343	10		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T178	9		T350	13		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T33	10		T118	6		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T207	13		T345	5		T312	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T65	3		T177	15		T252	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T65	11		T68	11		T34	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T68	12		T130	11		T245	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T65	11		T197	4		T187	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T252	10		T233	13		T232	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T187	10		T53	1		T288	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T66	17		T67	14		T204	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T157	1		T163	15		T129	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T246	13		T174	10		T249	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T204	10		T174	12		T207	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T40	11		T66	9		T162	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T211	18		T210	11		T54	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T32	11		T248	9		T130	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T40	13		T68	12		T47	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T285	4		T282	14		T288	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T63	9		T34	10		T163	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1474	1			T1	28		T66	6		T58	19
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T46	3		T204	9		T255	5

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22695

1

T1

3

T2

8

T3

14

auto[1]

auto[0]

4440

1

T1

28

T65

25

T40

24