Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27135

1

T1

31

T2

8

T3

14

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23274

1

T1

31

T2

8

T3

14

auto[ADC_CTRL_FILTER_COND_OUT]

3861

1

T4

1

T6

1

T8

4

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20692

1

T3

14

T5

38

T6

1

auto[1]

6443

1

T1

31

T2

8

T4

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22883

1

T1

31

T2

1

T3

14

auto[1]

4252

1

T2

7

T5

12

T7

19

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	368	1			T5	13		T33	1		T246	29
values[0]	81	1			T232	9		T135	18		T28	1
values[1]	677	1			T6	1		T8	1		T31	1
values[2]	539	1			T10	3		T40	34		T161	1
values[3]	873	1			T9	11		T10	9		T65	12
values[4]	3140	1			T1	31		T2	8		T7	22
values[5]	682	1			T65	12		T31	3		T183	1
values[6]	848	1			T8	3		T65	4		T40	1
values[7]	757	1			T4	2		T231	2		T34	48
values[8]	749	1			T6	1		T9	9		T66	18
values[9]	904	1			T66	7		T67	28		T63	10
minimum	17517	1			T3	14		T5	25		T31	142

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	717	1			T6	1		T8	1		T40	29
values[1]	592	1			T9	8		T10	12		T40	34
values[2]	823	1			T9	3		T65	12		T67	10
values[3]	3208	1			T1	31		T2	8		T7	22
values[4]	677	1			T65	4		T183	1		T204	14
values[5]	862	1			T4	1		T8	3		T40	1
values[6]	702	1			T4	1		T231	2		T34	48
values[7]	655	1			T6	1		T9	9		T66	18
values[8]	869	1			T66	7		T64	1		T157	21
values[9]	286	1			T5	13		T63	10		T161	1
minimum	17744	1			T3	14		T5	25		T31	143

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22695

1

T1

3

T2

8

T3

14

auto[1]

4440

1

T1

28

T65

25

T40

24

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T6	1		T40	13		T68	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T8	1		T196	1		T239	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T9	1		T40	14		T66	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T10	2		T43	1		T161	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T65	12		T183	1		T166	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	300	1			T9	1		T67	1		T68	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1727	1			T1	31		T2	1		T7	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T64	1		T157	2		T49	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T65	4		T204	3		T47	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T183	1		T204	11		T173	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T4	1		T33	11		T165	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T8	1		T40	1		T166	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T231	1		T244	1		T258	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T4	1		T231	1		T34	30
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T32	12		T166	1		T47	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T6	1		T9	1		T66	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T66	7		T64	1		T157	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T174	11		T169	1		T170	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T5	1		T161	1		T207	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T63	10		T163	16		T174	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17434	1			T3	14		T5	25		T31	142
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T46	8		T130	12		T232	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T40	16		T68	11		T246	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T239	13		T54	6		T263	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T9	7		T40	20		T163	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T10	10		T43	6		T130	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T166	5		T234	2		T197	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T9	2		T67	9		T68	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1016	1			T2	7		T7	19		T31	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T157	3		T49	1		T207	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T47	10		T187	12		T175	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T259	9		T260	9		T311	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T33	8		T34	12		T174	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T8	2		T166	9		T162	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T258	6		T262	14		T263	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T34	18		T255	5		T194	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T32	11		T47	1		T50	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T9	8		T67	13		T162	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T157	20		T246	15		T51	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T174	11		T264	8		T263	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T5	12		T207	2		T278	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T163	17		T174	10		T188	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T31	1		T68	6		T32	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T46	4		T130	9		T232	16

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T5	1		T33	1		T246	14
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T163	16		T174	13		T169	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T135	14		T351	1		T273	20
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T232	2		T28	1		T352	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T6	1		T31	1		T40	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T8	1		T46	8		T130	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T40	14		T246	13		T163	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T10	1		T161	1		T196	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T9	1		T65	12		T66	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	310	1			T9	1		T10	1		T43	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1692	1			T1	31		T2	1		T7	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T64	1		T248	1		T49	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T65	12		T31	1		T204	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T183	1		T157	2		T204	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T65	4		T33	11		T165	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T8	1		T40	1		T162	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T4	1		T231	1		T173	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T4	1		T231	1		T34	30
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T32	12		T210	12		T50	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T6	1		T9	1		T66	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T66	7		T64	1		T157	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T67	15		T63	10		T174	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17382	1			T3	14		T5	25		T31	141
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T5	12		T246	15		T278	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T163	17		T174	10		T264	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T135	4		T273	17		T353	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T232	7		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T40	16		T68	17		T168	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T46	4		T130	9		T232	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T40	20		T246	9		T163	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T10	2		T306	10		T236	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T9	7		T166	5		T163	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T9	2		T10	8		T43	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1004	1			T2	7		T7	19		T37	20
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T49	1		T194	8		T239	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T31	2		T165	8		T47	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T157	3		T207	15		T260	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T33	8		T34	12		T174	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T8	2		T162	1		T268	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T258	6		T262	14		T263	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T34	18		T166	9		T194	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T32	11		T50	5		T229	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T9	8		T162	13		T255	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T157	20		T47	1		T207	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T67	13		T174	11		T263	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T31	1		T32	2		T46	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	304	1			T6	1		T40	18		T68	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T8	1		T196	1		T239	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T9	8		T40	21		T66	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T10	12		T43	7		T161	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T65	1		T183	1		T166	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T9	3		T67	10		T68	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1357	1			T1	3		T2	8		T7	22
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T64	1		T157	4		T49	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T65	1		T204	1		T47	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T183	1		T204	1		T173	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T4	1		T33	9		T165	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T8	3		T40	1		T166	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T231	1		T244	1		T258	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T4	1		T231	1		T34	20
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T32	12		T166	1		T47	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T6	1		T9	9		T66	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T66	1		T64	1		T157	21
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T174	12		T169	1		T170	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T5	13		T161	1		T207	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T63	1		T163	18		T174	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17560	1			T3	14		T5	25		T31	143
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T46	9		T130	10		T232	18
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T40	11		T68	12		T246	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T54	5		T302	10		T117	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T40	13		T66	9		T163	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T211	18		T130	10		T119	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T65	11		T252	18		T253	21
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T68	11		T164	10		T207	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1386	1			T1	28		T65	11		T58	19
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T157	1		T49	1		T207	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T65	3		T204	2		T47	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T204	10		T260	10		T254	21
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T33	10		T165	4		T34	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T177	15		T196	9		T249	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T258	6		T233	11		T170	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T34	28		T255	5		T194	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T32	11		T47	1		T210	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T66	17		T67	14		T162	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T66	6		T204	9		T246	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T174	10		T170	7		T283	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T207	7		T271	9		T272	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T63	9		T163	15		T174	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T68	12		T168	10		T304	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T46	3		T130	11		T232	13

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T5	13		T33	1		T246	16
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T163	18		T174	11		T169	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T135	10		T351	1		T273	18
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T232	8		T28	1		T352	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T6	1		T31	1		T40	18
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T8	1		T46	9		T130	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T40	21		T246	10		T163	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T10	3		T161	1		T196	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T9	8		T65	1		T66	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T9	3		T10	9		T43	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1339	1			T1	3		T2	8		T7	22
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T64	1		T248	1		T49	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T65	1		T31	3		T204	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T183	1		T157	4		T204	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T65	1		T33	9		T165	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T8	3		T40	1		T162	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T4	1		T231	1		T173	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	301	1			T4	1		T231	1		T34	20
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T32	12		T210	1		T50	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T6	1		T9	9		T66	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T66	1		T64	1		T157	21
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T67	14		T63	1		T174	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17517	1			T3	14		T5	25		T31	142
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T246	13		T283	12		T238	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T163	15		T174	12		T170	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T135	8		T273	19		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T232	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T40	11		T68	24		T168	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T46	3		T130	11		T232	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T40	13		T246	12		T163	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T119	13		T269	1		T274	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T65	11		T66	9		T163	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T68	11		T164	10		T211	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1357	1			T1	28		T58	19		T62	19
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T49	1		T194	7		T54	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T65	11		T204	2		T165	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T157	1		T204	10		T207	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T65	3		T33	10		T165	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T177	15		T196	9		T298	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T258	6		T233	11		T170	20
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T34	28		T194	3		T52	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T32	11		T210	11		T50	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T66	17		T162	11		T255	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T66	6		T204	9		T47	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T67	14		T63	9		T174	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22695

1

T1

3

T2

8

T3

14

auto[1]

auto[0]

4440

1

T1

28

T65

25

T40

24