Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_5

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	331	1			T6	1		T31	1		T40	18
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T8	1		T46	9		T197	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T9	8		T40	21		T166	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T10	12		T161	1		T163	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T65	1		T66	1		T183	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T9	3		T43	7		T67	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1368	1			T1	3		T2	8		T7	22
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T64	1		T157	4		T49	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T65	1		T204	1		T47	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T183	1		T204	1		T173	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T4	1		T33	9		T165	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T8	3		T40	1		T34	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T231	1		T244	1		T258	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T4	1		T231	1		T173	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T32	12		T166	1		T210	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T6	1		T9	9		T66	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T66	1		T157	21		T33	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T174	12		T169	1		T170	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T5	13		T64	1		T161	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T63	1		T163	18		T174	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17517	1			T3	14		T5	25		T31	142
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T40	11		T68	24		T168	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T46	3		T197	4		T130	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T40	13		T163	5		T48	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T163	8		T211	18		T130	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T65	11		T66	9		T252	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T68	11		T164	10		T207	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1382	1			T1	28		T65	11		T58	19
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T157	1		T49	1		T207	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T65	3		T204	2		T47	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T204	10		T177	15		T260	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T33	10		T165	4		T34	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T34	16		T196	9		T249	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T258	6		T233	11		T170	20
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T194	3		T271	6		T245	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T32	11		T210	11		T50	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T66	17		T67	14		T34	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T66	6		T204	9		T47	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T174	10		T170	7		T264	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T207	7		T235	12		T272	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T63	9		T163	15		T174	12

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T198	1		T256	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T40	13		T257	1		T135	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T232	8		T18	2		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T6	1		T31	1		T40	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T8	1		T46	9		T197	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T40	21		T163	8		T48	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T10	3		T161	1		T266	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T9	8		T65	1		T66	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T9	3		T10	9		T43	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1332	1			T1	3		T2	8		T7	22
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T64	1		T173	1		T248	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T65	1		T31	3		T165	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T157	4		T204	1		T244	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T65	1		T33	9		T165	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T8	3		T40	1		T183	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T4	1		T231	1		T173	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	311	1			T4	1		T231	1		T34	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T32	12		T210	1		T50	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T6	1		T9	9		T66	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	348	1			T5	13		T66	1		T64	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	333	1			T67	14		T63	1		T163	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17517	1			T3	14		T5	25		T31	142
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T198	13		T256	9		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T40	11		T135	8		T273	19
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T232	1		T18	1		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T68	24		T168	10		T246	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T46	3		T197	4		T130	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T40	13		T163	5		T48	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T119	13		T269	1		T274	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T65	11		T66	9		T253	21
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T68	11		T163	8		T164	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1355	1			T1	28		T58	19		T62	19
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T194	7		T54	6		T261	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T65	11		T165	8		T47	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T157	1		T204	10		T49	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T65	3		T33	10		T165	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T34	16		T177	15		T196	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T170	20		T269	1		T275	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T34	12		T194	3		T52	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T32	11		T210	11		T50	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T66	17		T162	11		T255	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T66	6		T204	9		T47	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	315	1			T67	14		T63	9		T163	15

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22695

1

T1

3

T2

8

T3

14

auto[1]

auto[0]

4440

1

T1

28

T65

25

T40

24