Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27135

1

T1

31

T2

8

T3

14

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23373

1

T1

31

T2

8

T3

14

auto[ADC_CTRL_FILTER_COND_OUT]

3762

1

T8

4

T9

20

T10

12

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21017

1

T3

14

T4

1

T5

38

auto[1]

6118

1

T1

31

T2

8

T4

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22883

1

T1

31

T2

1

T3

14

auto[1]

4252

1

T2

7

T5

12

T7

19

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	13	1			T276	13		-	-		-	-
values[0]	62	1			T246	22		T175	15		T277	25
values[1]	692	1			T8	1		T9	9		T67	10
values[2]	2991	1			T1	31		T2	8		T5	13
values[3]	851	1			T65	12		T66	10		T204	10
values[4]	705	1			T6	1		T9	3		T65	4
values[5]	544	1			T31	1		T40	1		T33	19
values[6]	771	1			T10	9		T231	1		T67	28
values[7]	862	1			T6	1		T65	12		T68	44
values[8]	722	1			T4	1		T9	8		T31	3
values[9]	1405	1			T4	1		T8	3		T10	3
minimum	17517	1			T3	14		T5	25		T31	142

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	894	1			T5	13		T8	1		T9	9
values[1]	3088	1			T1	31		T2	8		T7	22
values[2]	792	1			T66	10		T32	23		T204	10
values[3]	690	1			T6	1		T65	4		T31	1
values[4]	567	1			T9	3		T10	9		T40	1
values[5]	744	1			T6	1		T67	28		T68	19
values[6]	862	1			T4	1		T65	12		T68	25
values[7]	907	1			T8	3		T9	8		T31	3
values[8]	936	1			T4	1		T10	3		T43	7
values[9]	138	1			T47	4		T234	3		T174	4
minimum	17517	1			T3	14		T5	25		T31	142

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22695

1

T1

3

T2

8

T3

14

auto[1]

4440

1

T1

28

T65

25

T40

24

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T5	1		T67	1		T34	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	316	1			T8	1		T9	1		T40	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1764	1			T1	31		T2	1		T7	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T66	18		T258	7		T48	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T66	10		T163	6		T129	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	296	1			T32	12		T204	10		T173	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T6	1		T64	1		T157	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T65	4		T31	1		T40	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T231	1		T183	1		T166	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T9	1		T10	1		T40	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	309	1			T6	1		T67	15		T68	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T33	1		T34	17		T51	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T4	1		T64	1		T157	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T65	12		T68	12		T255	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T166	1		T197	5		T49	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T8	1		T9	1		T31	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T4	1		T43	1		T46	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T10	1		T231	1		T183	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T47	3		T234	1		T174	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T278	1		T279	1		T176	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17382	1			T3	14		T5	25		T31	141
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T5	12		T67	9		T34	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T9	8		T40	20		T68	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1036	1			T2	7		T7	19		T37	20
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T258	6		T48	1		T130	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T163	7		T129	3		T53	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T32	11		T207	11		T261	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T157	3		T232	7		T54	19
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T40	12		T130	9		T270	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T194	8		T280	1		T175	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T9	2		T10	8		T33	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T67	13		T68	6		T162	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T34	2		T51	2		T239	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T157	20		T162	1		T47	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T68	13		T255	5		T130	19
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T166	5		T197	13		T49	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T8	2		T9	7		T31	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T43	6		T46	4		T165	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T10	2		T168	13		T172	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T47	1		T234	2		T174	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T278	12		T176	10		T281	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T31	1		T32	2		T46	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T276	3		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T175	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T246	13		T277	9		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T67	1		T34	11		T173	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T8	1		T9	1		T68	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1679	1			T1	31		T2	1		T5	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T40	14		T66	18		T204	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T65	12		T66	10		T163	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T204	10		T173	1		T211	19
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T6	1		T64	1		T157	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T9	1		T65	4		T40	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T166	1		T177	4		T194	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T31	1		T40	1		T33	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T231	1		T67	15		T183	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T10	1		T33	1		T34	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T6	1		T68	13		T157	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T65	12		T68	12		T130	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T4	1		T64	1		T166	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T9	1		T31	1		T255	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	367	1			T4	1		T43	1		T46	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	353	1			T8	1		T10	1		T40	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17382	1			T3	14		T5	25		T31	141
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T276	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T175	14		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T246	9		T277	16		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T67	9		T34	12		T207	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T9	8		T68	11		T248	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1013	1			T2	7		T5	12		T7	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T40	20		T258	6		T48	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T163	17		T259	9		T280	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T130	9		T207	26		T262	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T157	3		T163	7		T129	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T9	2		T40	12		T32	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T194	8		T54	19		T263	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T33	8		T239	13		T271	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T67	13		T162	13		T265	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T10	8		T34	2		T268	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T68	6		T157	20		T162	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T68	13		T130	19		T232	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T166	5		T49	1		T53	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T9	7		T31	2		T255	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	336	1			T43	6		T46	4		T165	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	349	1			T8	2		T10	2		T40	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T31	1		T32	2		T46	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T5	13		T67	10		T34	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T8	1		T9	9		T40	21
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1387	1			T1	3		T2	8		T7	22
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T66	1		T258	7		T48	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T66	1		T163	8		T129	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T32	12		T204	1		T173	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T6	1		T64	1		T157	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T65	1		T31	1		T40	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T231	1		T183	1		T166	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T9	3		T10	9		T40	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T6	1		T67	14		T68	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T33	1		T34	3		T51	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T4	1		T64	1		T157	21
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T65	1		T68	14		T255	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T166	6		T197	14		T49	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T8	3		T9	8		T31	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	305	1			T4	1		T43	7		T46	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T10	3		T231	1		T183	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T47	3		T234	3		T174	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T278	13		T279	1		T176	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17517	1			T3	14		T5	25		T31	142
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T34	10		T164	10		T207	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T40	13		T68	12		T204	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1413	1			T1	28		T65	11		T58	19
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T66	17		T258	6		T48	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T66	9		T163	5		T129	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T32	11		T204	9		T211	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T157	1		T232	1		T54	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T65	3		T40	11		T66	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T177	3		T194	7		T282	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T33	10		T174	12		T50	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T67	14		T68	12		T162	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T34	16		T51	2		T35	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T47	9		T246	13		T163	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T65	11		T68	11		T255	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T197	4		T49	1		T129	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T232	12		T187	15		T54	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T46	3		T63	9		T165	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T168	10		T253	21		T172	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T47	1		T174	1		T283	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T176	9		T284	13		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T276	11		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T175	15		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T246	10		T277	17		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T67	10		T34	13		T173	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T8	1		T9	9		T68	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1357	1			T1	3		T2	8		T5	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T40	21		T66	1		T204	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T65	1		T66	1		T163	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T204	1		T173	1		T211	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T6	1		T64	1		T157	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T9	3		T65	1		T40	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T166	1		T177	1		T194	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T31	1		T40	1		T33	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T231	1		T67	14		T183	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T10	9		T33	1		T34	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T6	1		T68	7		T157	21
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T65	1		T68	14		T130	20
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T4	1		T64	1		T166	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T9	8		T31	3		T255	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	413	1			T4	1		T43	7		T46	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	416	1			T8	3		T10	3		T40	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17517	1			T3	14		T5	25		T31	142
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T276	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T246	12		T277	8		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T34	10		T164	10		T207	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T68	12		T248	9		T174	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1335	1			T1	28		T58	19		T62	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T40	13		T66	17		T204	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T65	11		T66	9		T163	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T204	9		T211	18		T130	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T157	1		T163	5		T129	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T65	3		T40	11		T66	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T177	3		T194	7		T54	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T33	10		T271	1		T269	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T67	14		T162	11		T260	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T34	16		T174	12		T51	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T68	12		T47	9		T246	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T65	11		T68	11		T232	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T49	1		T53	1		T254	21
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T255	5		T232	12		T187	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	290	1			T46	3		T63	9		T165	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T168	10		T253	21		T172	17

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22695

1

T1

3

T2

8

T3

14

auto[1]

auto[0]

4440

1

T1

28

T65

25

T40

24