Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27135

1

T1

31

T2

8

T3

14

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23322

1

T1

31

T2

8

T3

14

auto[ADC_CTRL_FILTER_COND_OUT]

3813

1

T4

1

T5

13

T8

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20204

1

T3

14

T5

38

T6

1

auto[1]

6931

1

T1

31

T2

8

T4

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22883

1

T1

31

T2

1

T3

14

auto[1]

4252

1

T2

7

T5

12

T7

19

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	407	1			T31	1		T39	2		T41	4
values[0]	59	1			T63	10		T157	5		T232	24
values[1]	776	1			T6	2		T9	3		T65	12
values[2]	3007	1			T1	31		T2	8		T7	22
values[3]	616	1			T65	12		T31	3		T68	19
values[4]	672	1			T40	5		T66	10		T67	10
values[5]	839	1			T5	13		T32	23		T161	1
values[6]	673	1			T9	8		T65	4		T173	2
values[7]	753	1			T4	1		T40	1		T66	18
values[8]	949	1			T8	3		T161	2		T204	14
values[9]	1246	1			T4	1		T8	1		T9	9
minimum	17138	1			T3	14		T5	25		T31	141

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	981	1			T6	2		T9	3		T65	12
values[1]	2932	1			T1	31		T2	8		T7	22
values[2]	649	1			T65	12		T40	5		T66	10
values[3]	843	1			T67	10		T64	1		T161	1
values[4]	821	1			T5	13		T32	23		T173	1
values[5]	595	1			T4	1		T9	8		T65	4
values[6]	785	1			T40	1		T66	18		T68	24
values[7]	835	1			T4	1		T8	3		T161	1
values[8]	963	1			T8	1		T10	12		T40	58
values[9]	214	1			T9	9		T166	10		T244	1
minimum	17517	1			T3	14		T5	25		T31	142

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22695

1

T1

3

T2

8

T3

14

auto[1]

4440

1

T1

28

T65

25

T40

24

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T6	2		T9	1		T65	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T63	10		T157	2		T166	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1696	1			T1	31		T2	1		T7	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T31	2		T183	1		T33	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T66	10		T46	8		T166	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T65	12		T40	1		T68	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T64	1		T248	10		T258	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	306	1			T67	1		T161	1		T165	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T177	16		T48	5		T52	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T5	1		T32	12		T173	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T9	1		T65	4		T173	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T4	1		T47	3		T49	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T40	1		T68	13		T130	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T66	18		T183	1		T34	28
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T4	1		T8	1		T204	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T161	1		T204	3		T162	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	298	1			T10	2		T40	14		T68	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T8	1		T40	12		T64	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T194	1		T259	1		T285	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T9	1		T166	1		T244	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17382	1			T3	14		T5	25		T31	141
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T9	2		T43	6		T67	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T157	3		T130	9		T232	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1033	1			T2	7		T7	19		T37	20
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T31	2		T33	8		T129	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T46	4		T166	5		T255	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T40	4		T68	6		T260	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T248	10		T258	6		T262	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T67	9		T165	8		T246	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T48	1		T52	1		T263	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T5	12		T32	11		T163	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T9	7		T207	2		T280	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T47	1		T49	1		T265	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T68	11		T130	9		T207	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T34	14		T174	13		T130	19
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T8	2		T34	16		T162	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T162	13		T47	10		T50	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T10	10		T40	20		T68	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T40	12		T234	2		T174	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T194	1		T259	9		T285	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T9	8		T166	9		T54	19
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T31	1		T32	2		T46	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	393	1			T31	1		T39	2		T41	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T266	1		T212	1		T286	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T63	10		T157	2		T232	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T6	2		T9	1		T65	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T31	1		T166	1		T210	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1703	1			T1	31		T2	1		T7	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T183	1		T33	11		T211	19
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T46	8		T165	5		T255	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T65	12		T31	1		T68	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T66	10		T64	1		T166	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T40	1		T67	1		T165	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T248	10		T177	16		T48	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T5	1		T32	12		T161	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T9	1		T65	4		T173	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T173	1		T47	3		T49	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T40	1		T68	13		T207	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T4	1		T66	18		T183	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T8	1		T204	11		T34	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T161	2		T204	3		T50	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	307	1			T4	1		T10	2		T40	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	351	1			T8	1		T9	1		T40	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17003	1			T3	14		T5	25		T31	140
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T178	14		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T286	2		T281	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T157	3		T232	11		T287	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T9	2		T43	6		T268	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T130	9		T194	8		T249	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1076	1			T2	7		T7	19		T37	20
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T33	8		T129	2		T263	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T46	4		T255	5		T197	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T31	2		T68	6		T265	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T166	5		T258	6		T232	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T40	4		T67	9		T165	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T248	10		T48	1		T52	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T5	12		T32	11		T163	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T9	7		T207	2		T263	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T47	1		T49	1		T232	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T68	11		T207	11		T262	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T34	14		T174	13		T130	19
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T8	2		T34	16		T162	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T50	5		T239	9		T135	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	300	1			T10	10		T40	20		T68	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T9	8		T40	12		T166	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T31	1		T32	2		T46	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	319	1			T6	2		T9	3		T65	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T63	1		T157	4		T166	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1370	1			T1	3		T2	8		T7	22
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T31	4		T183	1		T33	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T66	1		T46	9		T166	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T65	1		T40	5		T68	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T64	1		T248	11		T258	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T67	10		T161	1		T165	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T177	1		T48	5		T52	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T5	13		T32	12		T173	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T9	8		T65	1		T173	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T4	1		T47	3		T49	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T40	1		T68	12		T130	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T66	1		T183	1		T34	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T4	1		T8	3		T204	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T161	1		T204	1		T162	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	321	1			T10	12		T40	21		T68	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T8	1		T40	13		T64	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T194	2		T259	10		T285	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T9	9		T166	10		T244	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17517	1			T3	14		T5	25		T31	142
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T65	11		T67	14		T163	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T63	9		T157	1		T211	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1359	1			T1	28		T66	6		T58	19
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T33	10		T129	10		T288	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T66	9		T46	3		T255	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T65	11		T68	12		T204	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T248	9		T258	6		T282	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T165	8		T246	13		T163	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T177	15		T48	1		T52	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T32	11		T163	5		T164	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T65	3		T207	7		T196	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T47	1		T49	1		T233	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T68	12		T130	11		T207	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T66	17		T34	26		T174	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T204	10		T34	12		T168	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T204	2		T162	11		T47	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T40	13		T68	11		T246	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T40	11		T174	12		T252	28
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T285	4		T289	8		T290	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T54	6		T264	13		T291	11

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	394	1			T31	1		T39	2		T41	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T266	1		T212	1		T286	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T63	1		T157	4		T232	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T6	2		T9	3		T65	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T31	1		T166	1		T210	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1413	1			T1	3		T2	8		T7	22
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T183	1		T33	9		T211	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T46	9		T165	1		T255	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T65	1		T31	3		T68	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T66	1		T64	1		T166	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T40	5		T67	10		T165	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T248	11		T177	1		T48	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T5	13		T32	12		T161	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T9	8		T65	1		T173	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T173	1		T47	3		T49	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T40	1		T68	12		T207	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T4	1		T66	1		T183	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T8	3		T204	1		T34	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T161	2		T204	1		T50	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	364	1			T4	1		T10	12		T40	21
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	352	1			T8	1		T9	9		T40	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17138	1			T3	14		T5	25		T31	141
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T178	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T286	6		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T63	9		T157	1		T232	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T65	11		T163	15		T207	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T210	11		T130	10		T194	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1366	1			T1	28		T66	6		T67	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T33	10		T211	18		T129	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T46	3		T165	4		T255	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T65	11		T68	12		T204	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T66	9		T258	6		T232	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T165	8		T246	13		T163	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T248	9		T177	15		T48	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T32	11		T163	5		T164	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T65	3		T207	7		T196	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T47	1		T49	1		T232	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T68	12		T207	10		T54	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T66	17		T34	26		T174	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T204	10		T34	12		T168	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T204	2		T50	9		T170	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T40	13		T68	11		T246	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T40	11		T162	11		T47	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22695

1

T1

3

T2

8

T3

14

auto[1]

auto[0]

4440

1

T1

28

T65

25

T40

24