Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27135

1

T1

31

T2

8

T3

14

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23176

1

T1

31

T2

8

T3

14

auto[ADC_CTRL_FILTER_COND_OUT]

3959

1

T4

1

T6

2

T9

17

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20678

1

T3

14

T4

2

T5

25

auto[1]

6457

1

T1

31

T2

8

T5

13

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22883

1

T1

31

T2

1

T3

14

auto[1]

4252

1

T2

7

T5

12

T7

19

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	31	1			T10	9		T232	22		-	-
values[0]	33	1			T228	1		T275	4		T237	14
values[1]	919	1			T9	8		T231	1		T165	17
values[2]	818	1			T4	1		T9	9		T31	1
values[3]	535	1			T4	1		T6	1		T65	4
values[4]	638	1			T5	13		T8	3		T65	12
values[5]	3184	1			T1	31		T2	8		T6	1
values[6]	756	1			T9	3		T31	3		T40	24
values[7]	608	1			T43	7		T157	5		T292	1
values[8]	634	1			T10	3		T64	1		T268	12
values[9]	1462	1			T8	1		T65	12		T40	39
minimum	17517	1			T3	14		T5	25		T31	142

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1099	1			T9	17		T31	1		T231	1
values[1]	811	1			T4	1		T46	12		T161	1
values[2]	570	1			T4	1		T5	13		T6	1
values[3]	2998	1			T1	31		T2	8		T7	22
values[4]	753	1			T6	1		T31	3		T66	10
values[5]	744	1			T9	3		T40	24		T43	7
values[6]	629	1			T10	3		T157	5		T34	29
values[7]	703	1			T66	18		T32	23		T64	1
values[8]	1045	1			T10	9		T65	12		T40	39
values[9]	236	1			T8	1		T196	8		T282	29
minimum	17547	1			T3	14		T5	25		T31	142

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22695

1

T1

3

T2

8

T3

14

auto[1]

4440

1

T1

28

T65

25

T40

24

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T31	1		T231	1		T34	17
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	340	1			T9	2		T165	9		T166	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T46	8		T173	1		T48	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T4	1		T161	1		T204	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T4	1		T5	1		T65	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T6	1		T65	12		T183	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1710	1			T1	31		T2	1		T7	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T67	15		T248	1		T177	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T66	10		T33	11		T161	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T6	1		T31	1		T67	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T9	1		T68	13		T197	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T40	12		T43	1		T64	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T157	2		T177	4		T244	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T10	1		T34	13		T292	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T66	18		T32	12		T204	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T64	1		T168	11		T244	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T65	12		T68	12		T33	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	384	1			T10	1		T40	15		T66	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T8	1		T293	13		T178	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T196	8		T282	15		T117	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17399	1			T3	14		T5	25		T31	141
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T294	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T34	2		T162	13		T239	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T9	15		T165	8		T166	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T46	4		T48	1		T262	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T248	10		T47	10		T171	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T5	12		T166	5		T246	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T129	2		T280	10		T295	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1028	1			T2	7		T7	19		T8	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T67	13		T163	9		T207	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T33	8		T232	11		T52	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T31	2		T67	9		T174	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T9	2		T68	11		T197	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T40	12		T43	6		T234	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T157	3		T130	9		T265	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T10	2		T34	16		T163	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T32	11		T268	11		T246	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T168	13		T194	8		T54	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T68	13		T162	1		T47	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	312	1			T10	8		T40	24		T157	20
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T293	14		T178	7		T296	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T282	14		T117	7		T119	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T31	1		T32	2		T46	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T294	2		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T10	1		T232	13		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T228	1		T275	4		T237	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T297	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T231	1		T34	17		T162	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T9	1		T165	9		T255	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T31	1		T46	8		T173	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T4	1		T9	1		T161	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T4	1		T65	4		T246	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T6	1		T183	1		T173	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T5	1		T8	1		T231	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T65	12		T67	16		T248	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1748	1			T1	31		T2	1		T7	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T6	1		T177	16		T130	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T9	1		T197	1		T53	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T31	1		T40	12		T64	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T157	2		T177	4		T244	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T43	1		T292	1		T163	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T268	1		T246	13		T258	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T10	1		T64	1		T196	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T8	1		T65	12		T66	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	506	1			T40	15		T66	7		T63	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17382	1			T3	14		T5	25		T31	141
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T10	8		T232	9		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T237	13		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T34	2		T162	13		T194	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T9	7		T165	8		T255	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T46	4		T48	1		T239	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T9	8		T166	9		T248	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T246	15		T232	7		T236	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T55	2		T280	10		T288	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T5	12		T8	2		T166	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T67	22		T163	9		T129	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1051	1			T2	7		T7	19		T37	20
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T130	19		T207	26		T239	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T9	2		T197	4		T53	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T31	2		T40	12		T34	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T157	3		T35	1		T298	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T43	6		T163	7		T174	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T268	11		T246	9		T258	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T10	2		T54	6		T229	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T68	13		T32	11		T162	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	405	1			T40	24		T157	20		T34	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T31	1		T32	2		T46	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T31	1		T231	1		T34	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	305	1			T9	17		T165	9		T166	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T46	9		T173	1		T48	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T4	1		T161	1		T204	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T4	1		T5	13		T65	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T6	1		T65	1		T183	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1376	1			T1	3		T2	8		T7	22
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T67	14		T248	1		T177	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T66	1		T33	9		T161	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T6	1		T31	3		T67	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T9	3		T68	12		T197	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T40	13		T43	7		T64	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T157	4		T177	1		T244	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T10	3		T34	17		T292	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T66	1		T32	12		T204	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T64	1		T168	14		T244	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T65	1		T68	14		T33	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	371	1			T10	9		T40	26		T66	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T8	1		T293	15		T178	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T196	1		T282	15		T117	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17531	1			T3	14		T5	25		T31	142
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T294	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T34	16		T162	11		T299	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T165	8		T255	5		T163	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T46	3		T48	1		T252	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T204	10		T248	9		T47	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T65	3		T246	13		T232	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T65	11		T129	10		T252	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1362	1			T1	28		T68	12		T58	19
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T67	14		T177	15		T163	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T66	9		T33	10		T165	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T174	1		T207	13		T53	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T68	12		T233	13		T53	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T40	11		T197	4		T129	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T157	1		T177	3		T130	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T34	12		T163	5		T174	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T66	17		T32	11		T204	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T168	10		T194	7		T54	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T65	11		T68	11		T47	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	325	1			T40	13		T66	6		T63	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T293	12		T178	5		T296	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T196	7		T282	14		T117	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T194	3		T300	10		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T10	9		T232	10		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T228	1		T275	4		T237	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T297	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T231	1		T34	3		T162	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T9	8		T165	9		T255	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T31	1		T46	9		T173	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T4	1		T9	9		T161	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T4	1		T65	1		T246	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T6	1		T183	1		T173	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T5	13		T8	3		T231	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T65	1		T67	24		T248	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1404	1			T1	3		T2	8		T7	22
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T6	1		T177	1		T130	20
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T9	3		T197	5		T53	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T31	3		T40	13		T64	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T157	4		T177	1		T244	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T43	7		T292	1		T163	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T268	12		T246	10		T258	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T10	3		T64	1		T196	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	333	1			T8	1		T65	1		T66	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	487	1			T40	26		T66	1		T63	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17517	1			T3	14		T5	25		T31	142
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T232	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T301	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T34	16		T162	11		T194	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T165	8		T255	5		T163	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T46	3		T48	1		T252	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T204	10		T248	9		T47	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T65	3		T246	13		T232	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T252	18		T55	1		T302	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T204	2		T211	18		T50	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T65	11		T67	14		T163	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1395	1			T1	28		T66	9		T68	24
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T177	15		T207	23		T254	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T53	1		T172	17		T254	21
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T40	11		T34	12		T174	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T157	1		T177	3		T233	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T163	5		T174	12		T228	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T246	12		T258	6		T130	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T196	9		T253	15		T54	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T65	11		T66	17		T68	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	424	1			T40	13		T66	6		T63	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22695

1

T1

3

T2

8

T3

14

auto[1]

auto[0]

4440

1

T1

28

T65

25

T40

24