CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] | 0 | 1 | 1 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 27135 | 1 | T1 | 31 | T2 | 8 | T3 | 14 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[ADC_CTRL_FILTER_COND_IN] | 21442 | 1 | T3 | 14 | T4 | 2 | T5 | 38 | ||||
auto[ADC_CTRL_FILTER_COND_OUT] | 5693 | 1 | T1 | 31 | T2 | 8 | T6 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 20809 | 1 | T3 | 14 | T5 | 25 | T6 | 2 | ||||
auto[1] | 6326 | 1 | T1 | 31 | T2 | 8 | T4 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 22883 | 1 | T1 | 31 | T2 | 1 | T3 | 14 | ||||
auto[1] | 4252 | 1 | T2 | 7 | T5 | 12 | T7 | 19 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 12 | 0 | 12 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
maximum | 35 | 1 | T204 | 11 | T258 | 13 | T269 | 3 | ||||
values[0] | 34 | 1 | T303 | 1 | T304 | 15 | T305 | 12 | ||||
values[1] | 717 | 1 | T65 | 12 | T40 | 35 | T67 | 28 | ||||
values[2] | 560 | 1 | T4 | 1 | T6 | 1 | T8 | 1 | ||||
values[3] | 906 | 1 | T6 | 1 | T65 | 12 | T40 | 24 | ||||
values[4] | 912 | 1 | T40 | 5 | T66 | 10 | T183 | 1 | ||||
values[5] | 659 | 1 | T68 | 25 | T183 | 1 | T166 | 6 | ||||
values[6] | 852 | 1 | T8 | 3 | T9 | 11 | T31 | 3 | ||||
values[7] | 486 | 1 | T65 | 4 | T231 | 1 | T33 | 1 | ||||
values[8] | 653 | 1 | T5 | 13 | T10 | 9 | T163 | 18 | ||||
values[9] | 3804 | 1 | T1 | 31 | T2 | 8 | T4 | 1 | ||||
minimum | 17517 | 1 | T3 | 14 | T5 | 25 | T31 | 142 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 12 | 1 | 11 | 91.67 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
maximum | 0 | 1 | 1 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 819 | 1 | T65 | 12 | T40 | 35 | T157 | 26 | ||||
values[1] | 3047 | 1 | T1 | 31 | T2 | 8 | T4 | 1 | ||||
values[2] | 907 | 1 | T65 | 12 | T40 | 24 | T43 | 7 | ||||
values[3] | 883 | 1 | T6 | 1 | T40 | 5 | T68 | 25 | ||||
values[4] | 704 | 1 | T9 | 3 | T183 | 1 | T46 | 12 | ||||
values[5] | 855 | 1 | T8 | 3 | T9 | 8 | T65 | 4 | ||||
values[6] | 530 | 1 | T10 | 9 | T33 | 1 | T204 | 3 | ||||
values[7] | 577 | 1 | T5 | 13 | T64 | 1 | T234 | 3 | ||||
values[8] | 1024 | 1 | T4 | 1 | T9 | 9 | T31 | 1 | ||||
values[9] | 272 | 1 | T204 | 11 | T174 | 4 | T258 | 13 | ||||
minimum | 17517 | 1 | T3 | 14 | T5 | 25 | T31 | 142 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 22695 | 1 | T1 | 3 | T2 | 8 | T3 | 14 | ||||
auto[1] | 4440 | 1 | T1 | 28 | T65 | 25 | T40 | 24 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins | 48 | 6 | 42 | 87.50 | 6 |
interrupt_cp | min_v_cp | cond_cp | COUNT | AT LEAST | NUMBER | STATUS |
* | [maximum] | * | -- | -- | 4 | |
* | [minimum] | [auto[ADC_CTRL_FILTER_COND_OUT]] | -- | -- | 2 |
interrupt_cp | min_v_cp | cond_cp | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | values[0] | auto[ADC_CTRL_FILTER_COND_IN] | 259 | 1 | T34 | 17 | T171 | 1 | T196 | 10 | ||||
auto[0] | values[0] | auto[ADC_CTRL_FILTER_COND_OUT] | 198 | 1 | T65 | 12 | T40 | 15 | T157 | 3 | ||||
auto[0] | values[1] | auto[ADC_CTRL_FILTER_COND_IN] | 152 | 1 | T4 | 1 | T66 | 7 | T161 | 1 | ||||
auto[0] | values[1] | auto[ADC_CTRL_FILTER_COND_OUT] | 1732 | 1 | T1 | 31 | T2 | 1 | T6 | 1 | ||||
auto[0] | values[2] | auto[ADC_CTRL_FILTER_COND_IN] | 258 | 1 | T66 | 10 | T68 | 13 | T165 | 9 | ||||
auto[0] | values[2] | auto[ADC_CTRL_FILTER_COND_OUT] | 217 | 1 | T65 | 12 | T40 | 12 | T43 | 1 | ||||
auto[0] | values[3] | auto[ADC_CTRL_FILTER_COND_IN] | 264 | 1 | T6 | 1 | T165 | 5 | T34 | 13 | ||||
auto[0] | values[3] | auto[ADC_CTRL_FILTER_COND_OUT] | 205 | 1 | T40 | 1 | T68 | 12 | T183 | 1 | ||||
auto[0] | values[4] | auto[ADC_CTRL_FILTER_COND_IN] | 202 | 1 | T183 | 1 | T46 | 8 | T166 | 1 | ||||
auto[0] | values[4] | auto[ADC_CTRL_FILTER_COND_OUT] | 179 | 1 | T9 | 1 | T210 | 12 | T232 | 13 | ||||
auto[0] | values[5] | auto[ADC_CTRL_FILTER_COND_IN] | 249 | 1 | T9 | 1 | T65 | 4 | T31 | 1 | ||||
auto[0] | values[5] | auto[ADC_CTRL_FILTER_COND_OUT] | 231 | 1 | T8 | 1 | T231 | 1 | T68 | 13 | ||||
auto[0] | values[6] | auto[ADC_CTRL_FILTER_COND_IN] | 186 | 1 | T204 | 3 | T162 | 12 | T163 | 9 | ||||
auto[0] | values[6] | auto[ADC_CTRL_FILTER_COND_OUT] | 93 | 1 | T10 | 1 | T33 | 1 | T173 | 1 | ||||
auto[0] | values[7] | auto[ADC_CTRL_FILTER_COND_IN] | 171 | 1 | T5 | 1 | T244 | 1 | T197 | 5 | ||||
auto[0] | values[7] | auto[ADC_CTRL_FILTER_COND_OUT] | 130 | 1 | T64 | 1 | T234 | 1 | T194 | 1 | ||||
auto[0] | values[8] | auto[ADC_CTRL_FILTER_COND_IN] | 301 | 1 | T4 | 1 | T9 | 1 | T161 | 2 | ||||
auto[0] | values[8] | auto[ADC_CTRL_FILTER_COND_OUT] | 308 | 1 | T31 | 1 | T32 | 12 | T63 | 10 | ||||
auto[0] | values[9] | auto[ADC_CTRL_FILTER_COND_IN] | 58 | 1 | T174 | 2 | T258 | 7 | T135 | 14 | ||||
auto[0] | values[9] | auto[ADC_CTRL_FILTER_COND_OUT] | 108 | 1 | T204 | 11 | T50 | 15 | T253 | 16 | ||||
auto[0] | minimum | auto[ADC_CTRL_FILTER_COND_IN] | 17382 | 1 | T3 | 14 | T5 | 25 | T31 | 141 | ||||
auto[1] | values[0] | auto[ADC_CTRL_FILTER_COND_IN] | 161 | 1 | T34 | 2 | T171 | 16 | T51 | 2 | ||||
auto[1] | values[0] | auto[ADC_CTRL_FILTER_COND_OUT] | 201 | 1 | T40 | 20 | T157 | 23 | T255 | 5 | ||||
auto[1] | values[1] | auto[ADC_CTRL_FILTER_COND_IN] | 127 | 1 | T232 | 11 | T239 | 9 | T298 | 4 | ||||
auto[1] | values[1] | auto[ADC_CTRL_FILTER_COND_OUT] | 1036 | 1 | T2 | 7 | T7 | 19 | T10 | 2 | ||||
auto[1] | values[2] | auto[ADC_CTRL_FILTER_COND_IN] | 294 | 1 | T68 | 11 | T165 | 8 | T166 | 9 | ||||
auto[1] | values[2] | auto[ADC_CTRL_FILTER_COND_OUT] | 138 | 1 | T40 | 12 | T43 | 6 | T34 | 12 | ||||
auto[1] | values[3] | auto[ADC_CTRL_FILTER_COND_IN] | 223 | 1 | T34 | 16 | T248 | 10 | T163 | 7 | ||||
auto[1] | values[3] | auto[ADC_CTRL_FILTER_COND_OUT] | 191 | 1 | T40 | 4 | T68 | 13 | T207 | 11 | ||||
auto[1] | values[4] | auto[ADC_CTRL_FILTER_COND_IN] | 213 | 1 | T46 | 4 | T166 | 5 | T187 | 16 | ||||
auto[1] | values[4] | auto[ADC_CTRL_FILTER_COND_OUT] | 110 | 1 | T9 | 2 | T232 | 9 | T53 | 1 | ||||
auto[1] | values[5] | auto[ADC_CTRL_FILTER_COND_IN] | 229 | 1 | T9 | 7 | T31 | 2 | T172 | 17 | ||||
auto[1] | values[5] | auto[ADC_CTRL_FILTER_COND_OUT] | 146 | 1 | T8 | 2 | T68 | 6 | T54 | 6 | ||||
auto[1] | values[6] | auto[ADC_CTRL_FILTER_COND_IN] | 177 | 1 | T162 | 13 | T163 | 9 | T129 | 3 | ||||
auto[1] | values[6] | auto[ADC_CTRL_FILTER_COND_OUT] | 74 | 1 | T10 | 8 | T47 | 1 | T306 | 11 | ||||
auto[1] | values[7] | auto[ADC_CTRL_FILTER_COND_IN] | 156 | 1 | T5 | 12 | T197 | 13 | T262 | 12 | ||||
auto[1] | values[7] | auto[ADC_CTRL_FILTER_COND_OUT] | 120 | 1 | T234 | 2 | T194 | 1 | T259 | 9 | ||||
auto[1] | values[8] | auto[ADC_CTRL_FILTER_COND_IN] | 195 | 1 | T9 | 8 | T162 | 1 | T174 | 11 | ||||
auto[1] | values[8] | auto[ADC_CTRL_FILTER_COND_OUT] | 220 | 1 | T32 | 11 | T47 | 10 | T246 | 15 | ||||
auto[1] | values[9] | auto[ADC_CTRL_FILTER_COND_IN] | 50 | 1 | T174 | 2 | T258 | 6 | T135 | 4 | ||||
auto[1] | values[9] | auto[ADC_CTRL_FILTER_COND_OUT] | 56 | 1 | T50 | 5 | T278 | 2 | T274 | 12 | ||||
auto[1] | minimum | auto[ADC_CTRL_FILTER_COND_IN] | 135 | 1 | T31 | 1 | T32 | 2 | T46 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins | 48 | 3 | 45 | 93.75 | 3 |
interrupt_cp | max_v_cp | cond_cp | COUNT | AT LEAST | NUMBER | STATUS |
[auto[0]] | [minimum] | [auto[ADC_CTRL_FILTER_COND_OUT]] | 0 | 1 | 1 | |
[auto[1]] | [values[0]] | [auto[ADC_CTRL_FILTER_COND_OUT]] | 0 | 1 | 1 | |
[auto[1]] | [minimum] | [auto[ADC_CTRL_FILTER_COND_OUT]] | 0 | 1 | 1 |
interrupt_cp | max_v_cp | cond_cp | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | maximum | auto[ADC_CTRL_FILTER_COND_IN] | 15 | 1 | T258 | 7 | T307 | 8 | - | - | ||||
auto[0] | maximum | auto[ADC_CTRL_FILTER_COND_OUT] | 13 | 1 | T204 | 11 | T269 | 2 | - | - | ||||
auto[0] | values[0] | auto[ADC_CTRL_FILTER_COND_IN] | 29 | 1 | T304 | 13 | T305 | 12 | T308 | 3 | ||||
auto[0] | values[0] | auto[ADC_CTRL_FILTER_COND_OUT] | 1 | 1 | T303 | 1 | - | - | - | - | ||||
auto[0] | values[1] | auto[ADC_CTRL_FILTER_COND_IN] | 186 | 1 | T34 | 17 | T171 | 1 | T186 | 1 | ||||
auto[0] | values[1] | auto[ADC_CTRL_FILTER_COND_OUT] | 193 | 1 | T65 | 12 | T40 | 15 | T67 | 15 | ||||
auto[0] | values[2] | auto[ADC_CTRL_FILTER_COND_IN] | 175 | 1 | T4 | 1 | T161 | 1 | T232 | 13 | ||||
auto[0] | values[2] | auto[ADC_CTRL_FILTER_COND_OUT] | 163 | 1 | T6 | 1 | T8 | 1 | T10 | 1 | ||||
auto[0] | values[3] | auto[ADC_CTRL_FILTER_COND_IN] | 230 | 1 | T6 | 1 | T66 | 7 | T68 | 13 | ||||
auto[0] | values[3] | auto[ADC_CTRL_FILTER_COND_OUT] | 218 | 1 | T65 | 12 | T40 | 12 | T43 | 1 | ||||
auto[0] | values[4] | auto[ADC_CTRL_FILTER_COND_IN] | 271 | 1 | T66 | 10 | T165 | 5 | T34 | 13 | ||||
auto[0] | values[4] | auto[ADC_CTRL_FILTER_COND_OUT] | 234 | 1 | T40 | 1 | T183 | 1 | T246 | 13 | ||||
auto[0] | values[5] | auto[ADC_CTRL_FILTER_COND_IN] | 196 | 1 | T183 | 1 | T166 | 1 | T292 | 1 | ||||
auto[0] | values[5] | auto[ADC_CTRL_FILTER_COND_OUT] | 153 | 1 | T68 | 12 | T232 | 13 | T53 | 3 | ||||
auto[0] | values[6] | auto[ADC_CTRL_FILTER_COND_IN] | 269 | 1 | T9 | 1 | T31 | 1 | T46 | 8 | ||||
auto[0] | values[6] | auto[ADC_CTRL_FILTER_COND_OUT] | 192 | 1 | T8 | 1 | T9 | 1 | T68 | 13 | ||||
auto[0] | values[7] | auto[ADC_CTRL_FILTER_COND_IN] | 130 | 1 | T65 | 4 | T204 | 3 | T232 | 2 | ||||
auto[0] | values[7] | auto[ADC_CTRL_FILTER_COND_OUT] | 153 | 1 | T231 | 1 | T33 | 1 | T173 | 1 | ||||
auto[0] | values[8] | auto[ADC_CTRL_FILTER_COND_IN] | 214 | 1 | T5 | 1 | T163 | 9 | T244 | 1 | ||||
auto[0] | values[8] | auto[ADC_CTRL_FILTER_COND_OUT] | 113 | 1 | T10 | 1 | T194 | 1 | T169 | 1 | ||||
auto[0] | values[9] | auto[ADC_CTRL_FILTER_COND_IN] | 385 | 1 | T4 | 1 | T9 | 1 | T161 | 2 | ||||
auto[0] | values[9] | auto[ADC_CTRL_FILTER_COND_OUT] | 1968 | 1 | T1 | 31 | T2 | 1 | T7 | 3 | ||||
auto[0] | minimum | auto[ADC_CTRL_FILTER_COND_IN] | 17382 | 1 | T3 | 14 | T5 | 25 | T31 | 141 | ||||
auto[1] | maximum | auto[ADC_CTRL_FILTER_COND_IN] | 6 | 1 | T258 | 6 | - | - | - | - | ||||
auto[1] | maximum | auto[ADC_CTRL_FILTER_COND_OUT] | 1 | 1 | T269 | 1 | - | - | - | - | ||||
auto[1] | values[0] | auto[ADC_CTRL_FILTER_COND_IN] | 4 | 1 | T304 | 2 | T308 | 2 | - | - | ||||
auto[1] | values[1] | auto[ADC_CTRL_FILTER_COND_IN] | 146 | 1 | T34 | 2 | T171 | 16 | T55 | 2 | ||||
auto[1] | values[1] | auto[ADC_CTRL_FILTER_COND_OUT] | 192 | 1 | T40 | 20 | T67 | 13 | T157 | 23 | ||||
auto[1] | values[2] | auto[ADC_CTRL_FILTER_COND_IN] | 103 | 1 | T232 | 11 | T51 | 2 | T239 | 9 | ||||
auto[1] | values[2] | auto[ADC_CTRL_FILTER_COND_OUT] | 119 | 1 | T10 | 2 | T67 | 9 | T33 | 8 | ||||
auto[1] | values[3] | auto[ADC_CTRL_FILTER_COND_IN] | 304 | 1 | T68 | 11 | T165 | 8 | T166 | 9 | ||||
auto[1] | values[3] | auto[ADC_CTRL_FILTER_COND_OUT] | 154 | 1 | T40 | 12 | T43 | 6 | T34 | 12 | ||||
auto[1] | values[4] | auto[ADC_CTRL_FILTER_COND_IN] | 199 | 1 | T34 | 16 | T248 | 10 | T168 | 13 | ||||
auto[1] | values[4] | auto[ADC_CTRL_FILTER_COND_OUT] | 208 | 1 | T40 | 4 | T246 | 9 | T48 | 1 | ||||
auto[1] | values[5] | auto[ADC_CTRL_FILTER_COND_IN] | 199 | 1 | T166 | 5 | T174 | 10 | T270 | 13 | ||||
auto[1] | values[5] | auto[ADC_CTRL_FILTER_COND_OUT] | 111 | 1 | T68 | 13 | T232 | 9 | T53 | 1 | ||||
auto[1] | values[6] | auto[ADC_CTRL_FILTER_COND_IN] | 247 | 1 | T9 | 7 | T31 | 2 | T46 | 4 | ||||
auto[1] | values[6] | auto[ADC_CTRL_FILTER_COND_OUT] | 144 | 1 | T8 | 2 | T9 | 2 | T68 | 6 | ||||
auto[1] | values[7] | auto[ADC_CTRL_FILTER_COND_IN] | 144 | 1 | T232 | 7 | T239 | 15 | T175 | 15 | ||||
auto[1] | values[7] | auto[ADC_CTRL_FILTER_COND_OUT] | 59 | 1 | T47 | 1 | T229 | 8 | T306 | 11 | ||||
auto[1] | values[8] | auto[ADC_CTRL_FILTER_COND_IN] | 215 | 1 | T5 | 12 | T163 | 9 | T197 | 13 | ||||
auto[1] | values[8] | auto[ADC_CTRL_FILTER_COND_OUT] | 111 | 1 | T10 | 8 | T194 | 1 | T259 | 9 | ||||
auto[1] | values[9] | auto[ADC_CTRL_FILTER_COND_IN] | 258 | 1 | T9 | 8 | T162 | 1 | T174 | 13 | ||||
auto[1] | values[9] | auto[ADC_CTRL_FILTER_COND_OUT] | 1193 | 1 | T2 | 7 | T7 | 19 | T37 | 20 | ||||
auto[1] | minimum | auto[ADC_CTRL_FILTER_COND_IN] | 135 | 1 | T31 | 1 | T32 | 2 | T46 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins | 48 | 7 | 41 | 85.42 | 7 |
wakeup_cp | min_v_cp | cond_cp | COUNT | AT LEAST | NUMBER | STATUS |
[auto[0]] | [maximum] | * | -- | -- | 2 | |
[auto[1]] | [maximum] | * | -- | -- | 2 | |
[auto[1]] | [minimum] | * | -- | -- | 2 |
wakeup_cp | min_v_cp | cond_cp | COUNT | AT LEAST | NUMBER | STATUS |
[auto[0]] | [minimum] | [auto[ADC_CTRL_FILTER_COND_OUT]] | 0 | 1 | 1 |
wakeup_cp | min_v_cp | cond_cp | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | values[0] | auto[ADC_CTRL_FILTER_COND_IN] | 216 | 1 | T34 | 3 | T171 | 17 | T196 | 1 | ||||
auto[0] | values[0] | auto[ADC_CTRL_FILTER_COND_OUT] | 240 | 1 | T65 | 1 | T40 | 22 | T157 | 25 | ||||
auto[0] | values[1] | auto[ADC_CTRL_FILTER_COND_IN] | 157 | 1 | T4 | 1 | T66 | 1 | T161 | 1 | ||||
auto[0] | values[1] | auto[ADC_CTRL_FILTER_COND_OUT] | 1382 | 1 | T1 | 3 | T2 | 8 | T6 | 1 | ||||
auto[0] | values[2] | auto[ADC_CTRL_FILTER_COND_IN] | 344 | 1 | T66 | 1 | T68 | 12 | T165 | 9 | ||||
auto[0] | values[2] | auto[ADC_CTRL_FILTER_COND_OUT] | 172 | 1 | T65 | 1 | T40 | 13 | T43 | 7 | ||||
auto[0] | values[3] | auto[ADC_CTRL_FILTER_COND_IN] | 261 | 1 | T6 | 1 | T165 | 1 | T34 | 17 | ||||
auto[0] | values[3] | auto[ADC_CTRL_FILTER_COND_OUT] | 226 | 1 | T40 | 5 | T68 | 14 | T183 | 1 | ||||
auto[0] | values[4] | auto[ADC_CTRL_FILTER_COND_IN] | 263 | 1 | T183 | 1 | T46 | 9 | T166 | 6 | ||||
auto[0] | values[4] | auto[ADC_CTRL_FILTER_COND_OUT] | 145 | 1 | T9 | 3 | T210 | 1 | T232 | 10 | ||||
auto[0] | values[5] | auto[ADC_CTRL_FILTER_COND_IN] | 264 | 1 | T9 | 8 | T65 | 1 | T31 | 3 | ||||
auto[0] | values[5] | auto[ADC_CTRL_FILTER_COND_OUT] | 192 | 1 | T8 | 3 | T231 | 1 | T68 | 7 | ||||
auto[0] | values[6] | auto[ADC_CTRL_FILTER_COND_IN] | 211 | 1 | T204 | 1 | T162 | 14 | T163 | 10 | ||||
auto[0] | values[6] | auto[ADC_CTRL_FILTER_COND_OUT] | 101 | 1 | T10 | 9 | T33 | 1 | T173 | 1 | ||||
auto[0] | values[7] | auto[ADC_CTRL_FILTER_COND_IN] | 186 | 1 | T5 | 13 | T244 | 1 | T197 | 14 | ||||
auto[0] | values[7] | auto[ADC_CTRL_FILTER_COND_OUT] | 144 | 1 | T64 | 1 | T234 | 3 | T194 | 2 | ||||
auto[0] | values[8] | auto[ADC_CTRL_FILTER_COND_IN] | 256 | 1 | T4 | 1 | T9 | 9 | T161 | 2 | ||||
auto[0] | values[8] | auto[ADC_CTRL_FILTER_COND_OUT] | 270 | 1 | T31 | 1 | T32 | 12 | T63 | 1 | ||||
auto[0] | values[9] | auto[ADC_CTRL_FILTER_COND_IN] | 67 | 1 | T174 | 3 | T258 | 7 | T135 | 10 | ||||
auto[0] | values[9] | auto[ADC_CTRL_FILTER_COND_OUT] | 81 | 1 | T204 | 1 | T50 | 11 | T253 | 1 | ||||
auto[0] | minimum | auto[ADC_CTRL_FILTER_COND_IN] | 17517 | 1 | T3 | 14 | T5 | 25 | T31 | 142 | ||||
auto[1] | values[0] | auto[ADC_CTRL_FILTER_COND_IN] | 204 | 1 | T34 | 16 | T196 | 9 | T51 | 2 | ||||
auto[1] | values[0] | auto[ADC_CTRL_FILTER_COND_OUT] | 159 | 1 | T65 | 11 | T40 | 13 | T157 | 1 | ||||
auto[1] | values[1] | auto[ADC_CTRL_FILTER_COND_IN] | 122 | 1 | T66 | 6 | T232 | 12 | T298 | 4 | ||||
auto[1] | values[1] | auto[ADC_CTRL_FILTER_COND_OUT] | 1386 | 1 | T1 | 28 | T67 | 14 | T58 | 19 | ||||
auto[1] | values[2] | auto[ADC_CTRL_FILTER_COND_IN] | 208 | 1 | T66 | 9 | T68 | 12 | T165 | 8 | ||||
auto[1] | values[2] | auto[ADC_CTRL_FILTER_COND_OUT] | 183 | 1 | T65 | 11 | T40 | 11 | T66 | 17 | ||||
auto[1] | values[3] | auto[ADC_CTRL_FILTER_COND_IN] | 226 | 1 | T165 | 4 | T34 | 12 | T248 | 9 | ||||
auto[1] | values[3] | auto[ADC_CTRL_FILTER_COND_OUT] | 170 | 1 | T68 | 11 | T207 | 10 | T170 | 7 | ||||
auto[1] | values[4] | auto[ADC_CTRL_FILTER_COND_IN] | 152 | 1 | T46 | 3 | T177 | 3 | T187 | 15 | ||||
auto[1] | values[4] | auto[ADC_CTRL_FILTER_COND_OUT] | 144 | 1 | T210 | 11 | T232 | 12 | T53 | 1 | ||||
auto[1] | values[5] | auto[ADC_CTRL_FILTER_COND_IN] | 214 | 1 | T65 | 3 | T172 | 17 | T283 | 12 | ||||
auto[1] | values[5] | auto[ADC_CTRL_FILTER_COND_OUT] | 185 | 1 | T68 | 12 | T177 | 15 | T164 | 10 | ||||
auto[1] | values[6] | auto[ADC_CTRL_FILTER_COND_IN] | 152 | 1 | T204 | 2 | T162 | 11 | T163 | 8 | ||||
auto[1] | values[6] | auto[ADC_CTRL_FILTER_COND_OUT] | 66 | 1 | T47 | 1 | T309 | 9 | T291 | 11 | ||||
auto[1] | values[7] | auto[ADC_CTRL_FILTER_COND_IN] | 141 | 1 | T197 | 4 | T233 | 11 | T245 | 14 | ||||
auto[1] | values[7] | auto[ADC_CTRL_FILTER_COND_OUT] | 106 | 1 | T170 | 6 | T254 | 21 | T310 | 7 | ||||
auto[1] | values[8] | auto[ADC_CTRL_FILTER_COND_IN] | 240 | 1 | T204 | 9 | T174 | 10 | T207 | 7 | ||||
auto[1] | values[8] | auto[ADC_CTRL_FILTER_COND_OUT] | 258 | 1 | T32 | 11 | T63 | 9 | T47 | 9 | ||||
auto[1] | values[9] | auto[ADC_CTRL_FILTER_COND_IN] | 41 | 1 | T174 | 1 | T258 | 6 | T135 | 8 | ||||
auto[1] | values[9] | auto[ADC_CTRL_FILTER_COND_OUT] | 83 | 1 | T204 | 10 | T50 | 9 | T253 | 15 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins | 48 | 4 | 44 | 91.67 | 4 |
wakeup_cp | max_v_cp | cond_cp | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] | [minimum] | * | -- | -- | 2 |
wakeup_cp | max_v_cp | cond_cp | COUNT | AT LEAST | NUMBER | STATUS |
[auto[0]] | [minimum] | [auto[ADC_CTRL_FILTER_COND_OUT]] | 0 | 1 | 1 | |
[auto[1]] | [values[0]] | [auto[ADC_CTRL_FILTER_COND_OUT]] | 0 | 1 | 1 |
wakeup_cp | max_v_cp | cond_cp | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | maximum | auto[ADC_CTRL_FILTER_COND_IN] | 8 | 1 | T258 | 7 | T307 | 1 | - | - | ||||
auto[0] | maximum | auto[ADC_CTRL_FILTER_COND_OUT] | 3 | 1 | T204 | 1 | T269 | 2 | - | - | ||||
auto[0] | values[0] | auto[ADC_CTRL_FILTER_COND_IN] | 8 | 1 | T304 | 3 | T305 | 1 | T308 | 3 | ||||
auto[0] | values[0] | auto[ADC_CTRL_FILTER_COND_OUT] | 1 | 1 | T303 | 1 | - | - | - | - | ||||
auto[0] | values[1] | auto[ADC_CTRL_FILTER_COND_IN] | 185 | 1 | T34 | 3 | T171 | 17 | T186 | 1 | ||||
auto[0] | values[1] | auto[ADC_CTRL_FILTER_COND_OUT] | 226 | 1 | T65 | 1 | T40 | 22 | T67 | 14 | ||||
auto[0] | values[2] | auto[ADC_CTRL_FILTER_COND_IN] | 138 | 1 | T4 | 1 | T161 | 1 | T232 | 12 | ||||
auto[0] | values[2] | auto[ADC_CTRL_FILTER_COND_OUT] | 152 | 1 | T6 | 1 | T8 | 1 | T10 | 3 | ||||
auto[0] | values[3] | auto[ADC_CTRL_FILTER_COND_IN] | 354 | 1 | T6 | 1 | T66 | 1 | T68 | 12 | ||||
auto[0] | values[3] | auto[ADC_CTRL_FILTER_COND_OUT] | 190 | 1 | T65 | 1 | T40 | 13 | T43 | 7 | ||||
auto[0] | values[4] | auto[ADC_CTRL_FILTER_COND_IN] | 235 | 1 | T66 | 1 | T165 | 1 | T34 | 17 | ||||
auto[0] | values[4] | auto[ADC_CTRL_FILTER_COND_OUT] | 246 | 1 | T40 | 5 | T183 | 1 | T246 | 10 | ||||
auto[0] | values[5] | auto[ADC_CTRL_FILTER_COND_IN] | 238 | 1 | T183 | 1 | T166 | 6 | T292 | 1 | ||||
auto[0] | values[5] | auto[ADC_CTRL_FILTER_COND_OUT] | 144 | 1 | T68 | 14 | T232 | 10 | T53 | 3 | ||||
auto[0] | values[6] | auto[ADC_CTRL_FILTER_COND_IN] | 294 | 1 | T9 | 8 | T31 | 3 | T46 | 9 | ||||
auto[0] | values[6] | auto[ADC_CTRL_FILTER_COND_OUT] | 188 | 1 | T8 | 3 | T9 | 3 | T68 | 7 | ||||
auto[0] | values[7] | auto[ADC_CTRL_FILTER_COND_IN] | 174 | 1 | T65 | 1 | T204 | 1 | T232 | 8 | ||||
auto[0] | values[7] | auto[ADC_CTRL_FILTER_COND_OUT] | 89 | 1 | T231 | 1 | T33 | 1 | T173 | 1 | ||||
auto[0] | values[8] | auto[ADC_CTRL_FILTER_COND_IN] | 250 | 1 | T5 | 13 | T163 | 10 | T244 | 1 | ||||
auto[0] | values[8] | auto[ADC_CTRL_FILTER_COND_OUT] | 132 | 1 | T10 | 9 | T194 | 2 | T169 | 1 | ||||
auto[0] | values[9] | auto[ADC_CTRL_FILTER_COND_IN] | 341 | 1 | T4 | 1 | T9 | 9 | T161 | 2 | ||||
auto[0] | values[9] | auto[ADC_CTRL_FILTER_COND_OUT] | 1582 | 1 | T1 | 3 | T2 | 8 | T7 | 22 | ||||
auto[0] | minimum | auto[ADC_CTRL_FILTER_COND_IN] | 17517 | 1 | T3 | 14 | T5 | 25 | T31 | 142 | ||||
auto[1] | maximum | auto[ADC_CTRL_FILTER_COND_IN] | 13 | 1 | T258 | 6 | T307 | 7 | - | - | ||||
auto[1] | maximum | auto[ADC_CTRL_FILTER_COND_OUT] | 11 | 1 | T204 | 10 | T269 | 1 | - | - | ||||
auto[1] | values[0] | auto[ADC_CTRL_FILTER_COND_IN] | 25 | 1 | T304 | 12 | T305 | 11 | T308 | 2 | ||||
auto[1] | values[1] | auto[ADC_CTRL_FILTER_COND_IN] | 147 | 1 | T34 | 16 | T196 | 9 | T55 | 1 | ||||
auto[1] | values[1] | auto[ADC_CTRL_FILTER_COND_OUT] | 159 | 1 | T65 | 11 | T40 | 13 | T67 | 14 | ||||
auto[1] | values[2] | auto[ADC_CTRL_FILTER_COND_IN] | 140 | 1 | T232 | 12 | T51 | 2 | T170 | 14 | ||||
auto[1] | values[2] | auto[ADC_CTRL_FILTER_COND_OUT] | 130 | 1 | T33 | 10 | T130 | 10 | T311 | 12 | ||||
auto[1] | values[3] | auto[ADC_CTRL_FILTER_COND_IN] | 180 | 1 | T66 | 6 | T68 | 12 | T165 | 8 | ||||
auto[1] | values[3] | auto[ADC_CTRL_FILTER_COND_OUT] | 182 | 1 | T65 | 11 | T40 | 11 | T66 | 17 | ||||
auto[1] | values[4] | auto[ADC_CTRL_FILTER_COND_IN] | 235 | 1 | T66 | 9 | T165 | 4 | T34 | 12 | ||||
auto[1] | values[4] | auto[ADC_CTRL_FILTER_COND_OUT] | 196 | 1 | T246 | 12 | T48 | 1 | T170 | 7 | ||||
auto[1] | values[5] | auto[ADC_CTRL_FILTER_COND_IN] | 157 | 1 | T177 | 3 | T174 | 12 | T270 | 12 | ||||
auto[1] | values[5] | auto[ADC_CTRL_FILTER_COND_OUT] | 120 | 1 | T68 | 11 | T232 | 12 | T53 | 1 | ||||
auto[1] | values[6] | auto[ADC_CTRL_FILTER_COND_IN] | 222 | 1 | T46 | 3 | T162 | 11 | T187 | 5 | ||||
auto[1] | values[6] | auto[ADC_CTRL_FILTER_COND_OUT] | 148 | 1 | T68 | 12 | T210 | 11 | T235 | 11 | ||||
auto[1] | values[7] | auto[ADC_CTRL_FILTER_COND_IN] | 100 | 1 | T65 | 3 | T204 | 2 | T232 | 1 | ||||
auto[1] | values[7] | auto[ADC_CTRL_FILTER_COND_OUT] | 123 | 1 | T47 | 1 | T177 | 15 | T164 | 10 | ||||
auto[1] | values[8] | auto[ADC_CTRL_FILTER_COND_IN] | 179 | 1 | T163 | 8 | T197 | 4 | T129 | 4 | ||||
auto[1] | values[8] | auto[ADC_CTRL_FILTER_COND_OUT] | 92 | 1 | T254 | 21 | T310 | 7 | T312 | 6 | ||||
auto[1] | values[9] | auto[ADC_CTRL_FILTER_COND_IN] | 302 | 1 | T204 | 9 | T174 | 11 | T207 | 7 | ||||
auto[1] | values[9] | auto[ADC_CTRL_FILTER_COND_OUT] | 1579 | 1 | T1 | 28 | T32 | 11 | T58 | 19 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins | 4 | 2 | 2 | 50.00 | 2 |
wakeup_cp | clk_gate_cp | COUNT | AT LEAST | NUMBER | STATUS |
* | [auto[1]] | -- | -- | 2 |
wakeup_cp | clk_gate_cp | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | auto[0] | 22695 | 1 | T1 | 3 | T2 | 8 | T3 | 14 | ||||
auto[1] | auto[0] | 4440 | 1 | T1 | 28 | T65 | 25 | T40 | 24 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |