Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27135

1

T1

31

T2

8

T3

14

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23075

1

T1

31

T2

8

T3

14

auto[ADC_CTRL_FILTER_COND_OUT]

4060

1

T4

1

T5

13

T8

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20811

1

T3

14

T4

2

T5

25

auto[1]

6324

1

T1

31

T2

8

T5

13

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22883

1

T1

31

T2

1

T3

14

auto[1]

4252

1

T2

7

T5

12

T7

19

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	230	1			T5	13		T40	24		T183	1
values[0]	7	1			T313	7		-	-		-	-
values[1]	703	1			T4	1		T8	3		T9	9
values[2]	734	1			T6	1		T9	8		T65	12
values[3]	845	1			T40	34		T68	24		T63	10
values[4]	683	1			T10	3		T40	1		T67	10
values[5]	3097	1			T1	31		T2	8		T4	1
values[6]	726	1			T31	3		T43	7		T66	10
values[7]	684	1			T6	1		T10	9		T68	25
values[8]	792	1			T31	1		T66	7		T204	10
values[9]	1117	1			T9	3		T65	4		T67	28
minimum	17517	1			T3	14		T5	25		T31	142

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	680	1			T4	1		T8	3		T9	9
values[1]	809	1			T6	1		T9	8		T65	12
values[2]	700	1			T40	35		T32	23		T63	10
values[3]	3150	1			T1	31		T2	8		T4	1
values[4]	826	1			T8	1		T231	1		T183	1
values[5]	614	1			T6	1		T31	3		T43	7
values[6]	626	1			T10	9		T31	1		T68	25
values[7]	907	1			T66	7		T157	21		T204	10
values[8]	1043	1			T5	13		T9	3		T40	24
values[9]	59	1			T65	4		T173	1		T236	19
minimum	17721	1			T3	14		T5	25		T31	142

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22695

1

T1

3

T2

8

T3

14

auto[1]

4440

1

T1

28

T65

25

T40

24

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T4	1		T8	1		T9	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T65	12		T66	18		T33	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T6	1		T9	1		T40	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T65	12		T161	1		T232	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T32	12		T173	1		T233	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T40	15		T63	10		T34	30
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1660	1			T1	31		T2	1		T7	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T4	1		T67	1		T46	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T231	1		T183	1		T165	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T8	1		T33	1		T166	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T6	1		T174	11		T49	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T31	1		T43	1		T66	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T10	1		T68	12		T166	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T31	1		T34	11		T171	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T163	6		T234	1		T130	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T66	7		T157	1		T204	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T9	1		T40	12		T68	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T5	1		T67	15		T183	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T236	9		T237	1		T314	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T65	4		T173	1		T314	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17471	1			T3	14		T5	25		T31	141
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T293	13		T315	1		T316	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T8	2		T9	8		T157	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T33	8		T129	3		T245	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T9	7		T40	4		T68	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T232	9		T239	15		T54	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T32	11		T232	7		T194	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T40	20		T34	18		T162	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	955	1			T2	7		T7	19		T10	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T67	9		T46	4		T255	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T47	1		T53	1		T239	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T166	5		T48	1		T207	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T174	11		T49	1		T50	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T31	2		T43	6		T162	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T10	8		T68	13		T166	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T34	12		T171	16		T174	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T163	7		T234	2		T130	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T157	20		T165	8		T249	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T9	2		T40	12		T68	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T5	12		T67	13		T163	26
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T236	10		T237	2		T317	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T241	12		T318	1		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T31	1		T32	2		T46	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T293	14		T319	6		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T40	12		T161	1		T320	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T5	1		T183	1		T173	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T313	7		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T4	1		T8	1		T9	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T65	12		T66	18		T210	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T6	1		T9	1		T40	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	307	1			T65	12		T33	11		T186	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T68	13		T197	5		T233	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T40	14		T63	10		T161	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T10	1		T32	12		T173	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T40	1		T67	1		T46	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1723	1			T1	31		T2	1		T7	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T4	1		T8	1		T173	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T183	1		T174	11		T49	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T31	1		T43	1		T66	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T6	1		T10	1		T68	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T34	11		T171	1		T174	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T163	6		T234	1		T244	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T31	1		T66	7		T204	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	294	1			T9	1		T68	13		T64	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T65	4		T67	15		T64	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17382	1			T3	14		T5	25		T31	141
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T40	12		T236	10		T321	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T5	12		T129	2		T298	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T8	2		T9	8		T157	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T129	3		T245	12		T175	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T9	7		T40	4		T246	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T33	8		T239	15		T54	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T68	11		T197	13		T232	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T40	20		T34	18		T248	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T10	2		T32	11		T35	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T67	9		T46	4		T162	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1008	1			T2	7		T7	19		T37	20
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T166	5		T47	10		T268	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T174	11		T49	1		T50	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T31	2		T43	6		T162	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T10	8		T68	13		T166	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T34	12		T171	16		T174	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T163	7		T234	2		T130	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T249	12		T175	3		T250	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T9	2		T68	6		T130	19
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T67	13		T157	20		T165	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T31	1		T32	2		T46	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T4	1		T8	3		T9	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T65	1		T66	1		T33	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T6	1		T9	8		T40	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T65	1		T161	1		T232	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T32	12		T173	1		T233	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T40	22		T63	1		T34	20
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1283	1			T1	3		T2	8		T7	22
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	333	1			T4	1		T67	10		T46	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T231	1		T183	1		T165	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T8	1		T33	1		T166	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T6	1		T174	12		T49	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T31	3		T43	7		T66	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T10	9		T68	14		T166	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T31	1		T34	13		T171	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	325	1			T163	8		T234	3		T130	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T66	1		T157	21		T204	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T9	3		T40	13		T68	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	322	1			T5	13		T67	14		T183	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T236	11		T237	3		T314	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T65	1		T173	1		T314	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17583	1			T3	14		T5	25		T31	142
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T293	15		T315	1		T316	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T157	1		T204	10		T177	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T65	11		T66	17		T33	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T68	12		T246	13		T197	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T65	11		T232	12		T54	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T32	11		T233	11		T232	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T40	13		T63	9		T34	28
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1332	1			T1	28		T58	19		T62	19
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T46	3		T255	5		T47	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T165	4		T47	1		T233	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T48	1		T207	10		T54	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T174	10		T49	1		T50	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T66	9		T162	11		T168	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T68	11		T246	12		T187	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T34	10		T174	1		T207	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T163	5		T130	11		T172	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T66	6		T204	9		T165	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T40	11		T68	12		T177	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T67	14		T163	23		T129	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T236	8		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T65	3		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T252	18		T187	5		T322	17
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T293	12		T316	14		T319	9

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T40	13		T161	1		T320	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T5	13		T183	1		T173	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T313	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T4	1		T8	3		T9	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T65	1		T66	1		T210	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T6	1		T9	8		T40	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T65	1		T33	9		T186	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T68	12		T197	14		T233	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T40	21		T63	1		T161	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T10	3		T32	12		T173	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T40	1		T67	10		T46	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1350	1			T1	3		T2	8		T7	22
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T4	1		T8	1		T173	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T183	1		T174	12		T49	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T31	3		T43	7		T66	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T6	1		T10	9		T68	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T34	13		T171	17		T174	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T163	8		T234	3		T244	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T31	1		T66	1		T204	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	340	1			T9	3		T68	7		T64	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	338	1			T65	1		T67	14		T64	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17517	1			T3	14		T5	25		T31	142
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T40	11		T236	8		T321	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T129	10		T298	1		T104	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T313	6		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T157	1		T252	18		T187	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T65	11		T66	17		T210	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T204	10		T246	13		T177	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T65	11		T33	10		T54	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T68	12		T197	4		T233	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T40	13		T63	9		T34	28
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T32	11		T211	18		T253	21
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T46	3		T255	5		T258	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1381	1			T1	28		T58	19		T62	19
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T47	9		T48	1		T207	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T174	10		T49	1		T50	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T66	9		T162	11		T168	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T68	11		T246	12		T52	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T34	10		T174	13		T164	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T163	5		T130	11		T187	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T66	6		T204	9		T249	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T68	12		T177	3		T194	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T65	3		T67	14		T165	8

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22695

1

T1

3

T2

8

T3

14

auto[1]

auto[0]

4440

1

T1

28

T65

25

T40

24