Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27135

1

T1

31

T2

8

T3

14

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23311

1

T1

31

T2

8

T3

14

auto[ADC_CTRL_FILTER_COND_OUT]

3824

1

T4

1

T5

13

T8

4

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20669

1

T3

14

T5

38

T6

1

auto[1]

6466

1

T1

31

T2

8

T4

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22883

1

T1

31

T2

1

T3

14

auto[1]

4252

1

T2

7

T5

12

T7

19

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	586	1			T9	9		T10	9		T31	1
values[0]	30	1			T231	1		T63	10		T212	1
values[1]	817	1			T6	2		T9	3		T65	12
values[2]	3000	1			T1	31		T2	8		T7	22
values[3]	615	1			T65	12		T31	3		T68	19
values[4]	685	1			T40	5		T66	10		T67	10
values[5]	878	1			T5	13		T32	23		T161	1
values[6]	661	1			T9	8		T65	4		T173	2
values[7]	737	1			T4	1		T40	1		T66	18
values[8]	850	1			T8	3		T161	1		T204	14
values[9]	1138	1			T4	1		T8	1		T10	3
minimum	17138	1			T3	14		T5	25		T31	141

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	685	1			T6	1		T65	12		T67	28
values[1]	2963	1			T1	31		T2	8		T7	22
values[2]	658	1			T65	12		T40	5		T66	10
values[3]	761	1			T67	10		T64	1		T161	1
values[4]	868	1			T5	13		T32	23		T173	1
values[5]	647	1			T4	1		T9	8		T65	4
values[6]	794	1			T40	1		T66	18		T68	24
values[7]	837	1			T4	1		T8	3		T161	1
values[8]	1013	1			T8	1		T10	12		T40	58
values[9]	108	1			T9	9		T166	10		T244	1
minimum	17801	1			T3	14		T5	25		T6	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22695

1

T1

3

T2

8

T3

14

auto[1]

4440

1

T1

28

T65

25

T40

24

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T6	1		T194	4		T249	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T65	12		T67	15		T157	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1723	1			T1	31		T2	1		T7	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T31	1		T231	1		T183	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T66	10		T46	8		T255	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T65	12		T40	1		T68	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T67	1		T64	1		T165	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T161	1		T246	14		T163	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T173	1		T177	16		T164	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T5	1		T32	12		T163	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T9	1		T65	4		T49	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T4	1		T173	1		T47	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T40	1		T68	13		T183	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T66	18		T34	28		T174	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T4	1		T161	1		T204	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T8	1		T162	12		T50	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	316	1			T10	2		T40	26		T171	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T8	1		T68	12		T64	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T166	1		T285	5		T323	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T9	1		T244	1		T194	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17451	1			T3	14		T5	25		T6	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T43	1		T130	11		T283	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T194	10		T249	12		T239	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T67	13		T157	3		T163	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1032	1			T2	7		T7	19		T31	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T33	8		T129	2		T295	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T46	4		T255	5		T197	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T40	4		T68	6		T166	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T67	9		T165	8		T248	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T246	15		T163	9		T160	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T48	1		T52	1		T172	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T5	12		T32	11		T163	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T9	7		T49	1		T207	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T47	1		T235	11		T247	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T68	11		T174	2		T130	28
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T34	14		T174	11		T53	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T34	16		T162	1		T168	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T8	2		T162	13		T50	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T10	10		T40	32		T171	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T68	13		T47	10		T234	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T166	9		T285	6		T241	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T9	8		T194	1		T306	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T9	2		T31	1		T32	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T43	6		T130	9		T324	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	416	1			T10	1		T31	1		T39	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T9	1		T244	1		T252	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T231	1		T63	10		T212	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T6	2		T9	1		T268	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T65	12		T43	1		T67	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1716	1			T1	31		T2	1		T7	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T31	1		T231	1		T183	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T31	1		T46	8		T165	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T65	12		T68	13		T204	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T66	10		T67	1		T64	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T40	1		T166	1		T246	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T248	10		T177	16		T164	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T5	1		T32	12		T161	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T9	1		T65	4		T173	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T173	1		T196	8		T253	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T40	1		T68	13		T183	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	312	1			T4	1		T66	18		T34	28
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T161	1		T204	14		T34	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T8	1		T50	15		T233	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	319	1			T4	1		T10	1		T40	26
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T8	1		T68	12		T64	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17003	1			T3	14		T5	25		T31	140
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T10	8		T166	9		T259	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T9	8		T306	13		T237	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T286	2		T281	2		T287	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T9	2		T268	11		T232	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T43	6		T67	13		T157	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1040	1			T2	7		T7	19		T37	20
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T33	8		T129	2		T299	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T31	2		T46	4		T255	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T68	6		T197	4		T55	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T67	9		T165	8		T258	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T40	4		T166	5		T246	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T248	10		T48	1		T52	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T5	12		T32	11		T163	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T9	7		T49	1		T207	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T235	11		T247	18		T280	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T68	11		T174	2		T207	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T34	14		T47	1		T174	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T34	16		T162	1		T168	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T8	2		T50	5		T53	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T10	2		T40	32		T171	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T68	13		T162	13		T47	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T31	1		T32	2		T46	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T6	1		T194	11		T249	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T65	1		T67	14		T157	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1372	1			T1	3		T2	8		T7	22
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T31	1		T231	1		T183	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T66	1		T46	9		T255	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T65	1		T40	5		T68	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T67	10		T64	1		T165	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T161	1		T246	16		T163	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T173	1		T177	1		T164	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T5	13		T32	12		T163	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T9	8		T65	1		T49	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T4	1		T173	1		T47	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T40	1		T68	12		T183	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T66	1		T34	16		T174	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T4	1		T161	1		T204	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T8	3		T162	14		T50	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	317	1			T10	12		T40	34		T171	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T8	1		T68	14		T64	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T166	10		T285	7		T323	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T9	9		T244	1		T194	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17598	1			T3	14		T5	25		T6	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T43	7		T130	10		T283	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T194	3		T249	11		T286	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T65	11		T67	14		T157	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1383	1			T1	28		T66	6		T58	19
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T33	10		T129	10		T312	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T66	9		T46	3		T255	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T65	11		T68	12		T204	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T165	8		T248	9		T258	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T246	13		T163	8		T188	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T177	15		T164	10		T48	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T32	11		T163	5		T232	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T65	3		T49	1		T207	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T47	1		T233	13		T196	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T68	12		T174	1		T130	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T66	17		T34	26		T174	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T204	12		T34	12		T168	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T162	11		T50	9		T233	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T40	24		T246	12		T177	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T68	11		T47	9		T174	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T285	4		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T284	9		T290	9		T307	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T63	9		T232	12		T245	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T130	10		T283	10		T325	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	422	1			T10	9		T31	1		T39	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T9	9		T244	1		T252	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T231	1		T63	1		T212	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T6	2		T9	3		T268	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T65	1		T43	7		T67	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1379	1			T1	3		T2	8		T7	22
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T31	1		T231	1		T183	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T31	3		T46	9		T165	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T65	1		T68	7		T204	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T66	1		T67	10		T64	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T40	5		T166	6		T246	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T248	11		T177	1		T164	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T5	13		T32	12		T161	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T9	8		T65	1		T173	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T173	1		T196	1		T253	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T40	1		T68	12		T183	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T4	1		T66	1		T34	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T161	1		T204	2		T34	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T8	3		T50	11		T233	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	346	1			T4	1		T10	3		T40	34
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T8	1		T68	14		T64	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17138	1			T3	14		T5	25		T31	141
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T252	18		T285	4		T326	5
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T252	10		T291	11		T327	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T63	9		T286	6		T287	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T232	12		T194	3		T249	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T65	11		T67	14		T157	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1377	1			T1	28		T66	6		T58	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T33	10		T211	18		T129	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T46	3		T165	4		T255	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T65	11		T68	12		T204	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T66	9		T165	8		T258	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T246	13		T163	8		T260	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T248	9		T177	15		T164	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T32	11		T163	5		T232	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T65	3		T49	1		T207	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T196	7		T253	15		T235	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T68	12		T174	1		T207	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T66	17		T34	26		T47	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T204	12		T34	12		T168	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T50	9		T233	11		T53	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T40	24		T246	12		T177	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T68	11		T162	11		T47	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22695

1

T1

3

T2

8

T3

14

auto[1]

auto[0]

4440

1

T1

28

T65

25

T40

24